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comparison services/ffs/intelsbdrv.c @ 0:75a11d740a02

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initial import of gsm-fw from freecalypso-sw rev 1033:5ab737ac3ad7
author Mychaela Falconia <falcon@freecalypso.org>
date Thu, 09 Jun 2016 00:02:41 +0000
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-1:000000000000 0:75a11d740a02
1 /******************************************************************************
2 * Flash File System (ffs)
3 * Idea, design and coding by Mads Meisner-Jensen, mmj@ti.com
4 *
5 * FFS AMD single bank low level flash driver RAM code
6 *
7 * $Id: intelsbdrv.c 1.13 Thu, 08 Jan 2004 15:05:23 +0100 tsj $
8 *
9 ******************************************************************************/
10
11 #include "../../include/config.h"
12 #include "ffs.h"
13 #include "drv.h"
14 #include "ffstrace.h"
15 #include "intctl.h"
16
17 #define INTEL_UNLOCK_SLOW 1
18
19 #undef tlw
20 #define tlw(contents)
21 #undef ttw
22 #define ttw(contents)
23
24 // Status bits for Intel flash memory devices
25 #define INTEL_STATE_MACHINE_DONE (1<<7)
26 #define FLASH_READ(addr) (*(volatile uint16 *) (addr))
27 #define FLASH_WRITE(addr, data) (*(volatile uint16 *) (addr)) = data
28
29 /******************************************************************************
30 * INTEL Single Bank Driver Functions
31 ******************************************************************************/
32 // Actually we should have disabled and enable the interrupts in this
33 // function, but when the interrupt functions are used Target don't run!
34 // Anyway, currently the interrupts are already disabled at this point thus
35 // it does not cause any problems.
36 int ffsdrv_ram_intel_sb_init(void)
37 {
38 uint32 i;
39 volatile uint16 *addr;
40
41 for (i = 0; i < dev.numblocks; i++)
42 {
43 addr = (volatile uint16 *) block2addr(i);
44
45 *addr = 0x60; // Intel Config Setup
46 *addr = 0xD0; // Intel Unlock Block
47
48 *addr = 0xFF; // Intel Read Array
49 }
50
51 return 0;
52 }
53
54 void ffsdrv_ram_intel_sb_write_halfword(volatile uint16 *addr, uint16 value)
55 {
56 uint32 cpsr;
57
58 ttw(ttr(TTrDrv, "wh(%x,%x)" NL, addr, value));
59
60 if (~*addr & value) {
61 ttw(ttr(TTrFatal, "wh(%x,%x->%x) fatal" NL, addr, *addr, value));
62 return;
63 }
64
65 cpsr = int_disable();
66 tlw(led_on(LED_WRITE));
67
68 #if (INTEL_UNLOCK_SLOW == 1)
69 *addr = 0x60; // Intel Config Setup
70 *addr = 0xD0; // Intel Unlock Block
71 #endif
72
73 *addr = 0x50; // Intel Clear Status Register
74 *addr = 0x40; // Intel program byte/word
75 *addr = value;
76 while ((*addr & 0x80) == 0)
77 ;
78 *addr = 0xFF; // Intel read array
79 tlw(led_off(LED_WRITE));
80 int_enable(cpsr);
81 }
82
83 void ffsdrv_ram_intel_sb_erase(uint8 block)
84 {
85 volatile uint16 *addr;
86 uint32 cpsr;
87 uint16 poll;
88
89 ttw(ttr(TTrDrvEra, "e(%d)" NL, block));
90
91 addr = (volatile uint16 *) block2addr(block);
92
93 cpsr = int_disable();
94 tlw(led_on(LED_ERASE));
95
96 #if (INTEL_UNLOCK_SLOW == 1)
97 *addr = 0x60; // Intel Config Setup
98 *addr = 0xD0; // Intel Unlock Block
99 #endif
100
101 *addr = 0x50; // Intel Clear Status Register
102 *addr = 0x20; // Intel Erase Setup
103 *addr = 0xD0; // Intel Erase Confirm
104 *addr = 0x70; // Intel Read Status Register
105
106 // Wait for erase to finish.
107 while ((*addr & 0x80) == 0) {
108 tlw(led_toggle(LED_ERASE));
109 // Poll interrupts, taking interrupt mask into account.
110 if (INT_REQUESTED)
111 {
112 // 1. suspend erase
113 // 2. enable interrupts
114 // .. now the interrupt code executes
115 // 3. disable interrupts
116 // 4. resume erase
117
118 tlw(led_on(LED_ERASE_SUSPEND));
119
120 *addr = 0xB0; // Intel Erase Suspend
121 *addr = 0x70; // Intel Read Status Register
122 while (((poll = *addr) & 0x80) == 0)
123 ;
124
125 // If erase is complete, exit immediately
126 if ((poll & 0x40) == 0)
127 break;
128
129 *addr = 0xFF; // Intel read array
130
131 tlw(led_off(LED_ERASE_SUSPEND));
132 int_enable(cpsr);
133
134 // Other interrupts and tasks run now...
135
136 cpsr = int_disable();
137 tlw(led_on(LED_ERASE_SUSPEND));
138
139 *addr = 0xD0; // Intel erase resume
140 // The following "extra" Read Status command is required because Intel has
141 // changed the specification of the W30 flash! (See "1.8 Volt Intel®
142 // Wireless Flash Memory with 3 Volt I/O 28F6408W30, 28F640W30, 28F320W30
143 // Specification Update")
144 *addr = 0x70; // Intel Read Status Register
145
146 tlw(led_off(LED_ERASE_SUSPEND));
147 }
148 }
149 *addr = 0xFF; // Intel read array
150
151 tlw(led_on(LED_ERASE));
152 tlw(led_off(LED_ERASE));
153 int_enable(cpsr);
154 }