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comparison L1/cfile/l1_drive.c @ 8:b36540edb046

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L1/cfile/l1_*.c: initial import from tcs211-l1-reconst
author Mychaela Falconia <falcon@freecalypso.org>
date Thu, 09 Jun 2016 05:45:03 +0000
parents 75a11d740a02
children b80f0c5016ee
comparison
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7:b7d857ebc9ca 8:b36540edb046
7 * 7 *
8 ************* Revision Controle System Header *************/ 8 ************* Revision Controle System Header *************/
9 9
10 #define L1_DRIVE_C 10 #define L1_DRIVE_C
11 11
12 #include "config.h"
13 #include "l1_confg.h" 12 #include "l1_confg.h"
14 13
15 #if (RF_FAM == 61) 14 #if (RF_FAM == 61)
16 #include "apc.h" 15 #include "apc.h"
17 #endif 16 #endif
18 17
19 #if ((W_A_WAIT_DSP_RESTART_AFTER_VOCODER_ENABLE ==1)&&(W_A_DSP_PR20037 == 1)) 18 #define W_A_DSP_PR20037 1 /* FreeCalypso */
20 #include "../../nucleus/nucleus.h" 19
20 #if ((L1M_WAIT_DSP_RESTART_AFTER_VOCODER_ENABLE ==1)&&(W_A_DSP_PR20037 == 1))
21 #include "nucleus.h"
21 #endif 22 #endif
22 #include "l1_macro.h" 23 #include "l1_macro.h"
23 #if (CODE_VERSION == SIMULATION) 24 #if (CODE_VERSION == SIMULATION)
24 #include <string.h> 25 #include <string.h>
25 #include "l1_types.h" 26 #include "l1_types.h"
104 #if (L1_AAC == 1) 105 #if (L1_AAC == 1)
105 #include "l1aac_defty.h" 106 #include "l1aac_defty.h"
106 #endif 107 #endif
107 #include "l1_defty.h" 108 #include "l1_defty.h"
108 #include "l1_varex.h" 109 #include "l1_varex.h"
109 #include "../../gpf/inc/cust_os.h" 110 #include "cust_os.h"
110 #include "l1_msgty.h" 111 #include "l1_msgty.h"
111 #if TESTMODE 112 #if TESTMODE
112 #include "l1tm_varex.h" 113 #include "l1tm_varex.h"
113 #endif 114 #endif
114 #if L2_L3_SIMUL 115 #if L2_L3_SIMUL
148 void l1dmacro_rx_fbsb (SYS_UWORD16 radio_freq); 149 void l1dmacro_rx_fbsb (SYS_UWORD16 radio_freq);
149 #endif 150 #endif
150 #endif//#if ((REL99 == 1) && (FF_BHO == 1)) 151 #endif//#if ((REL99 == 1) && (FF_BHO == 1))
151 152
152 void Cust_get_ramp_tab(API *a_ramp, UWORD8 txpwr_ramp_up, UWORD8 txpwr_ramp_down, UWORD16 radio_freq); 153 void Cust_get_ramp_tab(API *a_ramp, UWORD8 txpwr_ramp_up, UWORD8 txpwr_ramp_down, UWORD16 radio_freq);
153 #if ((ANALOG == 1) || (ANALOG == 2) || (ANALOG == 3) || (RF_FAM == 61)) 154 #if ((ANLG_FAM == 1) || (ANLG_FAM == 2) || (ANLG_FAM == 3) || (RF_FAM == 61))
154 UWORD16 Cust_get_pwr_data(UWORD8 txpwr, UWORD16 radio_freq 155 UWORD16 Cust_get_pwr_data(UWORD8 txpwr, UWORD16 radio_freq
155 #if(REL99 && FF_PRF) 156 #if(REL99 && FF_PRF)
156 ,UWORD8 number_uplink_timeslot 157 ,UWORD8 number_uplink_timeslot
157 #endif 158 #endif
158 ); 159 );
332 333
333 { 334 {
334 #endif 335 #endif
335 //######################## For DSP Rom ################################# 336 //######################## For DSP Rom #################################
336 l1s_dsp_com.dsp_db_w_ptr->d_afc = afc; // Write new afc command. 337 l1s_dsp_com.dsp_db_w_ptr->d_afc = afc; // Write new afc command.
337 #if ((ANALOG == 1) || (ANALOG == 2) || (ANALOG == 3) || (RF_FAM == 61)) 338 #if ((ANLG_FAM == 1) || (ANLG_FAM == 2) || (ANLG_FAM == 3) || (RF_FAM == 61))
338 // NOTE: In Locosto AFC loading is w.r.t DRP not in ABB 339 // NOTE: In Locosto AFC loading is w.r.t DRP not in ABB
339 l1s_dsp_com.dsp_db_w_ptr->d_ctrl_abb |= (1 << B_AFC); // Validate new afc value. 340 l1s_dsp_com.dsp_db_w_ptr->d_ctrl_abb |= (1 << B_AFC); // Validate new afc value.
340 #endif 341 #endif
341 #if (L1_EOTD==1) 342 #if (L1_EOTD==1)
342 } 343 }
374 */ 375 */
375 376
376 /*-------------------------------------------------------*/ 377 /*-------------------------------------------------------*/
377 void l1ddsp_load_txpwr(UWORD8 txpwr, UWORD16 radio_freq) 378 void l1ddsp_load_txpwr(UWORD8 txpwr, UWORD16 radio_freq)
378 { 379 {
379 #if ((ANALOG == 1) || (ANALOG == 2) || (ANALOG == 3) || (RF_FAM == 61)) 380 #if ((ANLG_FAM == 1) || (ANLG_FAM == 2) || (ANLG_FAM == 3) || (RF_FAM == 61))
380 UWORD16 pwr_data; 381 UWORD16 pwr_data;
381 #endif 382 #endif
382 383
383 //config 384 //config
384 if (l1_config.tx_pwr_code ==0) 385 if (l1_config.tx_pwr_code ==0)
397 /*** Reference to real ramp array (GSM: 15 power levels, 5-19, DCS: 16 power levels, 0-15) ***/ 398 /*** Reference to real ramp array (GSM: 15 power levels, 5-19, DCS: 16 power levels, 0-15) ***/
398 Cust_get_ramp_tab(l1s_dsp_com.dsp_ndb_ptr->a_ramp, txpwr, txpwr, radio_freq); 399 Cust_get_ramp_tab(l1s_dsp_com.dsp_ndb_ptr->a_ramp, txpwr, txpwr, radio_freq);
399 #endif 400 #endif
400 #endif 401 #endif
401 402
402 #if ((ANALOG == 1) || (ANALOG == 2) || (ANALOG == 3)) 403 #if ((ANLG_FAM == 1) || (ANLG_FAM == 2) || (ANLG_FAM == 3))
403 l1s_dsp_com.dsp_db_w_ptr->d_ctrl_abb |= ( (1 << B_RAMP) | (1 << B_BULRAMPDEL) | (1 << B_BULRAMPDEL2)); 404 l1s_dsp_com.dsp_db_w_ptr->d_ctrl_abb |= ( (1 << B_RAMP) | (1 << B_BULRAMPDEL) | (1 << B_BULRAMPDEL2));
404 #endif 405 #endif
405 406
406 #if(RF_FAM == 61) 407 #if(RF_FAM == 61)
407 l1s_dsp_com.dsp_db_w_ptr->d_ctrl_abb |= ( (1 << B_RAMP) | (1 << B_BULRAMPDEL) | (1 << B_BULRAMPDEL2)); 408 l1s_dsp_com.dsp_db_w_ptr->d_ctrl_abb |= ( (1 << B_RAMP) | (1 << B_BULRAMPDEL) | (1 << B_BULRAMPDEL2));
439 /*** Check to see if the TXPWR is to be suppressed (txpwr = NO_TXPWR) ***/ 440 /*** Check to see if the TXPWR is to be suppressed (txpwr = NO_TXPWR) ***/
440 441
441 if(txpwr == NO_TXPWR) 442 if(txpwr == NO_TXPWR)
442 { 443 {
443 /*** No transmit ***/ 444 /*** No transmit ***/
444 #if ((ANALOG == 1) || (ANALOG == 2) || (ANALOG == 3)) 445 #if ((ANLG_FAM == 1) || (ANLG_FAM == 2) || (ANLG_FAM == 3))
445 l1s_dsp_com.dsp_db_w_ptr->d_power_ctl = 0x12; // AUXAPC initialization addr 9 pg 0 Omega 446 l1s_dsp_com.dsp_db_w_ptr->d_power_ctl = 0x12; // AUXAPC initialization addr 9 pg 0 Omega
446 l1s_dsp_com.dsp_db_w_ptr->d_ctrl_abb |= ( (1 << B_RAMP) | (1 << B_BULRAMPDEL) | (1 << B_BULRAMPDEL2)); 447 l1s_dsp_com.dsp_db_w_ptr->d_ctrl_abb |= ( (1 << B_RAMP) | (1 << B_BULRAMPDEL) | (1 << B_BULRAMPDEL2));
447 #endif 448 #endif
448 449
449 #if(RF_FAM == 61 ) //Locosto without Syren Format 450 #if(RF_FAM == 61 ) //Locosto without Syren Format
462 ,1 463 ,1
463 #endif 464 #endif
464 ); 465 );
465 466
466 /*** Load power control level adding the APC address register ***/ 467 /*** Load power control level adding the APC address register ***/
467 #if ((ANALOG == 1) || (ANALOG == 2) || (ANALOG == 3)) 468 #if ((ANLG_FAM == 1) || (ANLG_FAM == 2) || (ANLG_FAM == 3))
468 l1s_dsp_com.dsp_db_w_ptr->d_power_ctl = ((pwr_data << 6) | 0x12); 469 l1s_dsp_com.dsp_db_w_ptr->d_power_ctl = ((pwr_data << 6) | 0x12);
469 // AUXAPC initialization addr 9 pg 0 Omega 470 // AUXAPC initialization addr 9 pg 0 Omega
470 #endif 471 #endif
471 472
472 #if(RF_FAM == 61) 473 #if(RF_FAM == 61)
492 #if (CODE_VERSION != SIMULATION) 493 #if (CODE_VERSION != SIMULATION)
493 Cust_get_ramp_tab(l1s_dsp_com.dsp_ndb_ptr->a_ramp, txpwr, txpwr, radio_freq); 494 Cust_get_ramp_tab(l1s_dsp_com.dsp_ndb_ptr->a_ramp, txpwr, txpwr, radio_freq);
494 #endif 495 #endif
495 #endif 496 #endif
496 497
497 #if ((ANALOG == 1) || (ANALOG == 2) || (ANALOG == 3)) 498 #if ((ANLG_FAM == 1) || (ANLG_FAM == 2) || (ANLG_FAM == 3))
498 // Setting bit 3 of this register causes DSP to write to APCDEL1 register in Omega. However, 499 // Setting bit 3 of this register causes DSP to write to APCDEL1 register in Omega. However,
499 // we are controlling this register from MCU through the SPI. Therefore, set it to 0. 500 // we are controlling this register from MCU through the SPI. Therefore, set it to 0.
500 l1s_dsp_com.dsp_db_w_ptr->d_ctrl_abb |= ( (1 << B_RAMP) | (0 << B_BULRAMPDEL) | (1 << B_BULRAMPDEL2)); 501 l1s_dsp_com.dsp_db_w_ptr->d_ctrl_abb |= ( (1 << B_RAMP) | (0 << B_BULRAMPDEL) | (1 << B_BULRAMPDEL2));
501 #endif 502 #endif
502 503
526 #if (CODE_VERSION != SIMULATION) 527 #if (CODE_VERSION != SIMULATION)
527 Cust_get_ramp_tab(l1s_dsp_com.dsp_ndb_ptr->a_ramp, txpwr, txpwr, radio_freq); 528 Cust_get_ramp_tab(l1s_dsp_com.dsp_ndb_ptr->a_ramp, txpwr, txpwr, radio_freq);
528 #endif 529 #endif
529 #endif 530 #endif
530 531
531 #if ((ANALOG == 1) || (ANALOG == 2) || (ANALOG == 3) ||(RF_FAM == 61)) 532 #if ((ANLG_FAM == 1) || (ANLG_FAM == 2) || (ANLG_FAM == 3) ||(RF_FAM == 61))
532 l1s_dsp_com.dsp_db_w_ptr->d_ctrl_abb |= ( (1 << B_RAMP) | (1 << B_BULRAMPDEL) | (1 << B_BULRAMPDEL2)); 533 l1s_dsp_com.dsp_db_w_ptr->d_ctrl_abb |= ( (1 << B_RAMP) | (1 << B_BULRAMPDEL) | (1 << B_BULRAMPDEL2));
533 #endif 534 #endif
534 } 535 }
535 } 536 }
536 } 537 }
814 #if (W_A_DSP_PR20037 == 1) 815 #if (W_A_DSP_PR20037 == 1)
815 if ((vocoder==TRUE) && (l1a_l1s_com.dedic_set.start_vocoder == TCH_VOCODER_DISABLED)) 816 if ((vocoder==TRUE) && (l1a_l1s_com.dedic_set.start_vocoder == TCH_VOCODER_DISABLED))
816 { 817 {
817 l1a_l1s_com.dedic_set.start_vocoder = TCH_VOCODER_ENABLE_REQ; 818 l1a_l1s_com.dedic_set.start_vocoder = TCH_VOCODER_ENABLE_REQ;
818 819
819 #if ( W_A_WAIT_DSP_RESTART_AFTER_VOCODER_ENABLE ==1) 820 #if ( L1M_WAIT_DSP_RESTART_AFTER_VOCODER_ENABLE ==1)
820 NU_Sleep(DSP_VOCODER_ON_TRANSITION); // DSP transition 821 NU_Sleep(DSP_VOCODER_ON_TRANSITION); // DSP transition
821 #endif 822 #endif
822 } 823 }
823 // When vocoder_on = FALSE, vocoder module is not executed 824 // When vocoder_on = FALSE, vocoder module is not executed
824 else if ((vocoder==FALSE) && (l1a_l1s_com.dedic_set.start_vocoder == TCH_VOCODER_ENABLED)) 825 else if ((vocoder==FALSE) && (l1a_l1s_com.dedic_set.start_vocoder == TCH_VOCODER_ENABLED))
932 /*-------------------------------------------------------*/ 933 /*-------------------------------------------------------*/
933 /* Parameters : */ 934 /* Parameters : */
934 /* Return : */ 935 /* Return : */
935 /* Functionality : */ 936 /* Functionality : */
936 /*-------------------------------------------------------*/ 937 /*-------------------------------------------------------*/
937 void l1ddsp_meas_read(UWORD8 nbmeas, UWORD16 *pm) 938 void l1ddsp_meas_read(UWORD8 nbmeas, UWORD8 *pm)
938 { 939 {
939 UWORD8 i; 940 UWORD8 i;
940 941
941 for (i= 0; i < nbmeas; i++) 942 for (i= 0; i < nbmeas; i++)
942 { 943 {
943 pm[i] = ((l1s_dsp_com.dsp_db_r_ptr->a_pm[i] & 0xffff)); 944 pm[i] = ((l1s_dsp_com.dsp_db_r_ptr->a_pm[i] & 0xffff) >> 5);
944 } 945 }
945 946
946 #if TESTMODE 947 #if TESTMODE
947 if(l1_config.TestMode) 948 if(l1_config.TestMode)
948 l1tm.tmode_stats.pm_recent = l1s_dsp_com.dsp_db_r_ptr->a_pm[0] & 0xffff; 949 l1tm.tmode_stats.pm_recent = l1s_dsp_com.dsp_db_r_ptr->a_pm[0] & 0xffff;
1059 // change DSP page pointer for next control 1060 // change DSP page pointer for next control
1060 l1s_dsp_com.dsp_w_page ^= 1; 1061 l1s_dsp_com.dsp_w_page ^= 1;
1061 #endif // AUDIO_SIMULATION 1062 #endif // AUDIO_SIMULATION
1062 1063
1063 #else // NOT_SIMULATION 1064 #else // NOT_SIMULATION
1064 UWORD32 dsp_task=0 ;//omaps00090550; 1065 UWORD32 dsp_task;
1065 switch(type) 1066 switch(type)
1066 { 1067 {
1067 case GSM_CTL: 1068 case GSM_CTL:
1068 // a DSP control for a GSM task 1069 // a DSP control for a GSM task
1069 //----------------------------- 1070 //-----------------------------
1070 { 1071 {
1071 // set only GSM task and GSM page 1072 // set only GSM task and GSM page
1072 dsp_task = B_GSM_TASK | l1s_dsp_com.dsp_w_page; 1073 dsp_task = B_GSM_TASK | l1s_dsp_com.dsp_w_page;
1073 // change DSP page pointer for next controle 1074 // change DSP page pointer for next controle
1074 l1s_dsp_com.dsp_w_page ^= 1; 1075 l1s_dsp_com.dsp_w_page ^= 1;
1075 } 1076 }
1076 break; 1077 break;
1077 1078
1078 case MISC_CTL: 1079 case MISC_CTL:
1079 // a DSP control for a MISC task 1080 // a DSP control for a MISC task
1080 //------------------------------ 1081 //------------------------------
1081 { 1082 {
1082 UWORD32 previous_page = l1s_dsp_com.dsp_w_page ^ 1; 1083 UWORD32 previous_page = l1s_dsp_com.dsp_w_page ^ 1;
1083 1084
1084 // set only MISC task and reset MISC page 1085 // set only MISC task and reset MISC page
1085 // (don't change GSM PAGE). 1086 // (don't change GSM PAGE).
1086 // set DSP communication Interrupt. 1087 // set DSP communication Interrupt.
1087 dsp_task = B_MISC_TASK | previous_page; 1088 dsp_task = B_MISC_TASK | previous_page;
1088 1089
1089 // Rem: DSP makes the DB header feedback even in case 1090 // Rem: DSP makes the DB header feedback even in case
1090 // of MISC task (like TONES). This created some 1091 // of MISC task (like TONES). This created some
1091 // side effect which are "work-around" passing 1092 // side effect which are "work-around" passing
1092 // the correct DB page to the DSP. 1093 // the correct DB page to the DSP.
1093 } 1094 }
1094 break;
1095
1096 case GSM_MISC_CTL:
1097 // a DSP control for a GSM and a MISC tasks
1098 //-----------------------------------------
1099 {
1100 // set GSM task, MISC task and GSM page bit.....
1101 dsp_task = B_GSM_TASK | B_MISC_TASK | l1s_dsp_com.dsp_w_page;
1102 // change DSP page pointer for next controle
1103 l1s_dsp_com.dsp_w_page ^= 1;
1104 }
1105 break; 1095 break;
1096
1097 case GSM_MISC_CTL:
1098 // a DSP control for a GSM and a MISC tasks
1099 //-----------------------------------------
1100 {
1101 // set GSM task, MISC task and GSM page bit.....
1102 dsp_task = B_GSM_TASK | B_MISC_TASK | l1s_dsp_com.dsp_w_page;
1103 // change DSP page pointer for next controle
1104 l1s_dsp_com.dsp_w_page ^= 1;
1105 }
1106 break;
1107
1108 #if 0 /* enable this after TCS211 reconstruction */
1109 default:
1110 dsp_task = 0;
1111 #endif
1106 } 1112 }
1107 1113
1108 // write dsp tasks..... 1114 // write dsp tasks.....
1109 #if (DSP >= 33) 1115 #if (DSP >= 33)
1110 l1s_dsp_com.dsp_ndb_ptr->d_dsp_page = (API) dsp_task; 1116 l1s_dsp_com.dsp_ndb_ptr->d_dsp_page = (API) dsp_task;
1200 if ((win_id == 0) || (afc_mode == L1_AFC_SCRIPT_MODE)) 1206 if ((win_id == 0) || (afc_mode == L1_AFC_SCRIPT_MODE))
1201 #else 1207 #else
1202 if (win_id == 0) 1208 if (win_id == 0)
1203 #endif 1209 #endif
1204 { 1210 {
1205 #if ((ANALOG == 1) || (ANALOG == 2) || (ANALOG == 3)) 1211 #if ((ANLG_FAM == 1) || (ANLG_FAM == 2) || (ANLG_FAM == 3))
1206 // NOTE: In Locosto AFC is in DRP not in triton 1212 // NOTE: In Locosto AFC is in DRP not in triton
1207 l1ddsp_load_afc(l1s.afc); 1213 l1ddsp_load_afc(l1s.afc);
1208 #endif 1214 #endif
1209 1215
1210 //Locosto 1216 //Locosto
1560 #else 1566 #else
1561 l1dmacro_rx_nb (radio_freq); // RX window for NB. 1567 l1dmacro_rx_nb (radio_freq); // RX window for NB.
1562 #endif 1568 #endif
1563 #endif 1569 #endif
1564 1570
1565 #if ((ANALOG == 1) || (ANALOG == 2) || (ANALOG == 3)) 1571 #if ((ANLG_FAM == 1) || (ANLG_FAM == 2) || (ANLG_FAM == 3))
1566 l1ddsp_load_afc(l1s.afc); 1572 l1ddsp_load_afc(l1s.afc);
1567 #endif 1573 #endif
1568 #if (RF_FAM == 61) 1574 #if (RF_FAM == 61)
1569 l1dtpu_load_afc(l1s.afc); 1575 l1dtpu_load_afc(l1s.afc);
1570 #endif 1576 #endif
2072 T_IQ_LOG_BUFFER iq_dump_buffer[IQ_DUMP_BUFFER_SIZE]; 2078 T_IQ_LOG_BUFFER iq_dump_buffer[IQ_DUMP_BUFFER_SIZE];
2073 2079
2074 UWORD32 iq_dump_buffer_log_index = 0; 2080 UWORD32 iq_dump_buffer_log_index = 0;
2075 UWORD32 iq_overflow_ind=0; 2081 UWORD32 iq_overflow_ind=0;
2076 2082
2077 #endif
2078
2079 void l1ddsp_read_iq_dump(UWORD8 task) 2083 void l1ddsp_read_iq_dump(UWORD8 task)
2080 { 2084 {
2081
2082 #if (L1_DEBUG_IQ_DUMP == 1)
2083 UWORD16 *p_dsp_iq_buffer_ptr; 2085 UWORD16 *p_dsp_iq_buffer_ptr;
2084 UWORD16 size; 2086 UWORD16 size;
2085 int i; 2087 int i;
2086 2088
2087 /* get the page logic*/ 2089 /* get the page logic*/
2117 memcpy(&iq_dump_buffer[iq_dump_buffer_log_index].iq_sample[0], 2119 memcpy(&iq_dump_buffer[iq_dump_buffer_log_index].iq_sample[0],
2118 p_dsp_iq_buffer_ptr, 2120 p_dsp_iq_buffer_ptr,
2119 size*2*2); /* size * 2 (as size is in IQsample pair) * 2 (to convert to bytes) */ 2121 size*2*2); /* size * 2 (as size is in IQsample pair) * 2 (to convert to bytes) */
2120 2122
2121 iq_dump_buffer_log_index = iq_dump_buffer_log_index + 1; 2123 iq_dump_buffer_log_index = iq_dump_buffer_log_index + 1;
2122 2124 }
2123 #endif 2125 #endif
2124 }
2125
2126