FreeCalypso > hg > freecalypso-citrine
comparison L1/cfile/l1_init.c @ 8:b36540edb046
L1/cfile/l1_*.c: initial import from tcs211-l1-reconst
author | Mychaela Falconia <falcon@freecalypso.org> |
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date | Thu, 09 Jun 2016 05:45:03 +0000 |
parents | 75a11d740a02 |
children | b80f0c5016ee |
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7:b7d857ebc9ca | 8:b36540edb046 |
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7 * | 7 * |
8 ************* Revision Controle System Header *************/ | 8 ************* Revision Controle System Header *************/ |
9 | 9 |
10 #define L1_INIT_C | 10 #define L1_INIT_C |
11 | 11 |
12 #include "config.h" | |
13 #include "l1_confg.h" | 12 #include "l1_confg.h" |
13 | |
14 #define W_A_DSP_PR20037 1 /* FreeCalypso */ | |
14 | 15 |
15 #if (CODE_VERSION == SIMULATION) | 16 #if (CODE_VERSION == SIMULATION) |
16 #include <string.h> | 17 #include <string.h> |
17 #include "l1_types.h" | 18 #include "l1_types.h" |
18 #include "sys_types.h" | 19 #include "sys_types.h" |
81 #include "sim_var.h" | 82 #include "sim_var.h" |
82 | 83 |
83 #else // NO SIMULATION | 84 #else // NO SIMULATION |
84 | 85 |
85 #include <string.h> | 86 #include <string.h> |
86 /* #include "tm_defs.h" */ | 87 #include "tm_defs.h" |
87 #include "l1_types.h" | 88 #include "l1_types.h" |
88 #include "sys_types.h" | 89 #include "sys_types.h" |
89 #include "../dsp/leadapi.h" | 90 #include "leadapi.h" |
90 #include "l1_const.h" | 91 #include "l1_const.h" |
91 #include "l1_macro.h" | 92 #include "l1_macro.h" |
92 #include "l1_time.h" | 93 #include "l1_time.h" |
93 #include "l1_signa.h" | 94 #include "l1_signa.h" |
94 #if (AUDIO_TASK == 1) | 95 #if (AUDIO_TASK == 1) |
96 #include "l1audio_cust.h" | 97 #include "l1audio_cust.h" |
97 #include "l1audio_defty.h" | 98 #include "l1audio_defty.h" |
98 #endif | 99 #endif |
99 | 100 |
100 | 101 |
101 #include "../../bsp/abb+spi/spi_drv.h" | 102 #include "spi_drv.h" |
102 #include "../../bsp/abb+spi/abb.h" | 103 #include "abb.h" |
103 #if (ANALOG != 11) | 104 #if (ANLG_FAM != 11) |
104 #include "../../bsp/abb+spi/abb_core_inth.h" | 105 #include "abb_core_inth.h" |
105 #endif | 106 #endif |
106 | 107 |
107 #if TESTMODE | 108 #if TESTMODE |
108 #include "l1tm_defty.h" | 109 #include "l1tm_defty.h" |
109 #endif | 110 #endif |
127 #if (L1_DYN_DSP_DWNLD == 1) | 128 #if (L1_DYN_DSP_DWNLD == 1) |
128 #include "l1_dyn_dwl_proto.h" | 129 #include "l1_dyn_dwl_proto.h" |
129 #endif | 130 #endif |
130 | 131 |
131 #include "l1_defty.h" | 132 #include "l1_defty.h" |
132 #include "../../gpf/inc/cust_os.h" | 133 #include "cust_os.h" |
133 #include "l1_msgty.h" | 134 #include "l1_msgty.h" |
134 #include "l1_varex.h" | 135 #include "l1_varex.h" |
135 #include "l1_proto.h" | 136 #include "l1_proto.h" |
136 #include "l1_mftab.h" | 137 #include "l1_mftab.h" |
137 #include "l1_tabs.h" | 138 #include "l1_tabs.h" |
139 #include "tpudrv.h" | 140 #include "tpudrv.h" |
140 | 141 |
141 #if (CHIPSET == 12) || (CHIPSET == 15) | 142 #if (CHIPSET == 12) || (CHIPSET == 15) |
142 #include "sys_inth.h" | 143 #include "sys_inth.h" |
143 #else | 144 #else |
144 #include "../../bsp/mem.h" | 145 #include "mem.h" |
145 #include "../../bsp/inth.h" | 146 #include "inth.h" |
146 #include "../../bsp/dma.h" | 147 #include "dma.h" |
147 #include "../../bsp/iq.h" | 148 #include "iq.h" |
148 #endif | 149 #endif |
149 | 150 |
150 #include "../../bsp/clkm.h" | 151 #include "clkm.h" |
151 #include "../../bsp/rhea_arm.h" | 152 #include "rhea_arm.h" |
152 #include "../../bsp/ulpd.h" | 153 #include "ulpd.h" |
153 | 154 |
154 #include "l1_proto.h" | 155 #include "l1_proto.h" |
155 | 156 |
156 #if L1_GPRS | 157 #if L1_GPRS |
157 #include "l1p_cons.h" | 158 #include "l1p_cons.h" |
195 #endif | 196 #endif |
196 | 197 |
197 #include <string.h> | 198 #include <string.h> |
198 #include <stdio.h> | 199 #include <stdio.h> |
199 | 200 |
200 #if (ANALOG == 11) | 201 #if (ANLG_FAM == 11) |
201 #include "bspTwl3029_I2c.h" | 202 #include "bspTwl3029_I2c.h" |
202 #include "bspTwl3029_Aud_Map.h" | 203 #include "bspTwl3029_Aud_Map.h" |
203 #include "bspTwl3029_Madc.h" | 204 #include "bspTwl3029_Madc.h" |
204 #endif | 205 #endif |
205 | 206 |
207 //OMAPS148175 | 208 //OMAPS148175 |
208 #include "l1_drp_if.h" | 209 #include "l1_drp_if.h" |
209 #include "drp_main.h" | 210 #include "drp_main.h" |
210 #endif | 211 #endif |
211 | 212 |
212 #if (ANALOG == 11) | 213 #if (ANLG_FAM == 11) |
213 #if (L1_MADC_ON == 1) | 214 #if (L1_MADC_ON == 1) |
214 extern BspTwl3029_MadcResults l1_madc_results; | 215 extern BspTwl3029_MadcResults l1_madc_results; |
215 extern void l1a_madc_callback(void); | 216 extern void l1a_madc_callback(void); |
216 #if(OP_L1_STANDALONE == 1 || L1_NAVC == 1 )//NAVC | 217 #if(OP_L1_STANDALONE == 1 || L1_NAVC == 1 )//NAVC |
217 extern UWORD32 Cust_navc_ctrl_status(UWORD8 d_navc_start_stop_read);//NAVC | 218 extern UWORD32 Cust_navc_ctrl_status(UWORD8 d_navc_start_stop_read);//NAVC |
377 l1s_dsp_com.dsp_ndb_ptr->a_du_1[2] = 0xffff; // NERR = 0xffff | 378 l1s_dsp_com.dsp_ndb_ptr->a_du_1[2] = 0xffff; // NERR = 0xffff |
378 l1s_dsp_com.dsp_ndb_ptr->a_fd[0] = (1<<B_FIRE1); // B_FIRE1 =1, B_FIRE0 =0 , BLUD =0 | 379 l1s_dsp_com.dsp_ndb_ptr->a_fd[0] = (1<<B_FIRE1); // B_FIRE1 =1, B_FIRE0 =0 , BLUD =0 |
379 l1s_dsp_com.dsp_ndb_ptr->a_fd[2] = 0xffff; // NERR = 0xffff | 380 l1s_dsp_com.dsp_ndb_ptr->a_fd[2] = 0xffff; // NERR = 0xffff |
380 l1s_dsp_com.dsp_ndb_ptr->d_a5mode = 0; | 381 l1s_dsp_com.dsp_ndb_ptr->d_a5mode = 0; |
381 | 382 |
382 #if ((ANALOG == 1) || (ANALOG == 2) || (ANALOG == 3) || (ANALOG == 11)) | 383 #if ((ANLG_FAM == 1) || (ANLG_FAM == 2) || (ANLG_FAM == 3) || (ANLG_FAM == 11)) |
383 l1s_dsp_com.dsp_ndb_ptr->d_tch_mode = 0x0800; // Analog base band selected = Nausica, Iota, Syren (bit 11) | 384 l1s_dsp_com.dsp_ndb_ptr->d_tch_mode = 0x0800; // Analog base band selected = Nausica, Iota, Syren (bit 11) |
384 #endif | 385 #endif |
385 | 386 |
386 #if ((ANALOG == 1) || (ANALOG == 2) || (ANALOG == 3)) | 387 #if ((ANLG_FAM == 1) || (ANLG_FAM == 2) || (ANLG_FAM == 3)) |
387 l1s_dsp_com.dsp_ndb_ptr->d_tch_mode |= (((l1_config.params.guard_bits - 4) & 0x000F) << 7); //Bit 7..10: guard bits | 388 l1s_dsp_com.dsp_ndb_ptr->d_tch_mode |= (((l1_config.params.guard_bits - 4) & 0x000F) << 7); //Bit 7..10: guard bits |
388 #endif | 389 #endif |
389 #if (ANALOG == 11) | 390 #if (ANLG_FAM == 11) |
390 l1s_dsp_com.dsp_ndb_ptr->d_tch_mode |= (((l1_config.params.guard_bits) & 0x000F) << 7); //Bit 7..10: guard bits | 391 l1s_dsp_com.dsp_ndb_ptr->d_tch_mode |= (((l1_config.params.guard_bits) & 0x000F) << 7); //Bit 7..10: guard bits |
391 #endif | 392 #endif |
392 | 393 |
393 #if (DSP == 32) | 394 #if (DSP == 32) |
394 l1s_dsp_com.dsp_ndb_ptr->d_tch_mode |= 0x2; | 395 l1s_dsp_com.dsp_ndb_ptr->d_tch_mode |= 0x2; |
412 #else | 413 #else |
413 // l1s_dsp_com.dsp_ndb_ptr->d_spcx_rif = 0x179; TBD put hte replacement here... Danny | 414 // l1s_dsp_com.dsp_ndb_ptr->d_spcx_rif = 0x179; TBD put hte replacement here... Danny |
414 | 415 |
415 #endif | 416 #endif |
416 | 417 |
417 #if (DSP == 33) || (DSP == 34) || (DSP == 35) || (DSP == 36) || (DSP == 37) || (DSP == 38) || (DSP == 39) | 418 #if (DSP >= 33) |
418 // Initialize V42b variables | 419 // Initialize V42b variables |
419 l1s_dsp_com.dsp_ndb_ptr->d_v42b_nego0 = 0; | 420 l1s_dsp_com.dsp_ndb_ptr->d_v42b_nego0 = 0; |
420 l1s_dsp_com.dsp_ndb_ptr->d_v42b_nego1 = 0; | 421 l1s_dsp_com.dsp_ndb_ptr->d_v42b_nego1 = 0; |
421 l1s_dsp_com.dsp_ndb_ptr->d_v42b_control = 0; | 422 l1s_dsp_com.dsp_ndb_ptr->d_v42b_control = 0; |
422 l1s_dsp_com.dsp_ndb_ptr->d_v42b_ratio_ind = 0; | 423 l1s_dsp_com.dsp_ndb_ptr->d_v42b_ratio_ind = 0; |
447 l1ps_dsp_com.pdsp_ndb_ptr->d_sched_mode_gprs = GSM_SCHEDULER; | 448 l1ps_dsp_com.pdsp_ndb_ptr->d_sched_mode_gprs = GSM_SCHEDULER; |
448 | 449 |
449 // Initialize the poll response buffer to "no poll request" | 450 // Initialize the poll response buffer to "no poll request" |
450 l1ps_dsp_com.pdsp_ndb_ptr->a_pu_gprs[0][0] = CS_NONE_TYPE; | 451 l1ps_dsp_com.pdsp_ndb_ptr->a_pu_gprs[0][0] = CS_NONE_TYPE; |
451 #else // L1_GPRS | 452 #else // L1_GPRS |
452 #if ((DSP == 31) || (DSP == 32) || (DSP == 33) || (DSP == 34) || (DSP == 35) || (DSP == 36) || (DSP == 37) || (DSP == 38) || (DSP == 39)) | 453 #if (DSP >= 31) |
453 l1s_dsp_com.dsp_ndb_ptr->d_sched_mode_gprs_ovly = GSM_SCHEDULER; | 454 l1s_dsp_com.dsp_ndb_ptr->d_sched_mode_gprs_ovly = GSM_SCHEDULER; |
454 #endif | 455 #endif |
455 #endif // L1_GPRS | 456 #endif // L1_GPRS |
456 | 457 |
457 // Set EOTD bit if required | 458 // Set EOTD bit if required |
473 #if ((DSP == 17)||(DSP == 32)) | 474 #if ((DSP == 17)||(DSP == 32)) |
474 l1s_dsp_com.dsp_ndb_ptr->d_tch_mode |= B_DCO_ON; | 475 l1s_dsp_com.dsp_ndb_ptr->d_tch_mode |= B_DCO_ON; |
475 #endif // DSP | 476 #endif // DSP |
476 #endif // DCO_ALGO | 477 #endif // DCO_ALGO |
477 | 478 |
478 #if ((DSP == 34) || (DSP == 35) || (DSP == 36) || (DSP == 37) || (DSP == 38)) || (DSP == 39) | 479 #if (DSP >= 34) |
479 l1s_dsp_com.dsp_ndb_ptr->a_amr_config[0] = 0; | 480 l1s_dsp_com.dsp_ndb_ptr->a_amr_config[0] = 0; |
480 l1s_dsp_com.dsp_ndb_ptr->a_amr_config[1] = 0; | 481 l1s_dsp_com.dsp_ndb_ptr->a_amr_config[1] = 0; |
481 l1s_dsp_com.dsp_ndb_ptr->a_amr_config[2] = 0; | 482 l1s_dsp_com.dsp_ndb_ptr->a_amr_config[2] = 0; |
482 l1s_dsp_com.dsp_ndb_ptr->a_amr_config[3] = 0; | 483 l1s_dsp_com.dsp_ndb_ptr->a_amr_config[3] = 0; |
483 #endif | 484 #endif |
484 | 485 |
485 #if (DSP == 35) || (DSP == 36) || (DSP == 37) || (DSP == 38) || (DSP == 39) | 486 #if (DSP >= 35) |
486 l1s_dsp_com.dsp_ndb_ptr->d_thr_onset_afs = 400; // thresh detection ONSET AFS | 487 l1s_dsp_com.dsp_ndb_ptr->d_thr_onset_afs = 400; // thresh detection ONSET AFS |
487 l1s_dsp_com.dsp_ndb_ptr->d_thr_sid_first_afs = 150; // thresh detection SID_FIRST AFS | 488 l1s_dsp_com.dsp_ndb_ptr->d_thr_sid_first_afs = 150; // thresh detection SID_FIRST AFS |
488 l1s_dsp_com.dsp_ndb_ptr->d_thr_ratscch_afs = 450; // thresh detection RATSCCH AFS | 489 l1s_dsp_com.dsp_ndb_ptr->d_thr_ratscch_afs = 450; // thresh detection RATSCCH AFS |
489 l1s_dsp_com.dsp_ndb_ptr->d_thr_update_afs = 300; // thresh detection SID_UPDATE AFS | 490 l1s_dsp_com.dsp_ndb_ptr->d_thr_update_afs = 300; // thresh detection SID_UPDATE AFS |
490 l1s_dsp_com.dsp_ndb_ptr->d_thr_onset_ahs = 200; // thresh detection ONSET AHS | 491 l1s_dsp_com.dsp_ndb_ptr->d_thr_onset_ahs = 200; // thresh detection ONSET AHS |
492 l1s_dsp_com.dsp_ndb_ptr->d_thr_ratscch_marker = 500; // thresh detection RATSCCH MARKER | 493 l1s_dsp_com.dsp_ndb_ptr->d_thr_ratscch_marker = 500; // thresh detection RATSCCH MARKER |
493 l1s_dsp_com.dsp_ndb_ptr->d_thr_sp_dgr = 3; // thresh detection SPEECH DEGRADED/NO_DATA | 494 l1s_dsp_com.dsp_ndb_ptr->d_thr_sp_dgr = 3; // thresh detection SPEECH DEGRADED/NO_DATA |
494 l1s_dsp_com.dsp_ndb_ptr->d_thr_soft_bits = 0; // thresh detection SPEECH DEGRADED/NO_DATA | 495 l1s_dsp_com.dsp_ndb_ptr->d_thr_soft_bits = 0; // thresh detection SPEECH DEGRADED/NO_DATA |
495 #endif | 496 #endif |
496 | 497 |
497 #if ((DSP==36 || (DSP == 37) || (DSP == 38) || (DSP == 39))&&(W_A_AMR_THRESHOLDS==1)) | 498 #if ((DSP >= 36) && (AMR_THRESHOLDS_WORKAROUND == 1)) |
498 // init of the afs thresholds parameters | 499 // init of the afs thresholds parameters |
499 l1s_dsp_com.dsp_ndb_ptr->a_d_macc_thr_afs[0]=0; | 500 l1s_dsp_com.dsp_ndb_ptr->a_d_macc_thr_afs[0]=0; |
500 l1s_dsp_com.dsp_ndb_ptr->a_d_macc_thr_afs[1]=0; | 501 l1s_dsp_com.dsp_ndb_ptr->a_d_macc_thr_afs[1]=0; |
501 l1s_dsp_com.dsp_ndb_ptr->a_d_macc_thr_afs[2]=0; | 502 l1s_dsp_com.dsp_ndb_ptr->a_d_macc_thr_afs[2]=0; |
502 l1s_dsp_com.dsp_ndb_ptr->a_d_macc_thr_afs[3]=0; | 503 l1s_dsp_com.dsp_ndb_ptr->a_d_macc_thr_afs[3]=0; |
503 l1s_dsp_com.dsp_ndb_ptr->a_d_macc_thr_afs[4]=0; | 504 l1s_dsp_com.dsp_ndb_ptr->a_d_macc_thr_afs[4]=0; |
504 l1s_dsp_com.dsp_ndb_ptr->a_d_macc_thr_afs[5]=0; | 505 l1s_dsp_com.dsp_ndb_ptr->a_d_macc_thr_afs[5]=0; |
505 l1s_dsp_com.dsp_ndb_ptr->a_d_macc_thr_afs[6]=0; | 506 l1s_dsp_com.dsp_ndb_ptr->a_d_macc_thr_afs[6]=0; |
506 l1s_dsp_com.dsp_ndb_ptr->a_d_macc_thr_afs[7]=1950; | 507 l1s_dsp_com.dsp_ndb_ptr->a_d_macc_thr_afs[7]=1500; |
507 | 508 |
508 // init of the ahs thresholds parameters | 509 // init of the ahs thresholds parameters |
509 l1s_dsp_com.dsp_ndb_ptr->a_d_macc_thr_ahs[0]=1500; | 510 l1s_dsp_com.dsp_ndb_ptr->a_d_macc_thr_ahs[0]=1500; |
510 l1s_dsp_com.dsp_ndb_ptr->a_d_macc_thr_ahs[1]=1500; | 511 l1s_dsp_com.dsp_ndb_ptr->a_d_macc_thr_ahs[1]=1500; |
511 l1s_dsp_com.dsp_ndb_ptr->a_d_macc_thr_ahs[2]=1500; | 512 l1s_dsp_com.dsp_ndb_ptr->a_d_macc_thr_ahs[2]=1500; |
513 l1s_dsp_com.dsp_ndb_ptr->a_d_macc_thr_ahs[4]=1500; | 514 l1s_dsp_com.dsp_ndb_ptr->a_d_macc_thr_ahs[4]=1500; |
514 l1s_dsp_com.dsp_ndb_ptr->a_d_macc_thr_ahs[5]=1500; | 515 l1s_dsp_com.dsp_ndb_ptr->a_d_macc_thr_ahs[5]=1500; |
515 #endif | 516 #endif |
516 | 517 |
517 // init of of the threshold for USF detection | 518 // init of of the threshold for USF detection |
518 #if (L1_FALSE_USF_DETECTION == 1) | 519 #if 1 /* match TCS211 object */ |
520 l1s_dsp_com.dsp_ndb_ptr->d_thr_usf_detect = 2140; | |
521 #elif (L1_FALSE_USF_DETECTION == 1) | |
519 l1s_dsp_com.dsp_ndb_ptr->d_thr_usf_detect = 2300; | 522 l1s_dsp_com.dsp_ndb_ptr->d_thr_usf_detect = 2300; |
520 #else | 523 #else |
521 l1s_dsp_com.dsp_ndb_ptr->d_thr_usf_detect = 0; | 524 l1s_dsp_com.dsp_ndb_ptr->d_thr_usf_detect = 0; |
522 #endif | 525 #endif |
523 | 526 |
524 #if (CHIPSET == 12) || (CHIPSET == 15) | 527 #if (CHIPSET == 12) || (CHIPSET == 15) |
525 #if (DSP == 35) || (DSP == 36) || (DSP == 37) || (DSP == 38) || (DSP == 39) | 528 #if (DSP >= 35) |
526 l1s_dsp_com.dsp_ndb_ptr->d_cport_init = 0; | 529 l1s_dsp_com.dsp_ndb_ptr->d_cport_init = 0; |
527 #endif | 530 #endif |
528 #endif | 531 #endif |
529 | 532 |
530 #if ((CHIPSET == 15) || (CHIPSET == 12) || (CHIPSET == 4) || ((CHIPSET == 10) && (OP_WCP == 1))) // Calypso+ or Perseus2 or locosto | 533 #if ((CHIPSET == 15) || (CHIPSET == 12) || (CHIPSET == 4) || ((CHIPSET == 10) && (OP_WCP == 1))) // Calypso+ or Perseus2 or locosto |
758 1 /* arbitrary value for arfcn*/); | 761 1 /* arbitrary value for arfcn*/); |
759 } | 762 } |
760 #endif | 763 #endif |
761 | 764 |
762 | 765 |
763 #if (ANALOG == 1) | 766 #if (ANLG_FAM == 1) |
764 // Omega registers values will be programmed at 1st DSP communication interrupt | 767 // Omega registers values will be programmed at 1st DSP communication interrupt |
765 | 768 |
766 dsp_ndb_ptr->d_debug1 = l1_config.params.debug1; // Enable f_tx delay of 400000 cyc DEBUG | 769 dsp_ndb_ptr->d_debug1 = l1_config.params.debug1; // Enable f_tx delay of 400000 cyc DEBUG |
767 dsp_ndb_ptr->d_afcctladd = l1_config.params.afcctladd; // Value at reset | 770 dsp_ndb_ptr->d_afcctladd = l1_config.params.afcctladd; // Value at reset |
768 dsp_ndb_ptr->d_vbuctrl = l1_config.params.vbuctrl; // Uplink gain amp 0dB, Sidetone gain to mute | 771 dsp_ndb_ptr->d_vbuctrl = l1_config.params.vbuctrl; // Uplink gain amp 0dB, Sidetone gain to mute |
784 dsp_ndb_ptr->d_bulgcal = 0x0000; | 787 dsp_ndb_ptr->d_bulgcal = 0x0000; |
785 dsp_ndb_ptr->d_vbctrl2 = 0x0000; | 788 dsp_ndb_ptr->d_vbctrl2 = 0x0000; |
786 dsp_ndb_ptr->d_apcdel2 = 0x0000; | 789 dsp_ndb_ptr->d_apcdel2 = 0x0000; |
787 #endif | 790 #endif |
788 #endif | 791 #endif |
789 #if (ANALOG == 2) | 792 #if (ANLG_FAM == 2) |
790 // Iota registers values will be programmed at 1st DSP communication interrupt | 793 // Iota registers values will be programmed at 1st DSP communication interrupt |
791 | 794 |
792 dsp_ndb_ptr->d_debug1 = l1_config.params.debug1; // Enable f_tx delay of 400000 cyc DEBUG | 795 dsp_ndb_ptr->d_debug1 = l1_config.params.debug1; // Enable f_tx delay of 400000 cyc DEBUG |
793 dsp_ndb_ptr->d_afcctladd = l1_config.params.afcctladd; // Value at reset | 796 dsp_ndb_ptr->d_afcctladd = l1_config.params.afcctladd; // Value at reset |
794 dsp_ndb_ptr->d_vbuctrl = l1_config.params.vbuctrl; // Uplink gain amp 0dB, Sidetone gain to mute | 797 dsp_ndb_ptr->d_vbuctrl = l1_config.params.vbuctrl; // Uplink gain amp 0dB, Sidetone gain to mute |
805 | 808 |
806 // APCDEL1 will be initialized on rach only .... | 809 // APCDEL1 will be initialized on rach only .... |
807 dsp_ndb_ptr->d_apcdel1 =l1_config.params.apcdel1; | 810 dsp_ndb_ptr->d_apcdel1 =l1_config.params.apcdel1; |
808 dsp_ndb_ptr->d_apcdel2 = l1_config.params.apcdel2; | 811 dsp_ndb_ptr->d_apcdel2 = l1_config.params.apcdel2; |
809 #endif | 812 #endif |
810 #if (ANALOG == 3) | 813 #if (ANLG_FAM == 3) |
811 // Syren registers values will be programmed at 1st DSP communication interrupt | 814 // Syren registers values will be programmed at 1st DSP communication interrupt |
812 | 815 |
813 dsp_ndb_ptr->d_debug1 = l1_config.params.debug1; // Enable f_tx delay of 400000 cyc DEBUG | 816 dsp_ndb_ptr->d_debug1 = l1_config.params.debug1; // Enable f_tx delay of 400000 cyc DEBUG |
814 dsp_ndb_ptr->d_afcctladd = l1_config.params.afcctladd; // Value at reset | 817 dsp_ndb_ptr->d_afcctladd = l1_config.params.afcctladd; // Value at reset |
815 dsp_ndb_ptr->d_vbuctrl = l1_config.params.vbuctrl; // Uplink gain amp 0dB, Sidetone gain to mute | 818 dsp_ndb_ptr->d_vbuctrl = l1_config.params.vbuctrl; // Uplink gain amp 0dB, Sidetone gain to mute |
840 dsp_ndb_ptr->d_vaud_pll = l1_config.params.vaud_pll; // Init to zero | 843 dsp_ndb_ptr->d_vaud_pll = l1_config.params.vaud_pll; // Init to zero |
841 dsp_ndb_ptr->d_togbr2 = 0; // TOGBR2 initial value handled by the DSP (this value doesn't nake any sense) | 844 dsp_ndb_ptr->d_togbr2 = 0; // TOGBR2 initial value handled by the DSP (this value doesn't nake any sense) |
842 | 845 |
843 #endif | 846 #endif |
844 | 847 |
845 #if (ANALOG == 11) | 848 #if (ANLG_FAM == 11) |
846 // The following settings need to be done only in L1 StandALoen as PSP would | 849 // The following settings need to be done only in L1 StandALoen as PSP would |
847 // do in the case of full PS Build... | 850 // do in the case of full PS Build... |
848 | 851 |
849 //Set the CTRL3 register | 852 //Set the CTRL3 register |
850 BspTwl3029_I2c_WriteSingle(BSP_TWL3029_I2C_AUD,BSP_TWL_3029_MAP_AUDIO_CTRL3_OFFSET, | 853 BspTwl3029_I2c_WriteSingle(BSP_TWL3029_I2C_AUD,BSP_TWL_3029_MAP_AUDIO_CTRL3_OFFSET, |
939 //++++++++++++++++++++++++++++++++++++++++++ | 942 //++++++++++++++++++++++++++++++++++++++++++ |
940 | 943 |
941 // flags for wake-up .... | 944 // flags for wake-up .... |
942 l1s.pw_mgr.Os_ticks_required = FALSE; | 945 l1s.pw_mgr.Os_ticks_required = FALSE; |
943 l1s.pw_mgr.frame_adjust = FALSE; | 946 l1s.pw_mgr.frame_adjust = FALSE; |
947 #if 0 /* not present in TCS211 */ | |
944 l1s.pw_mgr.wakeup_time = 0; | 948 l1s.pw_mgr.wakeup_time = 0; |
949 #endif | |
945 | 950 |
946 // variables for sleep .... | 951 // variables for sleep .... |
947 l1s.pw_mgr.sleep_duration = 0; | 952 l1s.pw_mgr.sleep_duration = 0; |
948 l1s.pw_mgr.sleep_performed = DO_NOT_SLEEP; | 953 l1s.pw_mgr.sleep_performed = DO_NOT_SLEEP; |
949 l1s.pw_mgr.modules_status = 0; // all clocks ON | 954 l1s.pw_mgr.modules_status = 0; // all clocks ON |
950 l1s.pw_mgr.paging_scheduled = FALSE; | 955 l1s.pw_mgr.paging_scheduled = FALSE; |
951 | 956 |
952 #if 0 /* removed in FreeCalypso */ | 957 #if 0 /* not present in TCS211 */ |
953 // variable for afc bypass mode | 958 // variable for afc bypass mode |
954 l1s.pw_mgr.afc_bypass_mode = AFC_BYPASS_MODE; | 959 l1s.pw_mgr.afc_bypass_mode = AFC_BYPASS_MODE; |
955 #endif | 960 #endif |
956 | 961 |
957 // 32 Khz gauging .... | 962 // 32 Khz gauging .... |
958 l1s.pw_mgr.gaug_count = 0; | 963 l1s.pw_mgr.gaug_count = 0; |
959 l1s.pw_mgr.enough_gaug = FALSE; | 964 l1s.pw_mgr.enough_gaug = FALSE; |
960 //Nina modify to save power, not forbid deep sleep, only force gauging in next paging | 965 //Nina modify to save power, not forbid deep sleep, only force gauging in next paging |
966 #if 0 /* not present in TCS211 */ | |
961 l1s.force_gauging_next_paging_due_to_CCHR = 0; | 967 l1s.force_gauging_next_paging_due_to_CCHR = 0; |
968 #endif | |
962 l1s.pw_mgr.gauging_task = INACTIVE; | 969 l1s.pw_mgr.gauging_task = INACTIVE; |
963 | 970 |
964 // GAUGING duration | 971 // GAUGING duration |
965 #if (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 10) || (CHIPSET == 11) || (CHIPSET == 12) || (CHIPSET == 15) | 972 #if (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 10) || (CHIPSET == 11) || (CHIPSET == 12) || (CHIPSET == 15) |
966 if (l1_config.dpll <8 ) | 973 if (l1_config.dpll <8 ) |
1016 l1s.pw_mgr.c_delta_hf_update = C_DELTA_HF_UPDATE; | 1023 l1s.pw_mgr.c_delta_hf_update = C_DELTA_HF_UPDATE; |
1017 #elif ((CHIPSET == 4) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 10) || (CHIPSET == 11) || (CHIPSET == 12) || (CHIPSET == 15)) | 1024 #elif ((CHIPSET == 4) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 10) || (CHIPSET == 11) || (CHIPSET == 12) || (CHIPSET == 15)) |
1018 // 78000/32.7712768 = 2380.13308 | 1025 // 78000/32.7712768 = 2380.13308 |
1019 l1s.pw_mgr.c_clk_min = (UWORD32)((l1_config.dpll*MCUCLK)/LF_100PPM); | 1026 l1s.pw_mgr.c_clk_min = (UWORD32)((l1_config.dpll*MCUCLK)/LF_100PPM); |
1020 // 0.13308*2^16 | 1027 // 0.13308*2^16 |
1021 l1s.pw_mgr.c_clk_init_min =(UWORD32) ((UWORD32)((UWORD32)(((UWORD32)(l1_config.dpll*MCUCLK))- | 1028 #if 0 /* LoCosto version */ |
1029 l1s.pw_mgr.c_clk_init_min =(UWORD32) ((UWORD32)((UWORD32)(((UWORD32)(l1_config.dpll*MCUCLK))- | |
1022 (l1s.pw_mgr.c_clk_min*LF_100PPM))* | 1030 (l1s.pw_mgr.c_clk_min*LF_100PPM))* |
1023 65536)/LF_100PPM); //omaps00090550 | 1031 65536)/LF_100PPM); //omaps00090550 |
1024 | 1032 #else /* TSM30 version */ |
1033 l1s.pw_mgr.c_clk_init_min = (UWORD32)(((double)(l1_config.dpll*MCUCLK)- | |
1034 (double)(l1s.pw_mgr.c_clk_min*LF_100PPM))* | |
1035 65536)/LF_100PPM; | |
1036 #endif | |
1025 // 78000/32.751616 = 2381.561875 | 1037 // 78000/32.751616 = 2381.561875 |
1026 l1s.pw_mgr.c_clk_max = (UWORD32)((l1_config.dpll*MCUCLK)/LF_500PPM); //omaps00090550 | 1038 l1s.pw_mgr.c_clk_max = (UWORD32)((l1_config.dpll*MCUCLK)/LF_500PPM); //omaps00090550 |
1027 // 0.561875*2^16 | 1039 // 0.561875*2^16 |
1028 l1s.pw_mgr.c_clk_init_max =(UWORD32)((UWORD32)(((double)(l1_config.dpll*MCUCLK)- | 1040 #if 0 /* LoCosto version */ |
1041 l1s.pw_mgr.c_clk_init_max =(UWORD32)((UWORD32)(((double)(l1_config.dpll*MCUCLK)- | |
1029 (double)(l1s.pw_mgr.c_clk_max*LF_500PPM))* | 1042 (double)(l1s.pw_mgr.c_clk_max*LF_500PPM))* |
1030 65536)/LF_500PPM);//omaps00090550 | 1043 65536)/LF_500PPM);//omaps00090550 |
1031 | 1044 #else /* TSM30 version */ |
1045 l1s.pw_mgr.c_clk_init_max =(UWORD32)(((double)(l1_config.dpll*MCUCLK)- | |
1046 (double)(l1s.pw_mgr.c_clk_max*LF_500PPM))* | |
1047 65536)/LF_500PPM; | |
1048 #endif | |
1032 // remember hf is expressed in nbr of clock in hz (ex 65Mhz,104Mhz) | 1049 // remember hf is expressed in nbr of clock in hz (ex 65Mhz,104Mhz) |
1033 l1s.pw_mgr.c_delta_hf_acquis =(UWORD32) (((GAUG_IN_32T/LF)-(GAUG_IN_32T/LF_50PPM))*(l1_config.dpll*MCUCLK));//omaps00090550 | 1050 l1s.pw_mgr.c_delta_hf_acquis =(UWORD32) (((GAUG_IN_32T/LF)-(GAUG_IN_32T/LF_50PPM))*(l1_config.dpll*MCUCLK));//omaps00090550 |
1034 l1s.pw_mgr.c_delta_hf_update =(UWORD32)( ((GAUG_IN_32T/LF)-(GAUG_IN_32T/LF_6PPM ))*(l1_config.dpll*MCUCLK));//omaps00090550 | 1051 l1s.pw_mgr.c_delta_hf_update =(UWORD32)( ((GAUG_IN_32T/LF)-(GAUG_IN_32T/LF_6PPM ))*(l1_config.dpll*MCUCLK));//omaps00090550 |
1035 #endif | 1052 #endif |
1036 | 1053 |
1076 } | 1093 } |
1077 } | 1094 } |
1078 l1s.frame_count = 0; | 1095 l1s.frame_count = 0; |
1079 l1s.forbid_meas = 0; | 1096 l1s.forbid_meas = 0; |
1080 #if L1_GPRS | 1097 #if L1_GPRS |
1098 #if 0 /* not present in TCS211 */ | |
1081 l1s.tcr_prog_done=0; | 1099 l1s.tcr_prog_done=0; |
1100 #endif | |
1082 #endif | 1101 #endif |
1083 #if (AUDIO_DEBUG == 1) | 1102 #if (AUDIO_DEBUG == 1) |
1084 audio_reg_read_status=0; | 1103 audio_reg_read_status=0; |
1085 #endif | 1104 #endif |
1086 // MFTAB management variables... | 1105 // MFTAB management variables... |
1116 l1s.toa_update = FALSE; | 1135 l1s.toa_update = FALSE; |
1117 #endif | 1136 #endif |
1118 #endif | 1137 #endif |
1119 | 1138 |
1120 #if (L1_GPRS == 1) | 1139 #if (L1_GPRS == 1) |
1140 #if 0 /* not present in TCS211 */ | |
1121 l1s.algo_change_synchro_active = FALSE; | 1141 l1s.algo_change_synchro_active = FALSE; |
1142 #endif | |
1122 #endif | 1143 #endif |
1123 | 1144 |
1124 #if (L1_RF_KBD_FIX == 1) | 1145 #if (L1_RF_KBD_FIX == 1) |
1125 l1s.total_kbd_on_time = 5000; | 1146 l1s.total_kbd_on_time = 5000; |
1126 l1s.correction_ratio = 1; | 1147 l1s.correction_ratio = 1; |
1173 l1s.actual_time.block_id = 0; | 1194 l1s.actual_time.block_id = 0; |
1174 l1s.next_time.block_id = 0; | 1195 l1s.next_time.block_id = 0; |
1175 l1s.next_plus_time = l1s.next_time; | 1196 l1s.next_plus_time = l1s.next_time; |
1176 l1s_increment_time(&(l1s.next_plus_time),1); | 1197 l1s_increment_time(&(l1s.next_plus_time),1); |
1177 l1s.ctrl_synch_before = FALSE; | 1198 l1s.ctrl_synch_before = FALSE; |
1178 l1s.next_gauging_scheduled_for_PNP= 0; | 1199 #if 0 /* not present in TCS211 */ |
1200 l1s.next_gauging_scheduled_for_PNP= 0; | |
1201 #endif | |
1179 #endif | 1202 #endif |
1180 } | 1203 } |
1181 | 1204 |
1182 // TXPWR management. | 1205 // TXPWR management. |
1183 //------------------- | 1206 //------------------- |
1212 l1s.version.dsp_patch_version = 0; | 1235 l1s.version.dsp_patch_version = 0; |
1213 l1s.version.dsp_checksum = 0; // checksum patch+code DSP | 1236 l1s.version.dsp_checksum = 0; // checksum patch+code DSP |
1214 | 1237 |
1215 l1s.version.mcu_tcs_program_release = PROGRAM_RELEASE_VERSION; | 1238 l1s.version.mcu_tcs_program_release = PROGRAM_RELEASE_VERSION; |
1216 l1s.version.mcu_tcs_internal = INTERNAL_VERSION; | 1239 l1s.version.mcu_tcs_internal = INTERNAL_VERSION; |
1217 l1s.version.mcu_tcs_official = MAINTENANCE_VERSION; | 1240 l1s.version.mcu_tcs_official = OFFICIAL_VERSION; |
1218 | 1241 |
1219 #if TESTMODE | 1242 #if TESTMODE |
1220 l1s.version.mcu_tm_version = TESTMODEVERSION; | 1243 l1s.version.mcu_tm_version = TESTMODEVERSION; |
1221 #else | 1244 #else |
1222 l1s.version.mcu_tm_version = 0; | 1245 l1s.version.mcu_tm_version = 0; |
1390 //---------------------- | 1413 //---------------------- |
1391 l1a_l1s_com.dedic_set.aset = NULL; | 1414 l1a_l1s_com.dedic_set.aset = NULL; |
1392 l1a_l1s_com.dedic_set.fset = NULL; | 1415 l1a_l1s_com.dedic_set.fset = NULL; |
1393 l1a_l1s_com.dedic_set.SignalCode = 0; | 1416 l1a_l1s_com.dedic_set.SignalCode = 0; |
1394 l1a_l1s_com.dedic_set.sync_tch = 0; | 1417 l1a_l1s_com.dedic_set.sync_tch = 0; |
1418 l1a_l1s_com.dedic_set.reset_facch = FALSE; | |
1395 l1a_l1s_com.dedic_set.stop_tch = 0; | 1419 l1a_l1s_com.dedic_set.stop_tch = 0; |
1396 l1a_l1s_com.dedic_set.reset_facch = FALSE; | |
1397 #if (FF_L1_TCH_VOCODER_CONTROL) | 1420 #if (FF_L1_TCH_VOCODER_CONTROL) |
1398 l1a_l1s_com.dedic_set.reset_sacch = FALSE; | 1421 l1a_l1s_com.dedic_set.reset_sacch = FALSE; |
1399 #if (L1_VOCODER_IF_CHANGE == 0) | 1422 #if (L1_VOCODER_IF_CHANGE == 0) |
1400 l1a_l1s_com.dedic_set.vocoder_on = TRUE; | 1423 l1a_l1s_com.dedic_set.vocoder_on = TRUE; |
1401 #if (W_A_DSP_PR20037 == 1) | 1424 #if (W_A_DSP_PR20037 == 1) |
1402 l1a_l1s_com.dedic_set.start_vocoder = TCH_VOCODER_ENABLE_REQ; | 1425 l1a_l1s_com.dedic_set.start_vocoder = TCH_VOCODER_ENABLE_REQ; |
1403 #else // W_A_DSP_PR20037 == 0 | 1426 #else // W_A_DSP_PR20037 == 0 |
1404 l1a_l1s_com.dedic_set.start_vocoder = FALSE; | 1427 l1a_l1s_com.dedic_set.start_vocoder = FALSE; |
1405 #endif // W_A_DSP_PR20037 | 1428 #endif // W_A_DSP_PR20037 |
1406 #else // L1_VOCODER_IF_CHANGE | 1429 #else // L1_VOCODER_IF_CHANGE |
1407 l1a_l1s_com.dedic_set.vocoder_on = FALSE; | 1430 l1a_l1s_com.dedic_set.vocoder_on = FALSE; |
1408 l1a_l1s_com.dedic_set.start_vocoder = TCH_VOCODER_RESET_COMMAND; | 1431 l1a_l1s_com.dedic_set.start_vocoder = TCH_VOCODER_RESET_COMMAND; |
1409 #endif // L1_VOCODER_IF_CHANGE | 1432 #endif // L1_VOCODER_IF_CHANGE |
1410 #endif // FF_L1_TCH_VOCODER_CONTROL | 1433 #endif // FF_L1_TCH_VOCODER_CONTROL |
1411 | 1434 |
1412 l1a_l1s_com.dedic_set.radio_freq = 0; | 1435 l1a_l1s_com.dedic_set.radio_freq = 0; |
1413 l1a_l1s_com.dedic_set.radio_freq_d = 0; | 1436 l1a_l1s_com.dedic_set.radio_freq_d = 0; |
1414 l1a_l1s_com.dedic_set.radio_freq_dd = 0; | 1437 l1a_l1s_com.dedic_set.radio_freq_dd = 0; |
1609 /*-------------------------------------------------------------*/ | 1632 /*-------------------------------------------------------------*/ |
1610 /* FUNCTION: l1_drp_wrapper_init */ | 1633 /* FUNCTION: l1_drp_wrapper_init */ |
1611 | 1634 |
1612 /*-------------------------------------------------------------*/ | 1635 /*-------------------------------------------------------------*/ |
1613 | 1636 |
1637 #if(RF_FAM == 61) | |
1614 void l1_drp_wrapper_init (void) | 1638 void l1_drp_wrapper_init (void) |
1615 { | 1639 { |
1616 #if(RF_FAM == 61) | |
1617 l1ddsp_apc_load_apcctrl2(l1_config.params.apcctrl2); | 1640 l1ddsp_apc_load_apcctrl2(l1_config.params.apcctrl2); |
1618 #endif | 1641 } |
1619 | 1642 #endif |
1620 } | |
1621 | 1643 |
1622 /*-------------------------------------------------------------*/ | 1644 /*-------------------------------------------------------------*/ |
1623 /* FUNCTION: l1_drp_init */ | 1645 /* FUNCTION: l1_drp_init */ |
1624 /* Params: Void */ | 1646 /* Params: Void */ |
1625 /* | 1647 /* |
1764 #if(L1_FF_MULTIBAND == 0) | 1786 #if(L1_FF_MULTIBAND == 0) |
1765 l1_config.std.id = mmi_l1_config->std; | 1787 l1_config.std.id = mmi_l1_config->std; |
1766 #endif | 1788 #endif |
1767 | 1789 |
1768 l1_config.tx_pwr_code = mmi_l1_config->tx_pwr_code; | 1790 l1_config.tx_pwr_code = mmi_l1_config->tx_pwr_code; |
1769 #if IDS | 1791 #if 0 /* not present in TCS211 */ |
1770 l1_config.ids_enable = mmi_l1_config->ids_enable; | 1792 #if IDS |
1771 #endif | 1793 l1_config.ids_enable = mmi_l1_config->ids_enable; |
1772 l1_config.facch_test.enable = mmi_l1_config->facch_test.enable; | 1794 #endif |
1773 l1_config.facch_test.period = mmi_l1_config->facch_test.period; | 1795 l1_config.facch_test.enable = mmi_l1_config->facch_test.enable; |
1796 l1_config.facch_test.period = mmi_l1_config->facch_test.period; | |
1797 #endif | |
1774 l1_config.dwnld = mmi_l1_config->dwnld; | 1798 l1_config.dwnld = mmi_l1_config->dwnld; |
1775 | 1799 |
1776 #if TESTMODE | 1800 #if TESTMODE |
1777 // Initialize TestMode params: must be done after Omega power-on | 1801 // Initialize TestMode params: must be done after Omega power-on |
1778 l1_config.TestMode = FALSE; | 1802 l1_config.TestMode = FALSE; |
1849 // Initialize statistics mode....... | 1873 // Initialize statistics mode....... |
1850 //================================================= | 1874 //================================================= |
1851 #if TRACE_TYPE==3 | 1875 #if TRACE_TYPE==3 |
1852 reset_stats(); | 1876 reset_stats(); |
1853 #endif | 1877 #endif |
1854 #if(OP_L1_STANDALONE == 1 || L1_NAVC == 1 )//NAVC | 1878 #if(OP_L1_STANDALONE == 1 || L1_NAVC == 1 )//NAVC |
1855 Cust_navc_ctrl_status(1);//start - NAVC | 1879 Cust_navc_ctrl_status(1);//start - NAVC |
1856 #endif//end of (OP_L1_STANDALONE == 1 || L1_NAVC == 1 ) | 1880 #endif//end of (OP_L1_STANDALONE == 1 || L1_NAVC == 1 ) |
1857 | 1881 |
1858 #if FEATURE_TCH_REROUTE | |
1859 feature_tch_reroute_init(); | |
1860 #endif | |
1861 } | 1882 } |
1862 | 1883 |
1863 /*-------------------------------------------------------*/ | 1884 /*-------------------------------------------------------*/ |
1864 /* l1_initialize_for_recovery */ | 1885 /* l1_initialize_for_recovery */ |
1865 /*-------------------------------------------------------*/ | 1886 /*-------------------------------------------------------*/ |
1886 //Required for interworking with Isample 2.1 and Isample 2.5 | 1907 //Required for interworking with Isample 2.1 and Isample 2.5 |
1887 Cust_init_params_drp(); | 1908 Cust_init_params_drp(); |
1888 drp_efuse_init(); | 1909 drp_efuse_init(); |
1889 #endif | 1910 #endif |
1890 l1_tpu_init(); | 1911 l1_tpu_init(); |
1891 wait_ARM_cycles(convert_nanosec_to_cycles(11000000)); // wait of 5.5 msec | 1912 #if 0 /* not in TCS211 */ |
1913 wait_ARM_cycles(convert_nanosec_to_cycles(11000000)); // wait of 5.5 msec | |
1914 #endif | |
1892 l1_dsp_init(); | 1915 l1_dsp_init(); |
1893 l1_initialize_var(); | 1916 l1_initialize_var(); |
1894 | 1917 |
1895 #if L1_GPRS | 1918 #if L1_GPRS |
1896 initialize_l1pvar(); | 1919 initialize_l1pvar(); |
1909 * (volatile UWORD16 *) INTH_IT_REG &= ~(1 << IQ_FRAME); // clear TDMA IRQ | 1932 * (volatile UWORD16 *) INTH_IT_REG &= ~(1 << IQ_FRAME); // clear TDMA IRQ |
1910 #endif | 1933 #endif |
1911 | 1934 |
1912 } | 1935 } |
1913 #endif | 1936 #endif |
1914 | |
1915 | |
1916 |