FreeCalypso > hg > freecalypso-citrine
comparison L1/cfile/l1_pwmgr.c @ 8:b36540edb046
L1/cfile/l1_*.c: initial import from tcs211-l1-reconst
author | Mychaela Falconia <falcon@freecalypso.org> |
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date | Thu, 09 Jun 2016 05:45:03 +0000 |
parents | 75a11d740a02 |
children | b80f0c5016ee |
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7:b7d857ebc9ca | 8:b36540edb046 |
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5 * Filename l1_pwmgr.c | 5 * Filename l1_pwmgr.c |
6 * Copyright 2003 (C) Texas Instruments | 6 * Copyright 2003 (C) Texas Instruments |
7 * | 7 * |
8 ************* Revision Controle System Header *************/ | 8 ************* Revision Controle System Header *************/ |
9 | 9 |
10 // pinghua add these programe code section to put some sleep code into internal ram. | |
11 /* | |
12 * FreeCalypso: the Leonardo binary object version puts all of l1_pwmgr | |
13 * into the regular run-from-flash text section, so we'll do the same | |
14 * for now. | |
15 */ | |
16 #if 0 | |
17 #pragma CODE_SECTION(l1s_sleep_manager,".emifconf") | |
18 #pragma CODE_SECTION(EMIF_SetConfReg,".emifconf") | |
19 #pragma CODE_SECTION(audio_madc_sleep,".emifconf") | |
20 #pragma CODE_SECTION(Check_Peripheral_App,".emifconf") | |
21 #pragma CODE_SECTION(DBB_Configure_DS,".emifconf") | |
22 #pragma CODE_SECTION(DBB_Wakeup_DS,".emifconf") | |
23 #pragma CODE_SECTION(l1ctl_pgm_clk32,".emifconf") | |
24 #pragma CODE_SECTION(l1ctl_gauging,".emifconf") | |
25 #pragma CODE_SECTION(GAUGING_Handler,".emifconf") | |
26 #pragma CODE_SECTION(l1s_get_HWTimers_ticks,".emifconf") | |
27 #pragma CODE_SECTION(l1s_adapt_traffic_controller,".emifconf") | |
28 #pragma CODE_SECTION(l1s_wakeup,".emifconf") | |
29 #pragma CODE_SECTION(l1s_wakeup_adjust,".emifconf") | |
30 #pragma CODE_SECTION(l1s_compute_wakeup_ticks,".emifconf") | |
31 #pragma CODE_SECTION(l1s_recover_Frame,".emifconf") | |
32 #pragma CODE_SECTION(l1s_recover_HWTimers,".emifconf") | |
33 #pragma CODE_SECTION(l1s_get_next_gauging_in_Packet_Idle,".emifconf") | |
34 #pragma CODE_SECTION(l1s_gauging_decision_with_PNP,".emifconf") | |
35 #pragma CODE_SECTION(l1s_gauging_decision_with_NP,".emifconf") | |
36 #pragma CODE_SECTION(l1s_gauging_task,".emifconf") | |
37 #pragma CODE_SECTION(l1s_gauging_task_end,".emifconf") | |
38 // 2-03-2007 pinghua added end | |
39 #endif | |
40 | |
41 #define L1_PWMGR_C | 10 #define L1_PWMGR_C |
42 //#pragma DUPLICATE_FOR_INTERNAL_RAM_START | 11 //#pragma DUPLICATE_FOR_INTERNAL_RAM_START |
43 | 12 |
44 #include "config.h" | 13 #include "timer/timer2.h" |
14 #include "armio/armio.h" | |
15 | |
16 //omaps00090550 #include "l1_macro.h" | |
45 #include "l1_confg.h" | 17 #include "l1_confg.h" |
46 | 18 |
47 //sajal added ..................................... | 19 #if (OP_L1_STANDALONE == 1) |
48 #if (CODE_VERSION == SIMULATION) | 20 #include "uart/serialswitch_core.h" |
49 //#include "l1_pwmgr.h" | 21 #else |
50 //omaps00090550 #303 warning removal typedef unsigned char UWORD_8; | 22 #include "uart/serialswitch.h" |
51 | 23 #endif |
52 // typedef volatile unsigned short REG_UWORD16; //omaps00090550 | 24 |
53 // #define REG16(A) (*(REG_UWORD16*)(A)) //omaps00090550 | 25 #if (OP_L1_STANDALONE == 0) |
54 // typedef volatile unsigned short REGISTER_UWORD16; //omaps00090550 | |
55 | |
56 #define MAP_ULPD_REG 0xFFFE2000 //ULPD registers start address (CS4) | |
57 #define ULPD_SETUP_CLK13_REG (*(REGISTER_UWORD16*)((REGISTER_UWORD16 *)(MAP_ULPD_REG) + 14)) | |
58 #define ULPD_SETUP_SLICER_REG (*(REGISTER_UWORD16*)((REGISTER_UWORD16 *)(MAP_ULPD_REG) + 15)) | |
59 #define ULPD_SETUP_VTCXO_REG (*(REGISTER_UWORD16*)((REGISTER_UWORD16 *)(MAP_ULPD_REG) + 16)) | |
60 | |
61 #define MAP_CLKM_REG 0xFFFFFD00 //CLOCKM registers start address (CS31) | |
62 #define CLKM_CNTL_CLK_OFFSET 0x02 | |
63 #define CLKM_CNTL_CLK_REG REG16 (MAP_CLKM_REG + CLKM_CNTL_CLK_OFFSET) | |
64 | |
65 #define EMIF_CONFIG_PWD_POS 0 | |
66 #define EMIF_CONFIG_PDE_POS 1 | |
67 #define EMIF_CONFIG_PREFETCH_POS 3 | |
68 #define EMIF_CONFIG_FLUSH_PREFETCH_POS 5 | |
69 #define EMIF_CONFIG_WP_POS 6 | |
70 | |
71 #define EMIF_CONFIG REG16(EMIF_CONFIG_BASE_ADDR+EMIF_CONFIG_REG_OFFSET) | |
72 #define EMIF_CONFIG_BASE_ADDR 0xFFFFFB00 //External Memory inter registers address (CS31) (NEW) | |
73 #define EMIF_CONFIG_REG_OFFSET 0x02 // Emif configuration register | |
74 | |
75 #endif | |
76 //sajal added till here...... | |
77 | |
78 | |
79 | |
80 #include "../../bsp/timer2.h" | |
81 #include "../../bsp/armio.h" | |
82 #include "../../serial/serialswitch.h" | |
83 | |
84 #if 0 //(OP_L1_STANDALONE == 0) | |
85 #include "sim/sim.h" | 26 #include "sim/sim.h" |
86 #include "rv_swe.h" | 27 #include "rv_swe.h" |
87 #endif | 28 #endif |
88 | 29 |
89 | 30 |
164 | 105 |
165 | 106 |
166 #include "l1_types.h" | 107 #include "l1_types.h" |
167 #include "l1_const.h" | 108 #include "l1_const.h" |
168 | 109 |
169 #include "../../bsp/abb+spi/abb.h" | 110 #include "abb/abb.h" |
170 /* #include "dma/sys_dma.h" */ | 111 #include "dma/sys_dma.h" |
171 | 112 |
172 #if (OP_BT == 1) | 113 #if (OP_BT == 1) |
173 #include "hci_ll_simul.h" | 114 #include "hci_ll_simul.h" |
174 #endif | 115 #endif |
175 | 116 |
202 #include "l1_defty.h" | 143 #include "l1_defty.h" |
203 #include "l1_varex.h" | 144 #include "l1_varex.h" |
204 #include "l1_tabs.h" | 145 #include "l1_tabs.h" |
205 #include "sys_types.h" | 146 #include "sys_types.h" |
206 #include "tpudrv.h" | 147 #include "tpudrv.h" |
207 #include "../../gpf/inc/cust_os.h" | 148 #include "cust_os.h" |
208 #include "l1_msgty.h" | 149 #include "l1_msgty.h" |
209 #include "l1_proto.h" | 150 #include "l1_proto.h" |
210 #include "l1_trace.h" | 151 #include "l1_trace.h" |
211 #include "../../bsp/timer.h" | 152 #include "timer/timer.h" |
212 | |
213 #include "l1_pwmgr.h" | |
214 | 153 |
215 #if (CHIPSET == 12) || (CHIPSET == 15) | 154 #if (CHIPSET == 12) || (CHIPSET == 15) |
216 #include "timer/timer_sec.h" | 155 #include "timer/timer_sec.h" |
217 #include "inth/sys_inth.h" | 156 #include "inth/sys_inth.h" |
218 | 157 |
219 | 158 /* FreeCalypso: massive #if (CHIPSET == 15) chunk removed */ |
220 | |
221 #if(CHIPSET == 15) | |
222 #include "l1_pwmgr.h" | |
223 #if (OP_L1_STANDALONE == 0) | |
224 #include "lcc/lcc_api.h" | |
225 #endif | |
226 | |
227 /* If NAND is enabled */ | |
228 #if defined(RVM_DATALIGHT_SWE) || defined(RVM_NAN_SWE) | |
229 unsigned int temp_NAND_Reg1; | |
230 unsigned int temp_NAND_Reg2; | |
231 unsigned int temp_NAND_Reg3; | |
232 #endif | |
233 | |
234 | |
235 | |
236 | |
237 | |
238 #if (OP_L1_STANDALONE == 1) | |
239 | |
240 const t_peripheral_interface Peripheral_interface [MAX_PERIPHERAL]= | |
241 { | |
242 f_peripheral_interface_dummy, | |
243 f_peripheral_interface_dummy, | |
244 f_peripheral_interface_dummy, | |
245 f_peripheral_interface_dummy, | |
246 f_peripheral_interface_dummy, | |
247 f_peripheral_interface_dummy, | |
248 f_peripheral_interface_dummy, | |
249 f_peripheral_interface_dummy, | |
250 madc_outen_check, /* MADC_AS_ID = 8 */ | |
251 f_peripheral_interface_dummy, | |
252 f_peripheral_interface_dummy, | |
253 f_peripheral_interface_dummy, | |
254 f_peripheral_interface_dummy, | |
255 f_peripheral_interface_dummy, | |
256 f_peripheral_interface_dummy, | |
257 f_peripheral_interface_dummy, | |
258 }; | |
259 | |
260 const t_application_interface Application_interface [MAX_APPLICATIONS] = | |
261 { | |
262 f_application_interface_dummy, | |
263 f_application_interface_dummy, | |
264 f_application_interface_dummy, | |
265 f_application_interface_dummy, | |
266 f_application_interface_dummy, | |
267 f_application_interface_dummy, | |
268 f_application_interface_dummy, | |
269 f_application_interface_dummy, | |
270 f_application_interface_dummy, | |
271 f_application_interface_dummy, | |
272 f_application_interface_dummy, | |
273 f_application_interface_dummy, | |
274 f_application_interface_dummy, | |
275 f_application_interface_dummy, | |
276 f_application_interface_dummy, | |
277 f_application_interface_dummy, | |
278 }; | |
279 #else // For integrated Build | |
280 const t_peripheral_interface Peripheral_interface [MAX_PERIPHERAL]= | |
281 { | |
282 uart_pwr_interface, | |
283 #ifdef RVM_USB_SWE | |
284 usb_pwr_interface, | |
285 #else | |
286 f_peripheral_interface_dummy, | |
287 #endif | |
288 usim_pwr_interface, | |
289 i2c_pwr_interface, | |
290 lcd_pwr_interface, | |
291 #ifdef RVM_CAMD_SWE | |
292 #if (OP_L1_STANDALONE == 0) | |
293 camera_pwr_interface, | |
294 #endif | |
295 #else | |
296 f_peripheral_interface_dummy, | |
297 #endif | |
298 backlight_pwr_interface, | |
299 f_peripheral_interface_dummy, | |
300 audio_madc_sleep, /* MADC_AS_ID = 8 */ | |
301 lcc_pwr_interface, | |
302 f_peripheral_interface_dummy, | |
303 f_peripheral_interface_dummy, | |
304 f_peripheral_interface_dummy, | |
305 f_peripheral_interface_dummy, | |
306 f_peripheral_interface_dummy, | |
307 f_peripheral_interface_dummy, | |
308 }; | |
309 | |
310 const t_application_interface Application_interface [MAX_APPLICATIONS] = | |
311 { | |
312 #ifdef BTS | |
313 | |
314 BTHAL_PM_HandleSleepManagerReq, | |
315 #else | |
316 f_application_interface_dummy, | |
317 #endif | |
318 f_application_interface_dummy, | |
319 f_application_interface_dummy, | |
320 f_application_interface_dummy, | |
321 f_application_interface_dummy, | |
322 f_application_interface_dummy, | |
323 f_application_interface_dummy, | |
324 f_application_interface_dummy, | |
325 f_application_interface_dummy, | |
326 f_application_interface_dummy, | |
327 f_application_interface_dummy, | |
328 f_application_interface_dummy, | |
329 f_application_interface_dummy, | |
330 f_application_interface_dummy, | |
331 f_application_interface_dummy, | |
332 f_application_interface_dummy, | |
333 }; | |
334 | |
335 | |
336 #endif // (OP_L1_STANDALONE == 1) | |
337 | |
338 #endif // omaps00090550 #14 -d removal (CHIPSET = 15) | |
339 | |
340 | 159 |
341 #else //(CHIPSET == 12) || (CHIPSET == 15) | 160 #else //(CHIPSET == 12) || (CHIPSET == 15) |
342 #include "../../bsp/iq.h" | 161 #include "inth/iq.h" |
343 #include "../../bsp/inth.h" | 162 #include "inth/inth.h" |
344 #endif | 163 #endif |
345 // #include "timer1.h" | 164 // #include "timer1.h" |
346 #include "../../bsp/ulpd.h" | 165 #include "ulpd/ulpd.h" |
347 #include "../../bsp/clkm.h" | 166 #include "clkm/clkm.h" |
348 #include "../../bsp/mem.h" | 167 #include "memif/mem.h" |
349 #if L2_L3_SIMUL | 168 #if L2_L3_SIMUL |
350 #include "hw_debug.h" | 169 #include "hw_debug.h" |
351 #endif | 170 #endif |
352 | 171 |
353 #if (OP_WCP == 1) && (OP_L1_STANDALONE != 1) | 172 #if (OP_WCP == 1) && (OP_L1_STANDALONE != 1) |
411 #if (CODE_VERSION != SIMULATION) && (CHIPSET == 15) | 230 #if (CODE_VERSION != SIMULATION) && (CHIPSET == 15) |
412 extern T_DRP_REGS_STR *drp_regs; | 231 extern T_DRP_REGS_STR *drp_regs; |
413 #endif | 232 #endif |
414 | 233 |
415 #if L1_GPRS | 234 #if L1_GPRS |
416 UWORD32 l1s_get_next_gauging_in_Packet_Idle(void); | 235 WORD32 l1s_get_next_gauging_in_Packet_Idle(void); |
417 #endif | 236 #endif |
418 //#pragma DUPLICATE_FOR_INTERNAL_RAM_END | 237 //#pragma DUPLICATE_FOR_INTERNAL_RAM_END |
419 | 238 |
420 #if !((MOVE_IN_INTERNAL_RAM == 1) && (GSM_IDLE_RAM !=0)) // MOVE TO INTERNAL MEM IN CASE GSM_IDLE_RAM enabled | 239 #if !((MOVE_IN_INTERNAL_RAM == 1) && (GSM_IDLE_RAM !=0)) // MOVE TO INTERNAL MEM IN CASE GSM_IDLE_RAM enabled |
421 //#pragma GSM_IDLE_DUPLICATE_FOR_INTERNAL_RAM_START // KEEP IN EXTERNAL MEM otherwise | 240 //#pragma GSM_IDLE_DUPLICATE_FOR_INTERNAL_RAM_START // KEEP IN EXTERNAL MEM otherwise |
437 #define RATIO(HF,LF, root, frac) \ | 256 #define RATIO(HF,LF, root, frac) \ |
438 root = (UWORD32)(HF/LF); \ | 257 root = (UWORD32)(HF/LF); \ |
439 frac = (UWORD32)(((HF - (root*LF)) << 16) / LF); | 258 frac = (UWORD32)(((HF - (root*LF)) << 16) / LF); |
440 | 259 |
441 // previous ratio with frac + 0.5 | 260 // previous ratio with frac + 0.5 |
261 #if 0 /* original LoCosto code */ | |
442 #define RATIO2(HF,LF, root, frac) \ | 262 #define RATIO2(HF,LF, root, frac) \ |
443 if(LF){ \ | 263 if(LF){ \ |
444 root = (UWORD32)(HF/LF); \ | 264 root = (UWORD32)(HF/LF); \ |
445 frac = (UWORD32)((((HF - (root*LF)) << 16) + 0.5*LF) / LF);} | 265 frac = (UWORD32)((((HF - (root*LF)) << 16) + 0.5*LF) / LF);} |
266 #else /* FreeCalypso TCS211 reconstruction */ | |
267 #define RATIO2(HF,LF, root, frac) \ | |
268 { \ | |
269 root = (UWORD32)(HF/LF); \ | |
270 frac = (UWORD32)((((HF - (root*LF)) << 16) + 0.5*LF) / LF);} | |
271 #endif | |
446 | 272 |
447 #define HFTHEO(LF, root, frac, hftheo) \ | 273 #define HFTHEO(LF, root, frac, hftheo) \ |
448 hftheo = root*LF + ((frac*LF) >>16); | 274 hftheo = root*LF + ((frac*LF) >>16); |
449 | 275 |
450 #define SUM(HF, LF, nb, ind) \ | 276 #define SUM(HF, LF, nb, ind) \ |
454 LF = LF +l1s.pw_mgr.histo[ind][0]; \ | 280 LF = LF +l1s.pw_mgr.histo[ind][0]; \ |
455 HF = HF +l1s.pw_mgr.histo[ind][1]; \ | 281 HF = HF +l1s.pw_mgr.histo[ind][1]; \ |
456 } | 282 } |
457 | 283 |
458 | 284 |
459 | 285 #if 0 /* FreeCalypso TCS211 reconstruction */ |
460 #if (CODE_VERSION!=SIMULATION) | |
461 T_PWMGR_DEBUG l1_pwmgr_debug; | 286 T_PWMGR_DEBUG l1_pwmgr_debug; |
462 #endif // NOT SIMULATION | 287 #endif |
463 | 288 |
464 #if(CHIPSET == 15) | 289 |
465 | 290 /* FreeCalypso: massive #if (CHIPSET == 15) chunk removed */ |
466 /************************************************************/ | |
467 /* Configure EMIF for optimal consumption */ | |
468 /************************************************************/ | |
469 | |
470 | |
471 void EMIF_SetConfReg(const UWORD8 wp,const UWORD8 flush_prefetch,const UWORD8 Prefetch_mode,const UWORD8 pde,const UWORD8 pwd_en) | |
472 { | |
473 UWORD16 Emif_config_Reg; | |
474 Emif_config_Reg = (pwd_en << EMIF_CONFIG_PWD_POS | pde << EMIF_CONFIG_PDE_POS | Prefetch_mode << EMIF_CONFIG_PREFETCH_POS | flush_prefetch << EMIF_CONFIG_FLUSH_PREFETCH_POS | wp << EMIF_CONFIG_WP_POS); | |
475 /*p_Emifreg -> EMIF_Config = (Emif_config_Reg & EMIF_CONFIG_REG_MASK );*/ | |
476 EMIF_CONFIG = Emif_config_Reg; | |
477 } // End of EMIF_SetConfReg | |
478 | |
479 | |
480 | |
481 #if (OP_L1_STANDALONE == 1) // API for Audio and MADC | |
482 | |
483 | |
484 | |
485 T_AUDIO_OUTEN_REG audio_outen_pm; | |
486 | |
487 // L1 Standalone function for Configuring Audio registers. | |
488 // Argument CLK_MASK checks if Audio path is active | |
489 // Argument SLEEP_CMD configures Audio registers for optimal consumption | |
490 // Argument WAKE_CMD reconfigure audio registers after wakeup | |
491 | |
492 Uint8 madc_outen_check(Uint8 cmd) { | |
493 BspTwl3029_ReturnCode returnVal = BSP_TWL3029_RETURN_CODE_FAILURE; | |
494 /* I2C array */ | |
495 Bsp_Twl3029_I2cTransReqArray i2cTransArray; | |
496 Bsp_Twl3029_I2cTransReqArrayPtr i2cTransArrayPtr= &i2cTransArray; | |
497 | |
498 /* twl3029 I2C reg info struct */ | |
499 BspTwl3029_I2C_RegisterInfo regInfo[8] ; | |
500 BspTwl3029_I2C_RegisterInfo* regInfoPtr = regInfo; | |
501 BspTwl3029_I2C_RegData shadow_pwronstatus, ston_bit; | |
502 Uint8 count = 0;//OMAPS90550-new | |
503 | |
504 | |
505 switch( cmd ) { | |
506 | |
507 case CLK_MASK: | |
508 returnVal = BspTwl3029_I2c_shadowRegRead(BSP_TWL3029_I2C_AUD, BSP_TWL_3029_MAP_AUDIO_PWRONSTATUS_OFFSET, | |
509 &shadow_pwronstatus); | |
510 ston_bit = (shadow_pwronstatus & (1 << BSP_TWL3029_LLIF_AUDIO_PWRONSTATUS_STON_OFFSET)); | |
511 | |
512 if (ston_bit == 1) return DCXO_CLOCK; | |
513 else return NO_CLOCK; | |
514 // omaps00090550 break; | |
515 | |
516 case SLEEP_CMD: | |
517 /* store the output enable 1 register */ | |
518 returnVal = BspTwl3029_I2c_shadowRegRead(BSP_TWL3029_I2C_AUD, BSP_TWL_3029_MAP_AUDIO_OUTEN1_OFFSET, | |
519 &audio_outen_pm.outen1); | |
520 | |
521 /* store the output enable 2 register */ | |
522 returnVal = BspTwl3029_I2c_shadowRegRead(BSP_TWL3029_I2C_AUD, BSP_TWL_3029_MAP_AUDIO_OUTEN2_OFFSET, | |
523 &audio_outen_pm.outen2); | |
524 | |
525 /* store the output enable 3 register */ | |
526 returnVal = BspTwl3029_I2c_shadowRegRead(BSP_TWL3029_I2C_AUD, BSP_TWL_3029_MAP_AUDIO_OUTEN3_OFFSET, | |
527 &audio_outen_pm.outen3); | |
528 | |
529 | |
530 /* write default values into OUTEN1,OUTEN2 & OUTEN3 */ | |
531 returnVal = BspTwl3029_I2c_regQueWrite(BSP_TWL3029_I2C_AUD, BSP_TWL_3029_MAP_AUDIO_OUTEN1_OFFSET, | |
532 BSP_TWL_3029_MAP_AUDIO_OUTEN1_DEFAULT,regInfoPtr++); | |
533 count++; | |
534 | |
535 /* store the output enable 2 register */ | |
536 returnVal = BspTwl3029_I2c_regQueWrite(BSP_TWL3029_I2C_AUD, BSP_TWL_3029_MAP_AUDIO_OUTEN2_OFFSET, | |
537 BSP_TWL_3029_MAP_AUDIO_OUTEN2_DEFAULT,regInfoPtr++); | |
538 count++; | |
539 | |
540 /* store the output enable 3 register */ | |
541 returnVal = BspTwl3029_I2c_regQueWrite(BSP_TWL3029_I2C_AUD, BSP_TWL_3029_MAP_AUDIO_OUTEN3_OFFSET, | |
542 BSP_TWL_3029_MAP_AUDIO_OUTEN3_DEFAULT,regInfoPtr++); | |
543 count++; | |
544 | |
545 | |
546 /* now request to I2C manager to write to Triton registers */ | |
547 if (returnVal != BSP_TWL3029_RETURN_CODE_FAILURE) | |
548 { | |
549 returnVal = BspTwl3029_I2c_regInfoSend(regInfo,(Uint16)count,NULL, | |
550 (BspI2c_TransactionRequest*)i2cTransArrayPtr); | |
551 } | |
552 | |
553 if (returnVal == BSP_TWL3029_RETURN_CODE_SUCCESS) return SUCCESS; | |
554 else return FAILURE; | |
555 | |
556 // omaps00090550 break; | |
557 | |
558 case WAKE_CMD: | |
559 /* write default values into OUTEN1,OUTEN2 & OUTEN3 */ | |
560 returnVal = BspTwl3029_I2c_regQueWrite(BSP_TWL3029_I2C_AUD, BSP_TWL_3029_MAP_AUDIO_OUTEN1_OFFSET, | |
561 audio_outen_pm.outen1,regInfoPtr++); | |
562 count++; | |
563 | |
564 /* store the output enable 2 register */ | |
565 returnVal = BspTwl3029_I2c_regQueWrite(BSP_TWL3029_I2C_AUD, BSP_TWL_3029_MAP_AUDIO_OUTEN2_OFFSET, | |
566 audio_outen_pm.outen2,regInfoPtr++); | |
567 count++; | |
568 | |
569 /* store the output enable 3 register */ | |
570 returnVal = BspTwl3029_I2c_regQueWrite(BSP_TWL3029_I2C_AUD, BSP_TWL_3029_MAP_AUDIO_OUTEN3_OFFSET, | |
571 audio_outen_pm.outen3,regInfoPtr++); | |
572 count++; | |
573 | |
574 | |
575 | |
576 /* now request to I2C manager to write to Triton registers */ | |
577 if (returnVal != BSP_TWL3029_RETURN_CODE_FAILURE) | |
578 { | |
579 returnVal = BspTwl3029_I2c_regInfoSend(regInfo,(Uint16)count,NULL, | |
580 (BspI2c_TransactionRequest*)i2cTransArrayPtr); | |
581 } | |
582 | |
583 if (returnVal == BSP_TWL3029_RETURN_CODE_SUCCESS) return SUCCESS; | |
584 else return FAILURE; | |
585 // omaps00090550 break; | |
586 } | |
587 return SUCCESS;//omaps00090550 | |
588 } | |
589 #else // Integrated build API for Audio and MADC | |
590 | |
591 // Full PS build function for Configuring Audio registers. | |
592 // Argument CLK_MASK checks if Audio path is active | |
593 // Argument SLEEP_CMD configures Audio registers for optimal consumption | |
594 // Argument WAKE_CMD reconfigure audio registers after wakeup | |
595 | |
596 | |
597 T_AUDIO_OUTEN_REG audio_outen_pm; | |
598 BspTwl3029_I2C_RegData audio_ctrl3; | |
599 | |
600 Uint8 audio_madc_sleep(Uint8 cmd) { | |
601 BspTwl3029_ReturnCode returnVal = BSP_TWL3029_RETURN_CODE_FAILURE; | |
602 /* I2C array */ | |
603 //Bsp_Twl3029_I2cTransReqArray i2cTransArray; | |
604 //Bsp_Twl3029_I2cTransReqArrayPtr i2cTransArrayPtr= &i2cTransArray; | |
605 | |
606 /* twl3029 I2C reg info struct */ | |
607 //BspTwl3029_I2C_RegisterInfo regInfo[8] ; | |
608 //BspTwl3029_I2C_RegisterInfo* regInfoPtr = regInfo; | |
609 BspTwl3029_I2C_RegData shadow_pwronstatus, ston_bit; | |
610 | |
611 | |
612 Uint8 count = 0; | |
613 | |
614 | |
615 switch( cmd ) { | |
616 | |
617 case CLK_MASK: | |
618 returnVal = BspTwl3029_I2c_shadowRegRead(BSP_TWL3029_I2C_AUD, BSP_TWL_3029_MAP_AUDIO_PWRONSTATUS_OFFSET, | |
619 &shadow_pwronstatus); | |
620 ston_bit = (shadow_pwronstatus & (1 << BSP_TWL3029_LLIF_AUDIO_PWRONSTATUS_STON_OFFSET)); | |
621 | |
622 if (ston_bit == 1) return DCXO_CLOCK; | |
623 else return NO_CLOCK; | |
624 //omaps00090550 break; | |
625 | |
626 case SLEEP_CMD: | |
627 #if 0 | |
628 /* store the output enable 1 register */ | |
629 returnVal = BspTwl3029_I2c_shadowRegRead(BSP_TWL3029_I2C_AUD, BSP_TWL_3029_MAP_AUDIO_OUTEN1_OFFSET, | |
630 &audio_outen_pm.outen1); | |
631 | |
632 /* store the output enable 2 register */ | |
633 returnVal = BspTwl3029_I2c_shadowRegRead(BSP_TWL3029_I2C_AUD, BSP_TWL_3029_MAP_AUDIO_OUTEN2_OFFSET, | |
634 &audio_outen_pm.outen2); | |
635 | |
636 /* store the output enable 3 register */ | |
637 returnVal = BspTwl3029_I2c_shadowRegRead(BSP_TWL3029_I2C_AUD, BSP_TWL_3029_MAP_AUDIO_OUTEN3_OFFSET, | |
638 &audio_outen_pm.outen3); | |
639 | |
640 returnVal = BspTwl3029_I2c_shadowRegRead(BSP_TWL3029_I2C_AUD, BSP_TWL_3029_MAP_AUDIO_OUTEN3_OFFSET, | |
641 &audio_ctrl3); | |
642 | |
643 if( audio_outen_pm.outen1 ) | |
644 { | |
645 /* write default values into OUTEN1,OUTEN2 & OUTEN3 */ | |
646 returnVal = BspTwl3029_I2c_regQueWrite(BSP_TWL3029_I2C_AUD, BSP_TWL_3029_MAP_AUDIO_OUTEN1_OFFSET, | |
647 BSP_TWL_3029_MAP_AUDIO_OUTEN1_DEFAULT,regInfoPtr++); | |
648 count++; | |
649 } | |
650 | |
651 if( audio_outen_pm.outen2 ) | |
652 { | |
653 | |
654 /* store the output enable 2 register */ | |
655 returnVal = BspTwl3029_I2c_regQueWrite(BSP_TWL3029_I2C_AUD, BSP_TWL_3029_MAP_AUDIO_OUTEN2_OFFSET, | |
656 BSP_TWL_3029_MAP_AUDIO_OUTEN2_DEFAULT,regInfoPtr++); | |
657 count++; | |
658 } | |
659 | |
660 if( audio_outen_pm.outen3 ) | |
661 { | |
662 /* store the output enable 3 register */ | |
663 returnVal = BspTwl3029_I2c_regQueWrite(BSP_TWL3029_I2C_AUD, BSP_TWL_3029_MAP_AUDIO_OUTEN3_OFFSET, | |
664 BSP_TWL_3029_MAP_AUDIO_OUTEN3_DEFAULT,regInfoPtr++); | |
665 count++; | |
666 } | |
667 | |
668 /* Selectively checking if INMODE is set or not. Write is queued only when INMODE(0-3) | |
669 is non-zero */ | |
670 if( audio_ctrl3 & 0xf) | |
671 { | |
672 /* store the output enable 3 register */ | |
673 returnVal = BspTwl3029_I2c_regQueWrite(BSP_TWL3029_I2C_AUD, BSP_TWL_3029_MAP_AUDIO_CTRL3_OFFSET, | |
674 BSP_TWL_3029_MAP_AUDIO_CTRL3_DEFAULT,regInfoPtr++); | |
675 count++; | |
676 } | |
677 | |
678 returnVal = BspTwl3029_I2c_regQueWrite(BSP_TWL3029_I2C_AUX,BSP_TWL3029_MAP_AUX_REG_TOGGLE1_OFFSET, | |
679 1 << BSP_TWL3029_LLIF_AUX_REG_TOGGLE1_MADCR_OFFSET, regInfoPtr++); | |
680 count++; | |
681 | |
682 //Turn off the USB leakage currrent | |
683 | |
684 // returnVal = BspTwl3029_I2c_regQueWrite(BSP_TWL3029_I2C_PAGE0, BSP_TWL_3029_MAP_CKG_TESTUNLOCK_OFFSET,0xb6,regInfoPtr++); | |
685 // count++; | |
686 | |
687 //returnVal = BspTwl3029_I2c_regQueWrite(BSP_TWL3029_I2C_PAGE2, BSP_TWL3029_MAP_USB_PSM_EN_TEST_SET_OFFSET,0x80,regInfoPtr++); | |
688 //count++; | |
689 | |
690 // returnVal = BspTwl3029_I2c_regQueWrite(BSP_TWL3029_I2C_PAGE2,BSP_TWL3029_MAP_USB_VBUS_EN_TEST_OFFSET,0x00,regInfoPtr++); | |
691 // count++; | |
692 | |
693 //returnVal = BspTwl3029_I2c_regQueWrite(BSP_TWL3029_I2C_PAGE0, BSP_TWL_3029_MAP_CKG_TESTUNLOCK_OFFSET,0x00,regInfoPtr++); | |
694 //count++; | |
695 | |
696 // now request to I2C manager to write to Triton registers | |
697 //if (returnVal != BSP_TWL3029_RETURN_CODE_FAILURE && !is_i2c_bus_locked()) | |
698 if (returnVal != BSP_TWL3029_RETURN_CODE_FAILURE) | |
699 { | |
700 returnVal = BspTwl3029_I2c_regInfoSend(regInfo,(Uint16)count,NULL, | |
701 (BspI2c_TransactionRequest*)i2cTransArrayPtr); | |
702 } | |
703 | |
704 if (returnVal == BSP_TWL3029_RETURN_CODE_SUCCESS) return SUCCESS; | |
705 else return FAILURE; | |
706 | |
707 #endif | |
708 | |
709 //omaps00090550 break; | |
710 | |
711 case WAKE_CMD: | |
712 #if 0 | |
713 | |
714 if( audio_outen_pm.outen1 ) | |
715 { | |
716 /* write default values into OUTEN1,OUTEN2 & OUTEN3 */ | |
717 returnVal = BspTwl3029_I2c_regQueWrite(BSP_TWL3029_I2C_AUD, BSP_TWL_3029_MAP_AUDIO_OUTEN1_OFFSET, | |
718 audio_outen_pm.outen1,regInfoPtr++); | |
719 count++; | |
720 } | |
721 | |
722 if( audio_outen_pm.outen2 ) | |
723 { | |
724 | |
725 /* store the output enable 2 register */ | |
726 returnVal = BspTwl3029_I2c_regQueWrite(BSP_TWL3029_I2C_AUD, BSP_TWL_3029_MAP_AUDIO_OUTEN2_OFFSET, | |
727 audio_outen_pm.outen2,regInfoPtr++); | |
728 count++; | |
729 } | |
730 | |
731 if( audio_outen_pm.outen3 ) | |
732 { | |
733 /* store the output enable 3 register */ | |
734 returnVal = BspTwl3029_I2c_regQueWrite(BSP_TWL3029_I2C_AUD, BSP_TWL_3029_MAP_AUDIO_OUTEN3_OFFSET, | |
735 audio_outen_pm.outen3,regInfoPtr++); | |
736 count++; | |
737 } | |
738 | |
739 /* Selectively checking if INMODE is set or not. Write is queued only when INMODE(0-3) | |
740 is non-zero */ | |
741 if( audio_ctrl3 & 0xf) | |
742 { | |
743 /* store the output enable 3 register */ | |
744 returnVal = BspTwl3029_I2c_regQueWrite(BSP_TWL3029_I2C_AUD, BSP_TWL_3029_MAP_AUDIO_CTRL3_OFFSET, | |
745 audio_ctrl3,regInfoPtr++); | |
746 count++; | |
747 } | |
748 | |
749 | |
750 //wake up mode: Enable MADC | |
751 returnVal = BspTwl3029_I2c_regQueWrite(BSP_TWL3029_I2C_AUX,BSP_TWL3029_MAP_AUX_REG_TOGGLE1_OFFSET, | |
752 1 << BSP_TWL3029_LLIF_AUX_REG_TOGGLE1_MADCS_OFFSET, regInfoPtr++); | |
753 | |
754 count++; //TI_SH added to set the madc on correctly | |
755 | |
756 //Enable the USB leakage current after wake up | |
757 | |
758 // returnVal = BspTwl3029_I2c_regQueWrite(BSP_TWL3029_I2C_PAGE0,BSP_TWL_3029_MAP_CKG_TESTUNLOCK_OFFSET,0xb6,regInfoPtr++); | |
759 // count++; | |
760 | |
761 // returnVal = BspTwl3029_I2c_regQueWrite(BSP_TWL3029_I2C_PAGE2,BSP_TWL3029_MAP_USB_VBUS_EN_TEST_OFFSET,0x0F,regInfoPtr++); | |
762 // count++; | |
763 | |
764 //returnVal = BspTwl3029_I2c_regQueWrite(BSP_TWL3029_I2C_PAGE2,BSP_TWL3029_MAP_USB_PSM_EN_TEST_CLR_OFFSET,0x80,regInfoPtr++); | |
765 //count++; | |
766 | |
767 // returnVal = BspTwl3029_I2c_regQueWrite(BSP_TWL3029_I2C_PAGE0,BSP_TWL_3029_MAP_CKG_TESTUNLOCK_OFFSET,0x00,regInfoPtr++); | |
768 // count++; | |
769 | |
770 // now request to I2C manager to write to Triton registers | |
771 //if (returnVal != BSP_TWL3029_RETURN_CODE_FAILURE && !is_i2c_bus_locked()) | |
772 if (returnVal != BSP_TWL3029_RETURN_CODE_FAILURE) | |
773 { | |
774 returnVal = BspTwl3029_I2c_regInfoSend(regInfo,(Uint16)count,NULL, | |
775 (BspI2c_TransactionRequest*)i2cTransArrayPtr); | |
776 } | |
777 | |
778 if (returnVal == BSP_TWL3029_RETURN_CODE_SUCCESS) return SUCCESS; | |
779 else return FAILURE; | |
780 #endif | |
781 break; | |
782 } | |
783 return SUCCESS; | |
784 } | |
785 #endif // API for Audio and MADC | |
786 | |
787 | |
788 | |
789 //Function to check status of Backlight Only Argument 0 is valid | |
790 | |
791 | |
792 Uint8 backlight_pwr_interface(Uint8 cmd) | |
793 { | |
794 BspTwl3029_I2C_RegData regData; | |
795 | |
796 | |
797 if(cmd == 0) | |
798 { | |
799 BspTwl3029_I2c_shadowRegRead(BSP_TWL3029_I2C_PAGE0,PWDNSTATUS,®Data); | |
800 if((regData) & 0x70) | |
801 { | |
802 return(DCXO_CLOCK); | |
803 } | |
804 else | |
805 { | |
806 return(NO_CLOCK); | |
807 } | |
808 | |
809 } | |
810 else | |
811 { | |
812 return(SUCCESS); | |
813 } | |
814 } | |
815 | |
816 //Dummy Function for peripheral check to populate Function pointer table for unused APIs | |
817 | |
818 | |
819 Uint8 f_peripheral_interface_dummy(Uint8 cmd) | |
820 { | |
821 if(cmd == 0) | |
822 { | |
823 return(NO_CLOCK); | |
824 } | |
825 else | |
826 { | |
827 return(SUCCESS); | |
828 } | |
829 | |
830 } | |
831 | |
832 //Dummy Function for Application check to populate Function pointer table for unused APIs | |
833 | |
834 Uint8 f_application_interface_dummy(Uint8 cmd) | |
835 { | |
836 if(cmd == 0) | |
837 { | |
838 return(PM_INACTIVE); | |
839 } | |
840 else | |
841 { | |
842 return(SUCCESS); | |
843 } | |
844 } | |
845 | |
846 //Function not used as of now //OMAPS00090550 | |
847 void Update_Sleep_Status( Uint8 ID, Uint8 state) | |
848 { | |
849 if(state) | |
850 { | |
851 SLEEP_STATE |= (state << ID); //omaps00090550 ! was present before | |
852 } | |
853 else | |
854 { | |
855 SLEEP_STATE &=((Uint8)~1 <<ID); //omaps00090550 | |
856 } | |
857 } | |
858 | |
859 //Function polls the status of the following peripherals to take | |
860 //Sleep Decision: | |
861 //UART, USB, I2C, LCD, Camera, Backlight, Audio Stereo path, | |
862 //Bluetooth and USIM. | |
863 //All peripherals either cause Deep Sleep or No Sleep. | |
864 //Only USIM can also cause Big Sleep. | |
865 | |
866 | |
867 | |
868 UWORD32 Check_Peripheral_App(void) | |
869 { | |
870 #if (CODE_VERSION!=SIMULATION) | |
871 UWORD8 ret_value; | |
872 /* Check Peripherals */ | |
873 ret_value = Peripheral_interface[UART_ID](CLK_MASK); | |
874 if(ret_value) | |
875 { | |
876 l1_pwmgr_debug.fail_id = UART_ID; | |
877 l1_pwmgr_debug.fail_ret_val = ret_value; | |
878 return(DO_NOT_SLEEP); | |
879 } | |
880 ret_value = Peripheral_interface[USB_ID](CLK_MASK); | |
881 if(ret_value) | |
882 { | |
883 l1_pwmgr_debug.fail_id = USB_ID; | |
884 l1_pwmgr_debug.fail_ret_val = ret_value; | |
885 return(DO_NOT_SLEEP); | |
886 } | |
887 ret_value = Peripheral_interface[I2C_ID](CLK_MASK); | |
888 if(ret_value) | |
889 { | |
890 l1_pwmgr_debug.fail_id = I2C_ID; | |
891 l1_pwmgr_debug.fail_ret_val = ret_value; | |
892 return(DO_NOT_SLEEP); | |
893 } | |
894 ret_value = Peripheral_interface[LCD_ID](CLK_MASK); | |
895 if(ret_value) | |
896 { | |
897 l1_pwmgr_debug.fail_id = LCD_ID; | |
898 l1_pwmgr_debug.fail_ret_val = ret_value; | |
899 return(DO_NOT_SLEEP); | |
900 } | |
901 ret_value = Peripheral_interface[CAMERA_ID](CLK_MASK); | |
902 if(ret_value) | |
903 { | |
904 l1_pwmgr_debug.fail_id = CAMERA_ID; | |
905 l1_pwmgr_debug.fail_ret_val = ret_value; | |
906 return(DO_NOT_SLEEP); | |
907 } | |
908 ret_value = Peripheral_interface[BACKLIGHT_ID](CLK_MASK); | |
909 if(ret_value) | |
910 { | |
911 l1_pwmgr_debug.fail_id = BACKLIGHT_ID; | |
912 l1_pwmgr_debug.fail_ret_val = ret_value; | |
913 return(DO_NOT_SLEEP); | |
914 } | |
915 ret_value = Peripheral_interface[MADC_AS_ID](CLK_MASK); | |
916 if(ret_value) | |
917 { | |
918 l1_pwmgr_debug.fail_id = MADC_AS_ID; | |
919 l1_pwmgr_debug.fail_ret_val = ret_value; | |
920 return(DO_NOT_SLEEP); | |
921 } | |
922 /* check battery charger */ | |
923 ret_value = Peripheral_interface[BCI_ID](CLK_MASK); | |
924 if(ret_value) | |
925 { | |
926 l1_pwmgr_debug.fail_id = BCI_ID; | |
927 l1_pwmgr_debug.fail_ret_val = ret_value; | |
928 return(DO_NOT_SLEEP); | |
929 } | |
930 | |
931 /* Check Applications */ | |
932 ret_value = Application_interface[BT_Stack_ID](APP_ACTIVITY); | |
933 if(ret_value) | |
934 { | |
935 // L1_APPLICATION_OFFSET is added to distinguish Application interface | |
936 l1_pwmgr_debug.fail_id = BT_Stack_ID + (L1_PWMGR_APP_OFFSET); | |
937 l1_pwmgr_debug.fail_ret_val = ret_value; | |
938 return(DO_NOT_SLEEP); | |
939 } | |
940 ret_value = Peripheral_interface[USIM_ID](CLK_MASK); | |
941 if(ret_value) | |
942 { | |
943 l1_pwmgr_debug.fail_id = USIM_ID; | |
944 l1_pwmgr_debug.fail_ret_val = ret_value; | |
945 l1s.pw_mgr.why_big_sleep = BIG_SLEEP_DUE_TO_SIM; | |
946 return(FRAME_STOP); | |
947 } | |
948 else | |
949 { | |
950 return(CLOCK_STOP); | |
951 } | |
952 #endif //NOT SIMULATION | |
953 } | |
954 | |
955 //This function Configures DBB for optimal Power Consumption | |
956 //during Deep Sleep | |
957 | |
958 | |
959 | |
960 void DBB_Configure_DS() | |
961 { | |
962 // FDP enabling and disabling of burst configuration in flash not required in Locosto | |
963 // Hardware Settings as per Power Bench | |
964 | |
965 // Stop RNG oscillators | |
966 RNG_CONFIG &= 0xF03F; | |
967 | |
968 | |
969 /* Set GPIOs 19 to 22 as outputs to avoid floating pins */ | |
970 GPIO1_CNTL_REG &= ~0x0078; | |
971 | |
972 /* Set PD on VDR and VFSRX for VSP bus to avoid floating pins */ | |
973 CONF_VDR |= 0x0008; | |
974 CONF_VFSRX |= 0x0008; | |
975 | |
976 /* Set HASH in auto-idle */ | |
977 SHA_MASK = 0x0001; | |
978 | |
979 /* Set DES in auto-idle */ | |
980 DES_MASK = 0x0001; | |
981 | |
982 /* Set RNG in auto-idle */ | |
983 RNG_MASK = 0x0001; | |
984 | |
985 | |
986 /* uart_in_pull_down(); */ | |
987 | |
988 #if defined(RVM_DATALIGHT_SWE) || defined(RVM_NAN_SWE) | |
989 | |
990 | |
991 temp_NAND_Reg1 = COMMAND_REG; | |
992 temp_NAND_Reg2 = CONTROL_REG; | |
993 temp_NAND_Reg3 = STATUS_IT_REG; | |
994 | |
995 COMMAND_REG = 0x06; | |
996 CONTROL_REG = 0x0; | |
997 STATUS_IT_REG = 0x0; | |
998 | |
999 #endif | |
1000 // RANGA: All these bit fields should be replaced by macros | |
1001 // Set DPLL in idle mode | |
1002 // Cut C-PORT (new), IRQ, BRIDGE and TIMER clocks | |
1003 /* Set DPLL in idle mode */ | |
1004 /* Cut C-PORT (new), IRQ, BRIDGE and TIMER clocks */ | |
1005 CLKM_CNTL_CLK_REG &= ~0x0010 ; | |
1006 CLKM_CNTL_CLK_REG |= 0x000F ; | |
1007 | |
1008 CNTL_APLL_DIV_CLK &= ~0x0001; /* Disable APLL */ | |
1009 | |
1010 // Statements below are not required for the current hardware version. | |
1011 // This was done to solve the problem of DCXO taking 10 frames | |
1012 // to wake-up from Deep Sleep in older hardware versions. | |
1013 | |
1014 //DCXO_THRESH_L = 0xC040; // Setting DCXO Thresholds | |
1015 //DCXO_THRESH_H = 0x051F; // to solve Deep Sleep problem | |
1016 } | |
1017 | |
1018 //This function Restores DBB after wakeup from Deep Sleep | |
1019 | |
1020 | |
1021 void DBB_Wakeup_DS() | |
1022 { | |
1023 // FDP re-enabling and burst re-configuration are not required if FDP is disabled | |
1024 // during deep-sleep | |
1025 | |
1026 CLKM_CNTL_CLK_REG |= 0x0010 ; // Enable CPORT Clock | |
1027 | |
1028 CNTL_APLL_DIV_CLK |= 0x0001; // Enable APLL clock | |
1029 | |
1030 #if defined(RVM_DATALIGHT_SWE) || defined(RVM_NAN_SWE) | |
1031 | |
1032 // Restoring NAND | |
1033 COMMAND_REG = temp_NAND_Reg1; | |
1034 CONTROL_REG = temp_NAND_Reg2; | |
1035 STATUS_IT_REG = temp_NAND_Reg3; | |
1036 // Restoring NAND | |
1037 #endif | |
1038 | |
1039 | |
1040 } | |
1041 | |
1042 | |
1043 //This function shuts down APC Bandgap.Cannot be used for PG 1.0 Can be used only for PG 2.0 | |
1044 | |
1045 | |
1046 void Disable_APC_BG() //omaps00090550 | |
1047 { | |
1048 while (RHSW_ARM_CNF & DSP_PERIPH_LOCK) | |
1049 RHSW_ARM_CNF |= ARM_PERIPH_LOCK; | |
1050 APCCTRL2 &= ~BGEN; | |
1051 return; | |
1052 } | |
1053 | |
1054 //This function enables APC Bandgap.Cannot be used for PG 1.0 Can be used only for PG 2.0 | |
1055 | |
1056 void Enable_APC_BG() //omaps00090550 | |
1057 { | |
1058 while (RHSW_ARM_CNF & DSP_PERIPH_LOCK) | |
1059 RHSW_ARM_CNF |= ARM_PERIPH_LOCK; | |
1060 APCCTRL2 |= BGEN; | |
1061 return; | |
1062 } | |
1063 | |
1064 #endif //CHIPSET = 15 | |
1065 | |
1066 | |
1067 | |
1068 | |
1069 | |
1070 | |
1071 | |
1072 | |
1073 | 291 |
1074 | 292 |
1075 // l1ctl_pgm_clk32() | 293 // l1ctl_pgm_clk32() |
1076 // convert ratio in 4.33Mhz and pgm INC_FRAC,INC_SIXTEEN. | 294 // convert ratio in 4.33Mhz and pgm INC_FRAC,INC_SIXTEEN. |
1077 | 295 |
1085 // REM: nb_hf is the real value of the high frequency (ex in nbr of 65Mhz clock) | 303 // REM: nb_hf is the real value of the high frequency (ex in nbr of 65Mhz clock) |
1086 // To compute the ratio, nb_hf must be expressed in nbr of clock 4.33 Mhz | 304 // To compute the ratio, nb_hf must be expressed in nbr of clock 4.33 Mhz |
1087 // that's why nb_hf is divided by 3*l1_config.dpll | 305 // that's why nb_hf is divided by 3*l1_config.dpll |
1088 // RATIO2(nb_hf/(3*l1_config.dpll),nb_32khz,inc_sixteen,inc_frac); | 306 // RATIO2(nb_hf/(3*l1_config.dpll),nb_32khz,inc_sixteen,inc_frac); |
1089 // this line above is equal to the ligne below: | 307 // this line above is equal to the ligne below: |
1090 lf=(UWORD32)((UWORD32)(3*((UWORD32)((UWORD32)(l1_config.dpll)*nb_32khz)))); //OMAPS00090550 | 308 lf=(UWORD32)(3*l1_config.dpll*nb_32khz); |
1091 RATIO2(nb_hf,lf,inc_sixteen,inc_frac); | 309 RATIO2(nb_hf,lf,inc_sixteen,inc_frac); |
1092 | 310 |
1093 // integer part | 311 // integer part |
1094 ULDP_INCSIXTEEN_UPDATE(inc_sixteen); | 312 ULDP_INCSIXTEEN_UPDATE(inc_sixteen); |
1095 | 313 |
1126 static UWORD8 bad_count; // bad gauging values | 344 static UWORD8 bad_count; // bad gauging values |
1127 static UWORD8 gauging_state= RESET; // RESET,INIT, ACQUIS, UPDATE | 345 static UWORD8 gauging_state= RESET; // RESET,INIT, ACQUIS, UPDATE |
1128 static UWORD8 nb_gaug; // number of gauging in ACQUIS | 346 static UWORD8 nb_gaug; // number of gauging in ACQUIS |
1129 static UWORD8 idx,i; // index | 347 static UWORD8 idx,i; // index |
1130 static UWORD32 root, frac; // ratio of HF and LF average | 348 static UWORD32 root, frac; // ratio of HF and LF average |
1131 UWORD32 sumLF=0 , sumHF=0; // sum of HF and LF counts | 349 UWORD32 sumLF, sumHF; // sum of HF and LF counts |
1132 double nbHF_theo; | 350 double nbHF_theo; |
1133 | 351 |
1134 | 352 |
1135 // AFC or TEMPERATURE variation | 353 // AFC or TEMPERATURE variation |
1136 | 354 |
1183 // compute clocks ratio from measurements. | 401 // compute clocks ratio from measurements. |
1184 RATIO(nb_hf,nb_32khz,root,frac) | 402 RATIO(nb_hf,nb_32khz,root,frac) |
1185 | 403 |
1186 | 404 |
1187 // allow [-500ppm,+100ppm] derive on 32Khz at startup. | 405 // allow [-500ppm,+100ppm] derive on 32Khz at startup. |
1188 // Commenting section below for OMAPS00148004 | 406 #if 0 /* really old code, apparently */ |
1189 /* if ( | 407 if ( |
1190 (root > l1s.pw_mgr.c_clk_min || | 408 (root > l1s.pw_mgr.c_clk_min || |
1191 (root == l1s.pw_mgr.c_clk_min && | 409 (root == l1s.pw_mgr.c_clk_min && |
1192 frac >= l1s.pw_mgr.c_clk_init_min) ) && | 410 frac >= l1s.pw_mgr.c_clk_init_min) ) && |
1193 (root < l1s.pw_mgr.c_clk_max || | 411 (root < l1s.pw_mgr.c_clk_max || |
1194 (root == l1s.pw_mgr.c_clk_max && | 412 (root == l1s.pw_mgr.c_clk_max && |
1195 frac <= l1s.pw_mgr.c_clk_init_max ) ) | 413 frac <= l1s.pw_mgr.c_clk_init_max ) ) |
1196 */ | 414 #elif 1 /* TCS211 reconstruction */ |
415 if ( | |
416 (root == l1s.pw_mgr.c_clk_min && | |
417 frac >= l1s.pw_mgr.c_clk_init_min ) || | |
418 (root == l1s.pw_mgr.c_clk_max && | |
419 frac <= l1s.pw_mgr.c_clk_init_max ) | |
420 #else /* LoCosto code */ | |
1197 if ( | 421 if ( |
1198 ( l1s.pw_mgr.c_clk_min == l1s.pw_mgr.c_clk_max && | 422 ( l1s.pw_mgr.c_clk_min == l1s.pw_mgr.c_clk_max && |
1199 frac >= l1s.pw_mgr.c_clk_init_min && | 423 frac >= l1s.pw_mgr.c_clk_init_min && |
1200 frac <= l1s.pw_mgr.c_clk_init_max ) | 424 frac <= l1s.pw_mgr.c_clk_init_max ) |
1201 || | 425 || |
1204 frac >= l1s.pw_mgr.c_clk_init_min ) || | 428 frac >= l1s.pw_mgr.c_clk_init_min ) || |
1205 (root > l1s.pw_mgr.c_clk_min && | 429 (root > l1s.pw_mgr.c_clk_min && |
1206 root < l1s.pw_mgr.c_clk_max ) || | 430 root < l1s.pw_mgr.c_clk_max ) || |
1207 (root == l1s.pw_mgr.c_clk_max && | 431 (root == l1s.pw_mgr.c_clk_max && |
1208 frac <= l1s.pw_mgr.c_clk_init_max ) ) ) | 432 frac <= l1s.pw_mgr.c_clk_init_max ) ) ) |
433 #endif | |
1209 ) | 434 ) |
1210 { | 435 { |
1211 l1s.pw_mgr.histo[idx ][0] = nb_32khz; // init histo with the number of 32kHz | 436 l1s.pw_mgr.histo[idx ][0] = nb_32khz; // init histo with the number of 32kHz |
1212 l1s.pw_mgr.histo[idx++][1] = nb_hf; // init histo with the number of hf (13Mhz) | 437 l1s.pw_mgr.histo[idx++][1] = nb_hf; // init histo with the number of hf (13Mhz) |
1213 | 438 |
1324 l1s.pw_mgr.state = gauging_state; | 549 l1s.pw_mgr.state = gauging_state; |
1325 l1s.pw_mgr.lf = nb_32khz ; | 550 l1s.pw_mgr.lf = nb_32khz ; |
1326 // WARNING WARNING, this case gauging_state == UPDATE modify the algo. | 551 // WARNING WARNING, this case gauging_state == UPDATE modify the algo. |
1327 // In case of trace the parameter root and frac are refresh. | 552 // In case of trace the parameter root and frac are refresh. |
1328 // it is not the case if no trace and it seems there is mistake | 553 // it is not the case if no trace and it seems there is mistake |
554 #if 0 /* FreeCalypso TCS211 reconstruction */ | |
1329 if (gauging_state == UPDATE) | 555 if (gauging_state == UPDATE) |
1330 { | 556 { |
1331 RATIO2(sumHF,sumLF,root,frac); | 557 RATIO2(sumHF,sumLF,root,frac); |
1332 } | 558 } |
559 #endif | |
1333 //End of Warning. | 560 //End of Warning. |
1334 l1s.pw_mgr.hf = nb_hf ; | 561 l1s.pw_mgr.hf = nb_hf ; |
1335 l1s.pw_mgr.root = root ; | 562 l1s.pw_mgr.root = root ; |
1336 l1s.pw_mgr.frac = frac ; | 563 l1s.pw_mgr.frac = frac ; |
1337 #endif // End Trace gauging | 564 #endif // End Trace gauging |
1338 } | 565 } |
1339 } | 566 } |
1340 | 567 |
1341 | 568 |
1342 | |
1343 | |
1344 /* GAUGING_Handler() */ | 569 /* GAUGING_Handler() */ |
1345 /* Description: update increment counter for 32Khz */ | 570 /* Description: update increment counter for 32Khz */ |
1346 /* This interrupt function computes the ratio between */ | 571 /* This interrupt function computes the ratio between */ |
1347 /* HF/32Khz gauging counters and program ULPD increment */ | 572 /* HF/32Khz gauging counters and program ULPD increment */ |
1348 /* values. */ | 573 /* values. */ |
1381 l1ctl_gauging(DEFAULT_32KHZ_VALUE,DEFAULT_HFMHZ_VALUE); | 606 l1ctl_gauging(DEFAULT_32KHZ_VALUE,DEFAULT_HFMHZ_VALUE); |
1382 #endif | 607 #endif |
1383 } | 608 } |
1384 | 609 |
1385 | 610 |
1386 | |
1387 | |
1388 // l1s_get_HWTimers_ticks() | 611 // l1s_get_HWTimers_ticks() |
1389 // Description: | 612 // Description: |
1390 // evaluate the loading of the HW Timers for dep sleep | 613 // evaluate the loading of the HW Timers for dep sleep |
1391 // BIG SLEEP: timers CLK may be stopped (user dependant) | 614 // BIG SLEEP: timers CLK may be stopped (user dependant) |
1392 // DEEP SLEEP:timers CLK and WTCHDOG CLK are stopped | 615 // DEEP SLEEP:timers CLK and WTCHDOG CLK are stopped |
1394 // setup time | 617 // setup time |
1395 | 618 |
1396 WORD32 l1s_get_HWTimers_ticks(void) | 619 WORD32 l1s_get_HWTimers_ticks(void) |
1397 { | 620 { |
1398 #if (CODE_VERSION != SIMULATION) | 621 #if (CODE_VERSION != SIMULATION) |
1399 if (l1_config.pwr_mngt == PWR_MNGT) | |
1400 { | |
1401 WORD32 timer1,timer2,watchdog,HWTimer; | 622 WORD32 timer1,timer2,watchdog,HWTimer; |
1402 #if (CHIPSET == 12) || (CHIPSET == 15) | 623 #if (CHIPSET == 12) || (CHIPSET == 15) |
1403 WORD32 watchdog_sec; | 624 WORD32 watchdog_sec; |
1404 #endif | 625 #endif |
1405 UWORD16 cntlreg; | 626 UWORD16 cntlreg; |
1418 #endif | 639 #endif |
1419 | 640 |
1420 cntlreg = Dtimer1_Get_cntlreg(); // AND 0x1F | 641 cntlreg = Dtimer1_Get_cntlreg(); // AND 0x1F |
1421 if ( (cntlreg & D_TIMER_RUN) == D_TIMER_RUN) | 642 if ( (cntlreg & D_TIMER_RUN) == D_TIMER_RUN) |
1422 { | 643 { |
1423 cntlreg = cntlreg&0x1F; | 644 #if 0 /* match TCS211 object */ |
645 cntlreg = cntlreg&0x1F; | |
646 #endif | |
1424 cntlreg >>= 2; // take PTV | 647 cntlreg >>= 2; // take PTV |
1425 cntlreg = 1 << (cntlreg+1); | 648 cntlreg = 1 << (cntlreg+1); |
1426 timer1 = (WORD32) ( ((Dtimer1_ReadValue()+1) * cntlreg * 0.0012308) / 4.615 ); | 649 timer1 = (WORD32) ( ((Dtimer1_ReadValue()+1) * cntlreg * 0.0012308) / 4.615 ); |
1427 if (timer1 <= MIN_SLEEP_TIME) return(0); | 650 if (timer1 <= MIN_SLEEP_TIME) return(0); |
1428 old = Dtimer1_ReadValue(); | 651 old = Dtimer1_ReadValue(); |
1430 } | 653 } |
1431 | 654 |
1432 cntlreg = Dtimer2_Get_cntlreg(); | 655 cntlreg = Dtimer2_Get_cntlreg(); |
1433 if ( (cntlreg & D_TIMER_RUN) == D_TIMER_RUN) | 656 if ( (cntlreg & D_TIMER_RUN) == D_TIMER_RUN) |
1434 { | 657 { |
1435 cntlreg = cntlreg&0x1F; | 658 #if 0 /* match TCS211 object */ |
659 cntlreg = cntlreg&0x1F; | |
660 #endif | |
1436 cntlreg >>= 2; // take PTV | 661 cntlreg >>= 2; // take PTV |
1437 cntlreg = 1 << (cntlreg+1); | 662 cntlreg = 1 << (cntlreg+1); |
1438 timer2 = (WORD32) ( ((Dtimer2_ReadValue()+1) * cntlreg * 0.0012308) / 4.615 ); | 663 timer2 = (WORD32) ( ((Dtimer2_ReadValue()+1) * cntlreg * 0.0012308) / 4.615 ); |
1439 if (timer2 <= MIN_SLEEP_TIME) return(0); | 664 if (timer2 <= MIN_SLEEP_TIME) return(0); |
1440 if (HWTimer == -1) HWTimer = timer2; | 665 if (HWTimer == -1) HWTimer = timer2; |
1479 } | 704 } |
1480 | 705 |
1481 #endif | 706 #endif |
1482 | 707 |
1483 return (HWTimer); | 708 return (HWTimer); |
1484 } | |
1485 #else // simulation part | 709 #else // simulation part |
1486 return (-1); // no HW timer in simulation | 710 return (-1); // no HW timer in simulation |
1487 #endif | 711 #endif |
1488 return(-1); //omaps00090550 | |
1489 } | 712 } |
1490 | 713 |
1491 #if (GSM_IDLE_RAM != 0) // Compile only if GSM_IDLE_RAM enabled | 714 #if (GSM_IDLE_RAM != 0) // Compile only if GSM_IDLE_RAM enabled |
1492 | 715 |
1493 void l1s_adapt_traffic_controller(void) | 716 void l1s_adapt_traffic_controller(void) |
1521 #endif | 744 #endif |
1522 } | 745 } |
1523 } | 746 } |
1524 #endif | 747 #endif |
1525 | 748 |
749 UWORD32 last_wakeup = 0; | |
750 UWORD8 wakeup_type; // Type of the interrupt | |
751 UWORD8 why_big_sleep; // Type of the big sleep | |
752 | |
753 extern UWORD16 int_id; | |
1526 | 754 |
1527 // l1s_sleep_manager() | 755 // l1s_sleep_manager() |
1528 // Description: | 756 // Description: |
1529 // evaluate the loading of the system | 757 // evaluate the loading of the system |
1530 // - SIM, UART, LCD .... | 758 // - SIM, UART, LCD .... |
1543 UWORD32 sleep_time = l1s.actual_time.fn_mod42432; | 771 UWORD32 sleep_time = l1s.actual_time.fn_mod42432; |
1544 #else | 772 #else |
1545 UWORD32 sleep_time = l1s.actual_time.fn; | 773 UWORD32 sleep_time = l1s.actual_time.fn; |
1546 #endif | 774 #endif |
1547 | 775 |
1548 #if(CHIPSET == 15) | |
1549 Uint8 sleep_status; | |
1550 #endif | |
1551 | |
1552 #if (GSM_IDLE_RAM != 0) | |
1553 T_L1S_GSM_IDLE_INTRAM * gsm_idle_ram_ctl; | |
1554 BOOL flag_traffic_controller_state = 0; | |
1555 gsm_idle_ram_ctl = &(l1s.gsm_idle_ram_ctl); | |
1556 | |
1557 #if (AUDIO_TASK == 1) | |
1558 gsm_idle_ram_ctl->l1s_full_exec = l1s.l1_audio_it_com; | |
1559 #endif | |
1560 | |
1561 if (gsm_idle_ram_ctl->l1s_full_exec == TRUE) | |
1562 return; | |
1563 #endif | |
1564 | |
1565 if (l1_config.pwr_mngt == PWR_MNGT) | 776 if (l1_config.pwr_mngt == PWR_MNGT) |
1566 { | 777 { |
1567 // Power management is enabled | 778 // Power management is enabled |
1568 WORD32 min_time, OSload, HWtimer,wake_up_time,min_time_gauging; | 779 WORD32 min_time, HWtimer,wake_up_time,min_time_gauging; |
1569 UWORD32 sleep_mode; | |
1570 #if (ANALOG != 11) | |
1571 WORD32 afc_fix; | 780 WORD32 afc_fix; |
1572 #endif | 781 static UWORD32 previous_sleep = CLOCK_STOP; |
1573 UWORD32 uw32_store_next_time; | |
1574 #if (CHIPSET != 15) | |
1575 static UWORD32 previous_sleep = FRAME_STOP; | |
1576 #endif | |
1577 #if (W_A_CALYPSO_PLUS_SPR_19599 == 1) | 782 #if (W_A_CALYPSO_PLUS_SPR_19599 == 1) |
1578 BOOL extended_page_mode_state = 0; //Store state of extended page mode | 783 BOOL extended_page_mode_state = 0; //Store state of extended page mode |
1579 #endif | 784 #endif |
1580 #if (CHIPSET != 15) | |
1581 WORD32 time_from_last_wakeup=0; | 785 WORD32 time_from_last_wakeup=0; |
1582 #endif | 786 UWORD32 sleep_mode; |
1583 | 787 |
1584 #if (OP_BT == 1) | 788 #if (OP_BT == 1) |
1585 WORD32 hci_ll_status; | 789 WORD32 hci_ll_status; |
1586 #endif | 790 #endif |
1587 | 791 |
1588 // init for trace and debug | 792 // init for trace and debug |
1589 l1s.pw_mgr.why_big_sleep = BIG_SLEEP_DUE_TO_UNDEFINED; | 793 why_big_sleep = BIG_SLEEP_DUE_TO_UNDEFINED; |
1590 l1s.pw_mgr.wakeup_type = WAKEUP_FOR_UNDEFINED; | 794 wakeup_type = WAKEUP_FOR_UNDEFINED; |
1591 | 795 |
1592 #if (CHIPSET != 15) | 796 time_from_last_wakeup = (sleep_time - last_wakeup + 42432) % 42432; |
1593 time_from_last_wakeup = (sleep_time - l1s.pw_mgr.wakeup_time + 42432) % 42432; | 797 |
1594 #endif | 798 //================================================= |
1595 | 799 // check System (SIM, UART, LDC ..... ) |
800 //================================================= | |
801 sleep_mode = Cust_check_system(); | |
802 | |
803 if (sleep_mode == DO_NOT_SLEEP) | |
804 return; | |
1596 | 805 |
1597 #if (CODE_VERSION != SIMULATION) | 806 #if (CODE_VERSION != SIMULATION) |
1598 //================================================= | 807 //================================================= |
1599 // Protect System structures | 808 // Protect System structures |
1600 // must be called BEFORE INT_DisableIRQ() while | 809 // must be called BEFORE INT_DisableIRQ() while |
1604 //================================================= | 813 //================================================= |
1605 // Disable IRQ | 814 // Disable IRQ |
1606 //================================================= | 815 //================================================= |
1607 INT_DisableIRQ(); | 816 INT_DisableIRQ(); |
1608 #endif // NOT SIMULATION | 817 #endif // NOT SIMULATION |
1609 //================================================= | 818 |
1610 // check System (SIM, UART, LDC ..... ) | |
1611 //================================================= | |
1612 #if (CHIPSET == 15) | |
1613 #if (WCP_PROF == 0) | |
1614 sleep_mode = Check_Peripheral_App(); /* For Locosto */ | |
1615 #else | |
1616 sleep_mode = DO_NOT_SLEEP; //Check_Peripheral_App(); /* For Locosto */ | |
1617 #endif | |
1618 #else | |
1619 sleep_mode = Cust_check_system(); | |
1620 #endif | |
1621 | |
1622 #if (GSM_IDLE_RAM != 0) | |
1623 //================================================= | |
1624 // check System (SIM, UART, LDC ..... ) | |
1625 //================================================= | |
1626 gsm_idle_ram_ctl->sleep_mode = sleep_mode; | |
1627 #endif | |
1628 | |
1629 if (sleep_mode == DO_NOT_SLEEP) | |
1630 { | |
1631 OS_system_Unprotect(); | |
1632 // free System structure | |
1633 // Enable all IRQ | |
1634 //l1_pwmgr_irq_dis_flag = 0; | |
1635 #if (CODE_VERSION!=SIMULATION) | |
1636 INT_EnableIRQ(); | |
1637 l1_trace_fail_sleep(FAIL_SLEEP_PERIPH_CHECK, l1_pwmgr_debug.fail_id, l1_pwmgr_debug.fail_ret_val); | |
1638 #endif | |
1639 #if (GSM_IDLE_RAM != 0) | |
1640 gsm_idle_ram_ctl->os_load = 0; | |
1641 gsm_idle_ram_ctl->hw_timer = 0; | |
1642 #endif // GSM_IDLE_RAM | |
1643 return; | |
1644 } | |
1645 | |
1646 | |
1647 #if (OP_L1_STANDALONE == 0) | |
1648 /*GC_Sleep(); OMAPS00134004*/ | |
1649 #endif | |
1650 //================================================= | 819 //================================================= |
1651 // check OS loading | 820 // check OS loading |
1652 //================================================= | 821 //================================================= |
1653 OSload = OS_get_inactivity_ticks(); | 822 min_time = OS_get_inactivity_ticks(); |
1654 #if (CODE_VERSION!=SIMULATION) | |
1655 if ((OSload >= 0) && (OSload <= MIN_SLEEP_TIME)){ | |
1656 l1_pwmgr_debug.fail_id = FAIL_SLEEP_DUE_TO_OSLOAD; | |
1657 l1_pwmgr_debug.fail_ret_val = OSload; | |
1658 } | |
1659 #endif //NOT SIMULATION | |
1660 | 823 |
1661 //================================================= | 824 //================================================= |
1662 // check HW Timers loading | 825 // check HW Timers loading |
1663 //================================================= | 826 //================================================= |
1664 HWtimer= l1s_get_HWTimers_ticks(); | 827 HWtimer= l1s_get_HWTimers_ticks(); |
1665 #if (CODE_VERSION!=SIMULATION) | |
1666 if (HWtimer == 0){ | |
1667 l1_pwmgr_debug.fail_id = FAIL_SLEEP_DUE_TO_HWTIMER; | |
1668 l1_pwmgr_debug.fail_ret_val = 0; | |
1669 } | |
1670 #endif //NOT SIMULATION | |
1671 | |
1672 #if (GSM_IDLE_RAM != 0) | |
1673 //================================================= | |
1674 // check OS loading | |
1675 //================================================= | |
1676 gsm_idle_ram_ctl->os_load = OSload; | |
1677 | |
1678 //================================================= | |
1679 // check HW Timers loading | |
1680 //================================================= | |
1681 gsm_idle_ram_ctl->hw_timer = HWtimer; | |
1682 #endif // GSM_IDLE_RAM | |
1683 | |
1684 if ((OSload > 0) && (OSload <= MIN_SLEEP_TIME)) | |
1685 OSload =0; | |
1686 | 828 |
1687 //================================================= | 829 //================================================= |
1688 // check next gauging task for Packet Idle | 830 // check next gauging task for Packet Idle |
1689 //================================================= | 831 //================================================= |
1690 #if L1_GPRS | 832 #if L1_GPRS |
1691 min_time_gauging = l1s_get_next_gauging_in_Packet_Idle(); | 833 min_time_gauging = l1s_get_next_gauging_in_Packet_Idle(); |
1692 #else | 834 #else |
1693 min_time_gauging = -1; // not used | 835 min_time_gauging = -1; // not used |
1694 #endif | 836 #endif |
1695 #if (CODE_VERSION!=SIMULATION) | |
1696 if (min_time_gauging == 0){ | |
1697 l1_pwmgr_debug.fail_id = FAIL_SLEEP_DUE_TO_MINTIMEGAUGING; | |
1698 l1_pwmgr_debug.fail_ret_val = 0; | |
1699 } | |
1700 #endif // NOT SIMULATION | |
1701 | |
1702 | 837 |
1703 #if (OP_BT == 1) | 838 #if (OP_BT == 1) |
1704 hci_ll_status = hci_ll_ok_for_sleep(); | 839 hci_ll_status = hci_ll_ok_for_sleep(); |
1705 #endif | 840 #endif |
1706 // check if immediate activity planned | 841 // check if immediate activity planned |
1707 // 0 means immediate activity | 842 // 0 means immediate activity |
1708 // in case big sleep is choosen (sleep mode == FRAME_STOP) because of UART or SIM, | 843 // in case big sleep is choosen (sleep mode == FRAME_STOP) because of UART or SIM, |
1709 // return and wait end of this activity (few TDMA frames) then check on next TDMA frames | 844 // return and wait end of this activity (few TDMA frames) then check on next TDMA frames |
1710 // if MS can go in deep sleep | 845 // if MS can go in deep sleep |
1711 if ( !OSload | 846 if ( !min_time |
1712 || !HWtimer | 847 || !HWtimer |
1713 || !min_time_gauging | 848 || !min_time_gauging |
1714 #if (CHIPSET != 15) | 849 || (sleep_mode != CLOCK_STOP) |
1715 || ((sleep_mode != CLOCK_STOP) && ((l1s.pw_mgr.why_big_sleep == BIG_SLEEP_DUE_TO_UART) || (l1s.pw_mgr.why_big_sleep == BIG_SLEEP_DUE_TO_SIM))) | |
1716 #endif | |
1717 #if (OP_BT == 1) | 850 #if (OP_BT == 1) |
1718 || !hci_ll_status | 851 || !hci_ll_status |
1719 #endif | 852 #endif |
1720 ) | 853 ) |
1721 { | 854 { |
1722 | 855 |
1723 | |
1724 | |
1725 #if (OP_L1_STANDALONE == 0) | |
1726 /*GC_Wakeup(); OMAPS00134004*/ | |
1727 #endif | |
1728 | 856 |
1729 #if (CODE_VERSION != SIMULATION) | 857 #if (CODE_VERSION != SIMULATION) |
1730 OS_system_Unprotect(); | 858 OS_system_Unprotect(); |
1731 // free System structure | 859 // free System structure |
1732 // Enable all IRQ | 860 // Enable all IRQ |
1733 INT_EnableIRQ(); | 861 INT_EnableIRQ(); |
1734 // Wake up UART | 862 // Wake up UART |
1735 #if (GSM_IDLE_RAM != 0) | 863 |
1736 // Traffic controller has to be enabled before calling SER_WakeUpUarts | |
1737 // as this function can access the external RAM. | |
1738 // Reset the flag that will indicates if an interrup will put the traffic | |
1739 // controller ON during that time. | |
1740 l1s.gsm_idle_ram_ctl.trff_ctrl_enable_cause_int = FALSE; | |
1741 if (!READ_TRAFFIC_CONT_STATE) | |
1742 { | |
1743 flag_traffic_controller_state = 1; | |
1744 CSMI_TrafficControllerOn(); | |
1745 } | |
1746 #endif | |
1747 | |
1748 #if (CHIPSET != 15) | |
1749 SER_WakeUpUarts(); // Wake up Uarts | 864 SER_WakeUpUarts(); // Wake up Uarts |
1750 #else | 865 |
1751 // To be checked if this needs a change | 866 #endif |
1752 #endif | |
1753 | |
1754 #if (GSM_IDLE_RAM != 0) | |
1755 // The traffic controller state shall be restored as it was before | |
1756 // calling SER_WakeUpUarts. Do not disable it if an interrup occured | |
1757 // in between and activated the traffic controller. | |
1758 if ((flag_traffic_controller_state == 1) && (l1s.gsm_idle_ram_ctl.trff_ctrl_enable_cause_int == FALSE)) | |
1759 { | |
1760 CSMI_TrafficControllerOff(); | |
1761 } | |
1762 flag_traffic_controller_state = 0; | |
1763 #endif | |
1764 #endif | |
1765 #if (CODE_VERSION!=SIMULATION) | |
1766 l1_trace_fail_sleep(FAIL_SLEEP_OSTIMERGAUGE, l1_pwmgr_debug.fail_id, l1_pwmgr_debug.fail_ret_val); | |
1767 #endif | |
1768 return; | 867 return; |
1769 } | 868 } |
1770 //================================================= | 869 //================================================= |
1771 // Select sleep duration .... | 870 // Select sleep duration .... |
1772 //================================================= | 871 //================================================= |
1773 // remember: -1 means no activity planned | 872 // remember: -1 means no activity planned |
1774 min_time = OSload; | |
1775 //l1a_l1s_com.time_to_next_l1s_task is UW32, min_time is W32. Max value of l1a_l1s_com.time_to_next_l1s_task will be 2p31 | 873 //l1a_l1s_com.time_to_next_l1s_task is UW32, min_time is W32. Max value of l1a_l1s_com.time_to_next_l1s_task will be 2p31 |
1776 //and ,min_time max value will be 2p30. If min_time > l1a_l1s_com.time_to_next_l1s_task, | 874 //and ,min_time max value will be 2p30. If min_time > l1a_l1s_com.time_to_next_l1s_task, |
1777 //means MSB of l1a_l1s_com.time_to_next_l1s_task is zero. so, we can use- uw32_store_next_time & 0x7FFFFFFF | 875 //means MSB of l1a_l1s_com.time_to_next_l1s_task is zero. so, we can use- uw32_store_next_time & 0x7FFFFFFF |
1778 uw32_store_next_time = l1a_l1s_com.time_to_next_l1s_task; | 876 |
1779 | 877 if (min_time == -1) min_time = l1a_l1s_com.time_to_next_l1s_task; |
1780 if (min_time == -1) min_time = (WORD32)uw32_store_next_time; | 878 else MIN(min_time, l1a_l1s_com.time_to_next_l1s_task) |
1781 //else MIN(min_time, (WORD32)l1a_l1s_com.time_to_next_l1s_task) | |
1782 else | |
1783 { | |
1784 if(min_time > l1a_l1s_com.time_to_next_l1s_task) min_time = uw32_store_next_time & 0x7FFFFFFF; | |
1785 //else min_time = min_time; | |
1786 } | |
1787 if (HWtimer != -1) MIN(min_time, HWtimer) | 879 if (HWtimer != -1) MIN(min_time, HWtimer) |
1788 if (min_time_gauging != -1) MIN(min_time, min_time_gauging) | 880 if (min_time_gauging != -1) MIN(min_time, min_time_gauging) |
1789 | 881 |
1790 #if (TRACE_TYPE !=0 ) && (TRACE_TYPE != 2) && (TRACE_TYPE != 3) | 882 #if (TRACE_TYPE !=0 ) && (TRACE_TYPE != 2) && (TRACE_TYPE != 3) |
1791 // to trace the Wake up source | 883 // to trace the Wake up source |
1792 // depending of min_time choose the wakeup_type | 884 // depending of min_time choose the wakeup_type |
1793 l1s.pw_mgr.wakeup_type = WAKEUP_FOR_L1_TASK; | 885 wakeup_type = WAKEUP_FOR_OS_TASK; |
1794 if (min_time == l1a_l1s_com.time_to_next_l1s_task) l1s.pw_mgr.wakeup_type = WAKEUP_FOR_L1_TASK; | 886 if (min_time == l1a_l1s_com.time_to_next_l1s_task) wakeup_type = WAKEUP_FOR_L1_TASK; |
1795 if (min_time == HWtimer) l1s.pw_mgr.wakeup_type = WAKEUP_FOR_HW_TIMER_TASK; | 887 if (min_time == HWtimer) wakeup_type = WAKEUP_FOR_HW_TIMER_TASK; |
1796 if (min_time == min_time_gauging) l1s.pw_mgr.wakeup_type = WAKEUP_FOR_GAUGING_TASK; | 888 if (min_time == min_time_gauging) wakeup_type = WAKEUP_FOR_GAUGING_TASK; |
1797 if (min_time == OSload) l1s.pw_mgr.wakeup_type = WAKEUP_FOR_OS_TASK; | |
1798 #endif | 889 #endif |
1799 | 890 |
1800 //================================================= | 891 //================================================= |
1801 // Choose DEEP or BIG SLEEP | 892 // Choose DEEP or BIG SLEEP |
1802 //================================================= | 893 //================================================= |
1818 l1s.pw_mgr.sleep_performed = CLOCK_STOP; | 909 l1s.pw_mgr.sleep_performed = CLOCK_STOP; |
1819 else | 910 else |
1820 { | 911 { |
1821 // BIG SLEEP is chosen : check the reason | 912 // BIG SLEEP is chosen : check the reason |
1822 l1s.pw_mgr.sleep_performed = FRAME_STOP; | 913 l1s.pw_mgr.sleep_performed = FRAME_STOP; |
1823 if ((l1s.pw_mgr.enough_gaug != TRUE) && (l1a_l1s_com.mode != CS_MODE0)) | 914 if (l1s.pw_mgr.enough_gaug != TRUE) |
1824 l1s.pw_mgr.why_big_sleep = BIG_SLEEP_DUE_TO_GAUGING; | 915 why_big_sleep = BIG_SLEEP_DUE_TO_GAUGING; |
1825 else | 916 else |
1826 l1s.pw_mgr.why_big_sleep = BIG_SLEEP_DUE_TO_DSP_TRACES; | 917 why_big_sleep = BIG_SLEEP_DUE_TO_DSP_TRACES; |
1827 } | 918 } |
1828 } | 919 } |
1829 if (l1s.pw_mgr.mode_authorized == BIG_SLEEP) | 920 if (l1s.pw_mgr.mode_authorized == BIG_SLEEP) |
1830 l1s.pw_mgr.why_big_sleep = BIG_SLEEP_DUE_TO_SLEEP_MODE; | 921 why_big_sleep = BIG_SLEEP_DUE_TO_SLEEP_MODE; |
1831 | 922 |
1832 if ( ((l1s.pw_mgr.mode_authorized == BIG_SLEEP) && (sleep_mode >= FRAME_STOP)) || | 923 if ( ((l1s.pw_mgr.mode_authorized == BIG_SLEEP) && (sleep_mode >= FRAME_STOP)) || |
1833 ((l1s.pw_mgr.mode_authorized >= DEEP_SLEEP) && (sleep_mode == FRAME_STOP)) ) | 924 ((l1s.pw_mgr.mode_authorized >= DEEP_SLEEP) && (sleep_mode == FRAME_STOP)) ) |
1834 l1s.pw_mgr.sleep_performed = FRAME_STOP; | 925 l1s.pw_mgr.sleep_performed = FRAME_STOP; |
1835 | 926 |
1836 | 927 |
1837 | |
1838 #if (CHIPSET != 15) | |
1839 if ((previous_sleep == CLOCK_STOP) && (time_from_last_wakeup < 7)) | 928 if ((previous_sleep == CLOCK_STOP) && (time_from_last_wakeup < 7)) |
1840 { | 929 { |
1841 #if (CODE_VERSION != SIMULATION) | 930 #if (CODE_VERSION != SIMULATION) |
1842 OS_system_Unprotect(); // free System structure | 931 OS_system_Unprotect(); // free System structure |
1843 INT_EnableIRQ(); // Enable all IRQ | 932 INT_EnableIRQ(); // Enable all IRQ |
1844 #if (GSM_IDLE_RAM != 0) | 933 |
1845 // Traffic controller has to be enabled before calling SER_WakeUpUarts | 934 SER_WakeUpUarts(); // Wake up Uarts |
1846 // as this function can access the external RAM. | 935 |
1847 // Reset the flag that will indicates if an interrup will put the traffic | |
1848 // controller ON during that time. | |
1849 l1s.gsm_idle_ram_ctl.trff_ctrl_enable_cause_int = FALSE; | |
1850 if (!READ_TRAFFIC_CONT_STATE) | |
1851 { | |
1852 flag_traffic_controller_state = 1; | |
1853 CSMI_TrafficControllerOn(); | |
1854 } | |
1855 #endif | |
1856 | |
1857 | |
1858 SER_WakeUpUarts(); // Wake up Uarts | |
1859 | |
1860 | |
1861 | |
1862 #if (GSM_IDLE_RAM != 0) | |
1863 // The traffic controller state shall be restored as it was before | |
1864 // calling SER_WakeUpUarts. Do not disable it if an interrup occured | |
1865 // in between and activated the traffic controller. | |
1866 if ((flag_traffic_controller_state == 1) && (l1s.gsm_idle_ram_ctl.trff_ctrl_enable_cause_int == FALSE)) | |
1867 { | |
1868 CSMI_TrafficControllerOff(); | |
1869 } | |
1870 flag_traffic_controller_state = 0; | |
1871 #endif | |
1872 #endif // NOT SIMULATION | 936 #endif // NOT SIMULATION |
1873 return; | 937 return; |
1874 } | 938 } |
1875 #else // CHIPSET == 15 | 939 |
1876 | |
1877 | |
1878 | |
1879 if (l1s.pw_mgr.sleep_performed == CLOCK_STOP) | |
1880 { | |
1881 | |
1882 #if (CODE_VERSION != SIMULATION) | |
1883 UWORD8 local_sleep_status; | |
1884 | |
1885 | |
1886 local_sleep_status = Peripheral_interface[UART_ID](SLEEP_CMD); | |
1887 sleep_status = local_sleep_status; | |
1888 if(local_sleep_status == 0) | |
1889 { | |
1890 l1_pwmgr_debug.fail_id = UART_ID; | |
1891 l1_pwmgr_debug.fail_ret_val = sleep_status; | |
1892 } | |
1893 | |
1894 OS_system_Unprotect(); | |
1895 local_sleep_status = Peripheral_interface[MADC_AS_ID](SLEEP_CMD); /* Call MADC & Stereo Sleep before I2C */ | |
1896 OS_system_protect(); | |
1897 sleep_status &= local_sleep_status; | |
1898 if(local_sleep_status == 0) | |
1899 { | |
1900 l1_pwmgr_debug.fail_id = MADC_AS_ID; | |
1901 l1_pwmgr_debug.fail_ret_val = sleep_status; | |
1902 } | |
1903 | |
1904 local_sleep_status = Peripheral_interface[USB_ID](SLEEP_CMD); | |
1905 sleep_status &= local_sleep_status; | |
1906 if(local_sleep_status == 0) | |
1907 { | |
1908 l1_pwmgr_debug.fail_id = USB_ID; | |
1909 l1_pwmgr_debug.fail_ret_val = sleep_status; | |
1910 } | |
1911 | |
1912 local_sleep_status = Peripheral_interface[USIM_ID](SLEEP_CMD); | |
1913 sleep_status &= local_sleep_status; | |
1914 if(local_sleep_status == 0) | |
1915 { | |
1916 l1_pwmgr_debug.fail_id = USIM_ID; | |
1917 l1_pwmgr_debug.fail_ret_val = sleep_status; | |
1918 } | |
1919 | |
1920 local_sleep_status = Peripheral_interface[I2C_ID](SLEEP_CMD); | |
1921 sleep_status &= local_sleep_status; | |
1922 if(local_sleep_status == 0) | |
1923 { | |
1924 l1_pwmgr_debug.fail_id = I2C_ID; | |
1925 l1_pwmgr_debug.fail_ret_val = sleep_status; | |
1926 } | |
1927 | |
1928 local_sleep_status = Peripheral_interface[LCD_ID](SLEEP_CMD); | |
1929 sleep_status &= local_sleep_status; | |
1930 if(local_sleep_status == 0) | |
1931 { | |
1932 l1_pwmgr_debug.fail_id = LCD_ID; | |
1933 l1_pwmgr_debug.fail_ret_val = sleep_status; | |
1934 } | |
1935 | |
1936 local_sleep_status = Peripheral_interface[CAMERA_ID](SLEEP_CMD); | |
1937 sleep_status &= local_sleep_status; | |
1938 if(local_sleep_status == 0) | |
1939 { | |
1940 l1_pwmgr_debug.fail_id = CAMERA_ID; | |
1941 l1_pwmgr_debug.fail_ret_val = sleep_status; | |
1942 } | |
1943 local_sleep_status = Peripheral_interface[BCI_ID](SLEEP_CMD); | |
1944 sleep_status &= local_sleep_status; | |
1945 if(local_sleep_status == 0) | |
1946 { | |
1947 l1_pwmgr_debug.fail_id = BCI_ID; | |
1948 l1_pwmgr_debug.fail_ret_val = sleep_status; | |
1949 } | |
1950 | |
1951 #endif // NOT SIMULATION | |
1952 if(!sleep_status) | |
1953 { | |
1954 | |
1955 #if (OP_L1_STANDALONE == 0) | |
1956 /*GC_Wakeup(); OMAPS00134004*/ | |
1957 #endif | |
1958 | |
1959 #if (CODE_VERSION != SIMULATION) | |
1960 OS_system_Unprotect(); | |
1961 l1_trace_fail_sleep(FAIL_SLEEP_PERIPH_SLEEP, l1_pwmgr_debug.fail_id, l1_pwmgr_debug.fail_ret_val); | |
1962 #endif // NOT SIMULATION | |
1963 local_sleep_status = Peripheral_interface[UART_ID](WAKE_CMD); //OMAPS00090550 | |
1964 local_sleep_status = Peripheral_interface[USB_ID](WAKE_CMD); //OMAPS00090550 | |
1965 local_sleep_status = Peripheral_interface[USIM_ID](WAKE_CMD); //OMAPS00090550 | |
1966 local_sleep_status = Peripheral_interface[I2C_ID](WAKE_CMD);//OMAPS00090550 | |
1967 local_sleep_status = Peripheral_interface[LCD_ID](WAKE_CMD);//OMAPS00090550 | |
1968 local_sleep_status = Peripheral_interface[CAMERA_ID](WAKE_CMD);//OMAPS00090550 | |
1969 local_sleep_status = Peripheral_interface[MADC_AS_ID](WAKE_CMD);//OMAPS00090550 | |
1970 local_sleep_status = Peripheral_interface[BCI_ID](WAKE_CMD); //wake up for battery charger interface//OMAPS00090550 | |
1971 INT_EnableIRQ(); | |
1972 return; | |
1973 } | |
1974 } | |
1975 | |
1976 #endif // CHIPSET == 15 | |
1977 | |
1978 #if (CHIPSET != 15) | |
1979 // update previous sleep | 940 // update previous sleep |
1980 previous_sleep = l1s.pw_mgr.sleep_performed; | 941 previous_sleep = l1s.pw_mgr.sleep_performed; |
1981 #endif | |
1982 | 942 |
1983 | 943 |
1984 #if (CODE_VERSION != SIMULATION) | 944 #if (CODE_VERSION != SIMULATION) |
1985 | 945 |
1986 #if (CHIPSET == 12) || (CHIPSET == 15) | 946 #if (CHIPSET == 12) || (CHIPSET == 15) |
2012 // If we have come in here during the inactive period of cell | 972 // If we have come in here during the inactive period of cell |
2013 // selection, then load the ULPD timers with default values | 973 // selection, then load the ULPD timers with default values |
2014 // (used when the MS lost the network: in this case the deep sleep may be used) | 974 // (used when the MS lost the network: in this case the deep sleep may be used) |
2015 if (l1a_l1s_com.mode == CS_MODE0) | 975 if (l1a_l1s_com.mode == CS_MODE0) |
2016 { | 976 { |
2017 l1ctl_pgm_clk32(DEFAULT_HFMHZ_VALUE*8,DEFAULT_32KHZ_VALUE); | 977 l1ctl_pgm_clk32(DEFAULT_HFMHZ_VALUE, DEFAULT_32KHZ_VALUE); |
2018 } | 978 } |
2019 | |
2020 #if (CHIPSET == 15) | |
2021 | |
2022 | |
2023 /* These APIs are to be provided by BSP */ | |
2024 // Disable_APC_BG(); | |
2025 gpio_sleep(); //LCD_Floating Pin Fix | |
2026 DBB_Configure_DS(); | |
2027 | |
2028 //gpio_sleep(); //LCD_Floating Pin Fix | |
2029 | |
2030 #endif | |
2031 | |
2032 | |
2033 } | 979 } |
2034 #if (CHIPSET == 15) | |
2035 else | |
2036 { | |
2037 //DBB_Configure_BS(); // Not used | |
2038 } | |
2039 #endif | |
2040 | |
2041 | |
2042 #if (CHIPSET == 15) | |
2043 // The following command writes '0' into CKM_OCPCLK register in DRP; | |
2044 // This is done before disabling DPLL | |
2045 // CKM_OCPCLK (R/W) = Address 0xFFFF040C | |
2046 // Bit 0: 0 ?OCP clock is the DCXO clock. | |
2047 // 1 ?OCP clock is the divided DSP clock | |
2048 // Bit 31:1 Not Used | |
2049 (drp_regs->CKM_OCPCLKL) &= (~(0x1)); | |
2050 asm(" NOP"); | |
2051 asm(" NOP"); | |
2052 #endif | |
2053 | |
2054 | 980 |
2055 | 981 |
2056 //============================================== | 982 //============================================== |
2057 // disable DPLL (do not provide clk to DSP & RIF (RIF)) | 983 // disable DPLL (do not provide clk to DSP & RIF (RIF)) |
2058 //============================================== | 984 //============================================== |
2059 #if ((CHIPSET ==4) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 10) || (CHIPSET == 11) || (CHIPSET == 12) || (CHIPSET == 15)) | 985 #if ((CHIPSET ==4) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 10) || (CHIPSET == 11) || (CHIPSET == 12) || (CHIPSET == 15)) |
2060 // disable DPLL (do not provide clk to DSP & RIF (Bridge)) | 986 // disable DPLL (do not provide clk to DSP & RIF (Bridge)) |
2061 ( * (volatile SYS_UWORD16 *) CLKM_CNTL_CLK) |= CLKM_DPLL_DIS ; /* CLKM_BRIDGE_DIS removed by Ranga*/ | 987 ( * (volatile SYS_UWORD16 *) CLKM_CNTL_CLK) |= CLKM_DPLL_DIS | CLKM_BRIDGE_DIS; |
2062 #endif | 988 #endif |
2063 | 989 |
2064 //============================================== | 990 //============================================== |
2065 // if CLOCK_STOP or FRAME-STOP : Asleep OMEGA (ABB) | 991 // if CLOCK_STOP or FRAME-STOP : Asleep OMEGA (ABB) |
2066 //============================================== | 992 //============================================== |
2067 #if (ANALOG != 11) | |
2068 afc_fix = ABB_sleep(l1s.pw_mgr.sleep_performed, l1s.afc); | 993 afc_fix = ABB_sleep(l1s.pw_mgr.sleep_performed, l1s.afc); |
2069 #else | |
2070 // Nothing to be done as it should be handled by BSP_TWL3029_Configure_DS/BS | |
2071 #endif | |
2072 | 994 |
2073 #if (OP_BT == 1) | 995 #if (OP_BT == 1) |
2074 hci_ll_go_to_sleep(); | 996 hci_ll_go_to_sleep(); |
2075 #endif | 997 #endif |
2076 //================================================= | 998 //================================================= |
2077 // STop SPI ..... | 999 // STop SPI ..... |
2078 //================================================= | 1000 //================================================= |
2079 | 1001 |
2080 #if(CHIPSET != 15) | 1002 *((volatile UWORD16 *)MEM_SPI)&=0xFFFE; // SPI CLK DISABLED |
2081 *((volatile UWORD16 *)MEM_SPI)&=0xFFFE; // SPI CLK DISABLED | |
2082 #endif | |
2083 #endif // NOT SIMULATION | 1003 #endif // NOT SIMULATION |
2084 | 1004 |
2085 | 1005 |
2086 //================================================= | 1006 //================================================= |
2087 // CQ19599: For Calypso+ chipset, extended page mode | 1007 // CQ19599: For Calypso+ chipset, extended page mode |
2107 //================================================= | 1027 //================================================= |
2108 //ULPD Timer can be loaded up to MAX_GSM_TIMER (possible in CS_MODE0) | 1028 //ULPD Timer can be loaded up to MAX_GSM_TIMER (possible in CS_MODE0) |
2109 if ( l1s.pw_mgr.sleep_performed == CLOCK_STOP ) | 1029 if ( l1s.pw_mgr.sleep_performed == CLOCK_STOP ) |
2110 { | 1030 { |
2111 // DEEP SLEEP -> need time to setup afc and rf | 1031 // DEEP SLEEP -> need time to setup afc and rf |
2112 wake_up_time = min_time - l1_config.params.rf_wakeup_tpu_scenario_duration; | 1032 wake_up_time = min_time - l1_config.params.setup_afc_and_rf; |
2113 #if (CODE_VERSION == NOT_SIMULATION) | |
2114 // Sleep one more TDMA - this is done as part of merging init and TPU control | |
2115 wake_up_time += 1; | |
2116 #endif | |
2117 | |
2118 } | 1033 } |
2119 else | 1034 else |
2120 // BIG SLEEP | 1035 // BIG SLEEP |
2121 wake_up_time = min_time - 1; | 1036 wake_up_time = min_time - 1; |
2122 | 1037 |
2169 arm7_deep_sleep(); | 1084 arm7_deep_sleep(); |
2170 #else // NO OP_WCP | 1085 #else // NO OP_WCP |
2171 #if (W_A_CALYPSO_BUG_01435 == 1) | 1086 #if (W_A_CALYPSO_BUG_01435 == 1) |
2172 f_arm_sleep_cmd(DEEP_SLEEP); | 1087 f_arm_sleep_cmd(DEEP_SLEEP); |
2173 #else | 1088 #else |
2174 //EMIF_SetConfReg ( 0, 0, 2 ,1 ,0); | |
2175 asm(" NOP"); | |
2176 asm(" NOP"); | |
2177 asm(" NOP"); | |
2178 asm(" NOP"); | |
2179 *((volatile UWORD16 *)CLKM_ARM_CLK) &= ~(CLKM_DEEP_SLEEP); // set deep sleep mode | 1089 *((volatile UWORD16 *)CLKM_ARM_CLK) &= ~(CLKM_DEEP_SLEEP); // set deep sleep mode |
2180 asm(" NOP"); | |
2181 asm(" NOP"); | |
2182 asm(" NOP"); | |
2183 asm(" NOP"); | |
2184 // set deep sleep mode in case it is not set back by hardware | |
2185 *((volatile UWORD16 *)CLKM_ARM_CLK) |= (CLKM_DEEP_SLEEP); | |
2186 | |
2187 //EMIF_SetConfReg ( 0, 0, 2 ,0 ,0); | |
2188 // *((volatile UWORD16 *)CLKM_ARM_CLK) &= 0xFFFF; // set deep sleep mode | |
2189 // *((volatile UWORD16 *)CLKM_ARM_CLK) &= ~(CLKM_MCLK_EN); // For Debug only | |
2190 | |
2191 | |
2192 #endif | 1090 #endif |
2193 #endif // OP_WCP | 1091 #endif // OP_WCP |
2194 } | 1092 } |
2195 else | 1093 else |
2196 { | 1094 { |
2198 | 1096 |
2199 //========================================================== | 1097 //========================================================== |
2200 //Shut down PERIPHERALS clocks UWIRE and ARMIO if authorized | 1098 //Shut down PERIPHERALS clocks UWIRE and ARMIO if authorized |
2201 //========================================================== | 1099 //========================================================== |
2202 | 1100 |
2203 #if(CHIPSET != 15) | 1101 UWORD16 clocks_stopped; //OMAPS90550- new |
2204 UWORD16 clocks_stopped; //OMAPS90550- new | |
2205 clocks_stopped = (l1s.pw_mgr.clocks & l1s.pw_mgr.modules_status); | 1102 clocks_stopped = (l1s.pw_mgr.clocks & l1s.pw_mgr.modules_status); |
2206 if((clocks_stopped & ARMIO_CLK_CUT) == ARMIO_CLK_CUT) | 1103 if((clocks_stopped & ARMIO_CLK_CUT) == ARMIO_CLK_CUT) |
2207 *((volatile UWORD16 *)ARMIO_CNTL_REG) &= ~(ARMIO_CLOCKEN); | 1104 *((volatile UWORD16 *)ARMIO_CNTL_REG) &= ~(ARMIO_CLOCKEN); |
2208 if((clocks_stopped & UWIRE_CLK_CUT) == UWIRE_CLK_CUT) | 1105 if((clocks_stopped & UWIRE_CLK_CUT) == UWIRE_CLK_CUT) |
2209 *((volatile UWORD16 *)(MEM_UWIRE + 0x8)) &= ~(0x0001); | 1106 *((volatile UWORD16 *)(MEM_UWIRE + 0x8)) &= ~(0x0001); |
2210 #else | |
2211 // Nothing to be done as it is taken care by Locosto_Configure_BS | |
2212 #endif | |
2213 | 1107 |
2214 #if (W_A_CALYPSO_BUG_01435 == 1) | 1108 #if (W_A_CALYPSO_BUG_01435 == 1) |
2215 f_arm_sleep_cmd(BIG_SLEEP); | 1109 f_arm_sleep_cmd(BIG_SLEEP); |
2216 #else | 1110 #else |
2217 | 1111 |
2242 #if (GSM_IDLE_RAM_DEBUG == 1) | 1136 #if (GSM_IDLE_RAM_DEBUG == 1) |
2243 (*( volatile unsigned short* )(0xFFFE4802)) |= (1 << 2); // GPIO-2=1 | 1137 (*( volatile unsigned short* )(0xFFFE4802)) |= (1 << 2); // GPIO-2=1 |
2244 #endif | 1138 #endif |
2245 | 1139 |
2246 | 1140 |
2247 l1s_wakeup(); | 1141 l1s_wakeup(); |
2248 | 1142 |
2249 #if (CHIPSET == 15) | 1143 last_wakeup = l1s.actual_time.fn_mod42432; |
2250 // The following command writes '1' into CKM_OCPCLK register in DRP; | 1144 |
2251 // This is done after the DPLL is up | 1145 if (last_wakeup == sleep_time) |
2252 // CKM_OCPCLK (R/W) = Address 0xFFFF040C | |
2253 // Bit 0: 0 ?OCP clock is the DCXO clock. | |
2254 // 1 ?OCP clock is the divided DSP clock | |
2255 // Bit 31:1 Not Used | |
2256 (drp_regs->CKM_OCPCLKL) |= (0x1); | |
2257 asm(" NOP"); | |
2258 asm(" NOP"); | |
2259 #endif | |
2260 | |
2261 l1s.pw_mgr.wakeup_time = l1s.actual_time.fn_mod42432; | |
2262 | |
2263 if (l1s.pw_mgr.wakeup_time == sleep_time) | |
2264 // sleep duration == 0 -> wakeup in the same frame as sleep | 1146 // sleep duration == 0 -> wakeup in the same frame as sleep |
2265 l1s.pw_mgr.wakeup_type = WAKEUP_ASYNCHRONOUS_SLEEP_DURATION_0; | 1147 wakeup_type = WAKEUP_ASYNCHRONOUS_SLEEP_DURATION_0; |
2266 | 1148 |
2267 #if (GSM_IDLE_RAM != 0) | 1149 #if (GSM_IDLE_RAM != 0) |
2268 // Update counters with sleep duration -> will be used case expiration in next wake up phase before traffic controller is enabled by msg sending | 1150 // Update counters with sleep duration -> will be used case expiration in next wake up phase before traffic controller is enabled by msg sending |
2269 gsm_idle_ram_ctl->os_load -= (l1s.pw_mgr.sleep_duration); | 1151 gsm_idle_ram_ctl->os_load -= (l1s.pw_mgr.sleep_duration); |
2270 gsm_idle_ram_ctl->hw_timer -= (l1s.pw_mgr.sleep_duration); | 1152 gsm_idle_ram_ctl->hw_timer -= (l1s.pw_mgr.sleep_duration); |
2284 if ( l1s.pw_mgr.sleep_performed == CLOCK_STOP ) | 1166 if ( l1s.pw_mgr.sleep_performed == CLOCK_STOP ) |
2285 { | 1167 { |
2286 // (*(volatile UWORD16 *)l1s_tpu_com.reg_cmd) = TPU_CTRL_CLK_EN; | 1168 // (*(volatile UWORD16 *)l1s_tpu_com.reg_cmd) = TPU_CTRL_CLK_EN; |
2287 UWORD8 local_sleep_status; | 1169 UWORD8 local_sleep_status; |
2288 | 1170 |
2289 | |
2290 #if (CHIPSET == 15) | |
2291 | |
2292 DBB_Wakeup_DS(); | |
2293 | |
2294 gpio_wakeup(); //LCD_Floating Pin Fix | |
2295 | |
2296 /* These APIs to be provided by BSP */ | |
2297 //Enable_APC_BG(); | |
2298 //BT_Wakeup(); | |
2299 //IRDA_Wakeup(); | |
2300 local_sleep_status = Peripheral_interface[UART_ID](WAKE_CMD); //OMAPS00090550 | |
2301 local_sleep_status = Peripheral_interface[USB_ID](WAKE_CMD);//OMAPS00090550 | |
2302 local_sleep_status = Peripheral_interface[USIM_ID](WAKE_CMD);//OMAPS00090550 | |
2303 local_sleep_status = Peripheral_interface[I2C_ID](WAKE_CMD);//OMAPS00090550 | |
2304 local_sleep_status = Peripheral_interface[LCD_ID](WAKE_CMD);//OMAPS00090550 | |
2305 local_sleep_status = Peripheral_interface[CAMERA_ID](WAKE_CMD);//OMAPS00090550 | |
2306 | |
2307 OS_system_Unprotect(); | |
2308 local_sleep_status = Peripheral_interface[MADC_AS_ID](WAKE_CMD);//OMAPS00090550 | |
2309 local_sleep_status = Peripheral_interface[BCI_ID](WAKE_CMD); //wake up for battery charger//OMAPS00090550 | |
2310 OS_system_protect(); | |
2311 //added for OMAPS00090550 warning removal | |
2312 if(local_sleep_status == 0) | |
2313 { | |
2314 l1_pwmgr_debug.fail_ret_val = local_sleep_status; | |
2315 } | |
2316 //upto this OMAPS00090550 | |
2317 | |
2318 | |
2319 #endif | |
2320 l1dmacro_RF_wakeup(); | 1171 l1dmacro_RF_wakeup(); |
2321 | 1172 |
2322 } | 1173 } |
2323 | 1174 |
2324 #if ((CHIPSET ==4) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 10) || (CHIPSET == 11)) | 1175 #if ((CHIPSET ==4) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 10) || (CHIPSET == 11)) |
2332 #endif | 1183 #endif |
2333 | 1184 |
2334 //================================================= | 1185 //================================================= |
2335 //if CLOCK_STOP or FRAME-STOP : ReStart SPI | 1186 //if CLOCK_STOP or FRAME-STOP : ReStart SPI |
2336 //================================================= | 1187 //================================================= |
2337 #if(CHIPSET != 15) | 1188 *((volatile UWORD16 *)MEM_SPI)|=0x0001; // SPI CLK ENABLED |
2338 *((volatile UWORD16 *)MEM_SPI)|=0x0001; // SPI CLK ENABLED | |
2339 #endif | |
2340 | 1189 |
2341 //================================================= | 1190 //================================================= |
2342 // Wake up ABB | 1191 // Wake up ABB |
2343 //================================================= | 1192 //================================================= |
2344 #if (ANALOG != 11) | |
2345 ABB_wakeup(l1s.pw_mgr.sleep_performed, l1s.afc); | 1193 ABB_wakeup(l1s.pw_mgr.sleep_performed, l1s.afc); |
2346 #else | |
2347 // Nothing to be done here as it will be handled by BSP_TWL3029_Wakeup_DS/BS | |
2348 #endif | |
2349 | 1194 |
2350 #if (OP_BT == 1) | 1195 #if (OP_BT == 1) |
2351 hci_ll_wake_up(); | 1196 hci_ll_wake_up(); |
2352 #endif | 1197 #endif |
2353 #endif //CODE VERSION | 1198 #endif //CODE VERSION |
2374 | 1219 |
2375 #if (TRACE_TYPE != 0) | 1220 #if (TRACE_TYPE != 0) |
2376 if (l1a_l1s_com.mode != CS_MODE0) // in this mode the trace prevent from going to deep sleep due to UART activity | 1221 if (l1a_l1s_com.mode != CS_MODE0) // in this mode the trace prevent from going to deep sleep due to UART activity |
2377 { | 1222 { |
2378 #if (GSM_IDLE_RAM == 0) | 1223 #if (GSM_IDLE_RAM == 0) |
2379 l1_trace_sleep(sleep_time,l1s.actual_time.fn_mod42432,l1s.pw_mgr.sleep_performed,l1s.pw_mgr.wakeup_type,l1s.pw_mgr.why_big_sleep, l1s.pw_mgr.wake_up_int_id); | 1224 l1_trace_sleep(sleep_time, l1s.actual_time.fn_mod42432, l1s.pw_mgr.sleep_performed, wakeup_type, why_big_sleep); |
2380 #else | 1225 #else |
2381 l1_trace_sleep_intram(sleep_time,l1s.actual_time.fn_mod42432,l1s.pw_mgr.sleep_performed,l1s.pw_mgr.wakeup_type,l1s.pw_mgr.why_big_sleep, l1s.pw_mgr.wake_up_int_id); | 1226 l1_trace_sleep_intram(sleep_time, l1s.actual_time.fn_mod42432, l1s.pw_mgr.sleep_performed, wakeup_type, why_big_sleep); |
2382 #if (TRACE_TYPE==1) || (TRACE_TYPE==4) | 1227 #if (TRACE_TYPE==1) || (TRACE_TYPE==4) |
2383 l1s_trace_mftab(); | 1228 l1s_trace_mftab(); |
2384 #endif | 1229 #endif |
2385 #endif | 1230 #endif |
2386 } | 1231 } |
2387 l1s.pw_mgr.wake_up_int_id = 0; | |
2388 #endif | 1232 #endif |
2389 | 1233 |
2390 #if (TRACE_TYPE == 1) || (TRACE_TYPE == 4) | 1234 #if (TRACE_TYPE == 1) || (TRACE_TYPE == 4) |
2391 trace_info.sleep_performed = TRUE; | 1235 trace_info.sleep_performed = TRUE; |
2392 #endif | 1236 #endif |
2425 CSMI_TrafficControllerOn(); | 1269 CSMI_TrafficControllerOn(); |
2426 } | 1270 } |
2427 #endif | 1271 #endif |
2428 | 1272 |
2429 | 1273 |
2430 | |
2431 #if (CHIPSET != 15) | |
2432 SER_WakeUpUarts(); // Wake up Uarts | 1274 SER_WakeUpUarts(); // Wake up Uarts |
2433 #else | |
2434 // To be checked if this needs a change | |
2435 #endif | |
2436 | 1275 |
2437 | 1276 |
2438 #if (GSM_IDLE_RAM != 0) | 1277 #if (GSM_IDLE_RAM != 0) |
2439 // The traffic controller state shall be restored as it was before | 1278 // The traffic controller state shall be restored as it was before |
2440 // calling SER_WakeUpUarts. Do not disable it if an interrup occured | 1279 // calling SER_WakeUpUarts. Do not disable it if an interrup occured |
2472 #else | 1311 #else |
2473 INTH_DISABLEONEIT(IQ_TGSM); // mask TGSM int. | 1312 INTH_DISABLEONEIT(IQ_TGSM); // mask TGSM int. |
2474 #endif | 1313 #endif |
2475 | 1314 |
2476 #if (CHIPSET == 12) || (CHIPSET == 15) | 1315 #if (CHIPSET == 12) || (CHIPSET == 15) |
2477 l1s.pw_mgr.wake_up_int_id = ((* (SYS_UWORD16 *) C_INTH_B_IRQ_REG) & C_INTH_SRC_NUM);// For debug: Save IRQ that causes the waking up | 1316 int_id = ((* (SYS_UWORD16 *) C_INTH_B_IRQ_REG) & C_INTH_SRC_NUM);// For debug: Save IRQ that causes the waking up |
2478 if ( l1s.pw_mgr.wake_up_int_id >= 256 ) | 1317 if ( int_id >= 256 ) |
2479 l1s.pw_mgr.wake_up_int_id = ((* (SYS_UWORD16 *) C_INTH_B_FIQ_REG) & C_INTH_SRC_NUM)+100; | 1318 int_id = ((* (SYS_UWORD16 *) C_INTH_B_FIQ_REG) & C_INTH_SRC_NUM)+100; |
2480 #else | 1319 #else |
2481 l1s.pw_mgr.wake_up_int_id = ((* (SYS_UWORD16 *) INTH_B_IRQ_REG) & INTH_SRC_NUM);// For debug: Save IRQ that causes the waking up | 1320 int_id = ((* (SYS_UWORD16 *) INTH_B_IRQ_REG) & INTH_SRC_NUM);// For debug: Save IRQ that causes the waking up |
2482 if ( l1s.pw_mgr.wake_up_int_id >= 256 ) | 1321 if ( int_id >= 256 ) |
2483 l1s.pw_mgr.wake_up_int_id = ((* (SYS_UWORD16 *) INTH_B_FIQ_REG) & INTH_SRC_NUM)+100; | 1322 int_id = ((* (SYS_UWORD16 *) INTH_B_FIQ_REG) & INTH_SRC_NUM)+100; |
2484 #endif | 1323 #endif |
2485 | 1324 |
2486 // clear pending IQ_FRAME it and unmask it | 1325 // clear pending IQ_FRAME it and unmask it |
2487 #if (CHIPSET == 12) || (CHIPSET == 15) | 1326 #if (CHIPSET == 12) || (CHIPSET == 15) |
2488 F_INTH_RESET_ONE_IT(C_INTH_FRAME_IT); | 1327 F_INTH_RESET_ONE_IT(C_INTH_FRAME_IT); |
2562 /***************************************************/ | 1401 /***************************************************/ |
2563 l1s.pw_mgr.frame_adjust = l1s_compute_wakeup_ticks(); | 1402 l1s.pw_mgr.frame_adjust = l1s_compute_wakeup_ticks(); |
2564 | 1403 |
2565 #if (TRACE_TYPE !=0 ) && (TRACE_TYPE != 2) && (TRACE_TYPE != 3) | 1404 #if (TRACE_TYPE !=0 ) && (TRACE_TYPE != 2) && (TRACE_TYPE != 3) |
2566 if ((l1s.pw_mgr.frame_adjust == TRUE)) | 1405 if ((l1s.pw_mgr.frame_adjust == TRUE)) |
2567 l1s.pw_mgr.wakeup_type = WAKEUP_BY_ASYNC_INTERRUPT; | 1406 wakeup_type = WAKEUP_BY_ASYNC_INTERRUPT; |
2568 #endif | 1407 #endif |
2569 | 1408 |
2570 | 1409 |
2571 /* Fix Frame */ | 1410 /* Fix Frame */ |
2572 | 1411 |
2670 /*-------------------------------------------------------*/ | 1509 /*-------------------------------------------------------*/ |
2671 BOOL l1s_compute_wakeup_ticks(void) | 1510 BOOL l1s_compute_wakeup_ticks(void) |
2672 { | 1511 { |
2673 UWORD16 temp_clear_intr; | 1512 UWORD16 temp_clear_intr; |
2674 #if (CODE_VERSION != SIMULATION) | 1513 #if (CODE_VERSION != SIMULATION) |
2675 if (l1_config.pwr_mngt == PWR_MNGT) | |
2676 { | |
2677 // read current value of count down counter | 1514 // read current value of count down counter |
2678 l1s.pw_mgr.sleep_duration = READ_ULDP_TIMER_VALUE; | 1515 l1s.pw_mgr.sleep_duration = READ_ULDP_TIMER_VALUE; |
2679 | 1516 |
2680 // if count down=0 it's a scheduled wake-up.... | 1517 // if count down=0 it's a scheduled wake-up.... |
2681 if (l1s.pw_mgr.sleep_duration == 0) | 1518 if (l1s.pw_mgr.sleep_duration == 0) |
2682 { | 1519 { |
2683 // read sleeping planned value in TPU INIT register | 1520 // read sleeping planned value in TPU INIT register |
2684 l1s.pw_mgr.sleep_duration = READ_ULDP_TIMER_INIT; | 1521 l1s.pw_mgr.sleep_duration = READ_ULDP_TIMER_INIT; |
2685 // INTH is different from the ULPD interrupt -> aynchronous wakeup | 1522 // INTH is different from the ULPD interrupt -> aynchronous wakeup |
2686 #if (CHIPSET == 12) || (CHIPSET == 15) | 1523 #if (CHIPSET == 12) || (CHIPSET == 15) |
2687 if (l1s.pw_mgr.wake_up_int_id != C_INTH_TGSM_IT) | 1524 if (int_id != C_INTH_TGSM_IT) |
2688 #else | 1525 #else |
2689 if (l1s.pw_mgr.wake_up_int_id != IQ_TGSM) | 1526 if (int_id != IQ_TGSM) |
2690 #endif | 1527 #endif |
2691 { | 1528 { |
2692 l1s.pw_mgr.wakeup_type = WAKEUP_ASYNCHRONOUS_ULPD_0; | 1529 wakeup_type = WAKEUP_ASYNCHRONOUS_ULPD_0; |
2693 // RESET IT_ULPD in ULPD module | 1530 // RESET IT_ULPD in ULPD module |
2694 // The ULDP_GSM_TIMER_IT_REG is a read only register and is cleared on reading the register | 1531 // The ULDP_GSM_TIMER_IT_REG is a read only register and is cleared on reading the register |
2695 temp_clear_intr =(* (volatile UWORD16 *) ULDP_GSM_TIMER_IT_REG) & ULPD_IT_TIMER_GSM; | 1532 temp_clear_intr =(* (volatile UWORD16 *) ULDP_GSM_TIMER_IT_REG) & ULPD_IT_TIMER_GSM; |
2696 #if (CHIPSET == 12) || (CHIPSET == 15) | 1533 #if (CHIPSET == 12) || (CHIPSET == 15) |
2697 // RESET IQ_TGSM (IT_ULPD) in IT register | 1534 // RESET IQ_TGSM (IT_ULPD) in IT register |
2698 F_INTH_RESET_ONE_IT(C_INTH_TGSM_IT); | 1535 F_INTH_RESET_ONE_IT(C_INTH_TGSM_IT); |
2699 // RESET IQ_FRAME in IT register | 1536 // RESET IQ_FRAME in IT register |
2700 F_INTH_RESET_ONE_IT(C_INTH_FRAME_IT); | 1537 F_INTH_RESET_ONE_IT(C_INTH_FRAME_IT); |
2701 l1s.pw_mgr.wake_up_int_id = C_INTH_TGSM_IT; | 1538 int_id = C_INTH_TGSM_IT; |
2702 #else | 1539 #else |
2703 // RESET IQ_TGSM (IT_ULPD) in IT register | 1540 // RESET IQ_TGSM (IT_ULPD) in IT register |
2704 INTH_RESETONEIT(IQ_TGSM); | 1541 INTH_RESETONEIT(IQ_TGSM); |
2705 // RESET IQ_FRAME in IT register | 1542 // RESET IQ_FRAME in IT register |
2706 INTH_RESETONEIT(IQ_FRAME); | 1543 INTH_RESETONEIT(IQ_FRAME); |
2707 l1s.pw_mgr.wake_up_int_id = IQ_TGSM; | 1544 int_id = IQ_TGSM; |
2708 #endif | 1545 #endif |
2709 return(FALSE); | 1546 return(FALSE); |
2710 } | 1547 } |
2711 else | 1548 else |
2712 return(FALSE); | 1549 return(FALSE); |
2715 { | 1552 { |
2716 // read sleeping planned value in TPU INIT register & compute time elapsed | 1553 // read sleeping planned value in TPU INIT register & compute time elapsed |
2717 l1s.pw_mgr.sleep_duration = READ_ULDP_TIMER_INIT - l1s.pw_mgr.sleep_duration; | 1554 l1s.pw_mgr.sleep_duration = READ_ULDP_TIMER_INIT - l1s.pw_mgr.sleep_duration; |
2718 return(TRUE); | 1555 return(TRUE); |
2719 } | 1556 } |
2720 } | 1557 #else |
2721 #endif | |
2722 return(FALSE);//omaps00090550 | 1558 return(FALSE);//omaps00090550 |
1559 #endif | |
2723 } | 1560 } |
2724 | 1561 |
2725 /*-------------------------------------------------------*/ | 1562 /*-------------------------------------------------------*/ |
2726 /* l1s_recover_Frame() */ | 1563 /* l1s_recover_Frame() */ |
2727 /*-------------------------------------------------------*/ | 1564 /*-------------------------------------------------------*/ |
2815 UWORD16 cntlreg; | 1652 UWORD16 cntlreg; |
2816 UWORD16 modereg; | 1653 UWORD16 modereg; |
2817 double duration; | 1654 double duration; |
2818 | 1655 |
2819 | 1656 |
2820 | |
2821 | |
2822 | |
2823 | |
2824 | |
2825 | |
2826 | |
2827 | |
2828 | |
2829 | |
2830 //WORD32 old;- OMAPS 90550 new | 1657 //WORD32 old;- OMAPS 90550 new |
2831 | 1658 |
2832 // read Hercules Timers & Watchdog | 1659 // read Hercules Timers & Watchdog |
2833 //================================================= | 1660 //================================================= |
2834 // Tint = Tclk * (LOAD_TIM+1) * 2^(PTV+1) | 1661 // Tint = Tclk * (LOAD_TIM+1) * 2^(PTV+1) |
2837 //------------------------------------------------- | 1664 //------------------------------------------------- |
2838 | 1665 |
2839 cntlreg = Dtimer1_Get_cntlreg(); | 1666 cntlreg = Dtimer1_Get_cntlreg(); |
2840 if ( (cntlreg & D_TIMER_RUN) == D_TIMER_RUN) | 1667 if ( (cntlreg & D_TIMER_RUN) == D_TIMER_RUN) |
2841 { | 1668 { |
2842 cntlreg = cntlreg&0x1F; | 1669 #if 0 /* match TCS211 object */ |
1670 cntlreg = cntlreg&0x1F; | |
1671 #endif | |
2843 cntlreg >>= 2; // take PTV | 1672 cntlreg >>= 2; // take PTV |
2844 cntlreg = 1 << (cntlreg+1); // compute 2^(PTV+1) | 1673 cntlreg = 1 << (cntlreg+1); // compute 2^(PTV+1) |
2845 // convert sleep duration in HWTimers ticks.... | 1674 // convert sleep duration in HWTimers ticks.... |
2846 duration = (l1s.pw_mgr.sleep_duration * 4.615 - (DELTA_TIME/32.768)) / (cntlreg * 0.0012308); | 1675 duration = (l1s.pw_mgr.sleep_duration * 4.615 - (DELTA_TIME/32.768)) / (cntlreg * 0.0012308); |
2847 if (duration < 0.0){ | 1676 #if 0 /* match TCS211 object */ |
2848 duration = 0.0; // This needs to be done for all the timers | 1677 if (duration < 0.0){ |
2849 } | 1678 duration = 0.0; // This needs to be done for all the timers |
1679 } | |
1680 #endif | |
2850 timer1 = Dtimer1_ReadValue() - (UWORD16) duration; | 1681 timer1 = Dtimer1_ReadValue() - (UWORD16) duration; |
2851 | 1682 |
2852 Dtimer1_Start(0); | 1683 Dtimer1_Start(0); |
2853 Dtimer1_WriteValue(timer1); | 1684 Dtimer1_WriteValue(timer1); |
2854 Dtimer1_Start(1); | 1685 Dtimer1_Start(1); |
2855 } | 1686 } |
2856 | 1687 |
2857 cntlreg = Dtimer2_Get_cntlreg(); | 1688 cntlreg = Dtimer2_Get_cntlreg(); |
2858 if ( (cntlreg & D_TIMER_RUN) == D_TIMER_RUN) | 1689 if ( (cntlreg & D_TIMER_RUN) == D_TIMER_RUN) |
2859 { | 1690 { |
2860 cntlreg = cntlreg&0x1F; | 1691 #if 0 /* match TCS211 object */ |
1692 cntlreg = cntlreg&0x1F; | |
1693 #endif | |
2861 cntlreg >>= 2; // take PTV | 1694 cntlreg >>= 2; // take PTV |
2862 cntlreg = 1 << (cntlreg+1); | 1695 cntlreg = 1 << (cntlreg+1); |
2863 // convert sleep duration in HWTimers ticks.... | 1696 // convert sleep duration in HWTimers ticks.... |
2864 duration = (l1s.pw_mgr.sleep_duration * 4.615 - (DELTA_TIME/32.768)) / (cntlreg * 0.0012308); | 1697 duration = (l1s.pw_mgr.sleep_duration * 4.615 - (DELTA_TIME/32.768)) / (cntlreg * 0.0012308); |
2865 if (duration < 0.0){ | 1698 #if 0 /* match TCS211 object */ |
2866 duration = 0.0; // This needs to be done for all the timers | 1699 if (duration < 0.0){ |
2867 } | 1700 duration = 0.0; // This needs to be done for all the timers |
1701 } | |
1702 #endif | |
2868 timer2 = Dtimer2_ReadValue() - (UWORD16) duration; | 1703 timer2 = Dtimer2_ReadValue() - (UWORD16) duration; |
2869 Dtimer2_Start(0); | 1704 Dtimer2_Start(0); |
2870 Dtimer2_WriteValue(timer2); | 1705 Dtimer2_WriteValue(timer2); |
2871 Dtimer2_Start(1); | 1706 Dtimer2_Start(1); |
2872 } | 1707 } |
2922 /* ------------ */ | 1757 /* ------------ */ |
2923 /* return the nbr of frames before the next gauging */ | 1758 /* return the nbr of frames before the next gauging */ |
2924 /* return -1 means no activity planned */ | 1759 /* return -1 means no activity planned */ |
2925 /*-------------------------------------------------------*/ | 1760 /*-------------------------------------------------------*/ |
2926 #if L1_GPRS | 1761 #if L1_GPRS |
2927 UWORD32 l1s_get_next_gauging_in_Packet_Idle(void) | 1762 UWORD32 next_gauging_scheduled_for_PNP; // gauging for Packet Idle |
1763 | |
1764 WORD32 l1s_get_next_gauging_in_Packet_Idle(void) | |
2928 { | 1765 { |
2929 WORD32 next_gauging; | 1766 WORD32 next_gauging; |
2930 | 1767 |
2931 // gauging performed with Normal Paging (we are in Idle mode) | 1768 // gauging performed with Normal Paging (we are in Idle mode) |
2932 if (l1a_l1s_com.l1s_en_task[NP] == TASK_ENABLED) | 1769 if (l1a_l1s_com.l1s_en_task[NP] == TASK_ENABLED) |
2933 return ((UWORD32)(-1)); // no activity planned //omaps00090550 | 1770 return (-1); // no activity planned |
2934 | 1771 |
2935 // we are not in Packet Idle Mode | 1772 // we are not in Packet Idle Mode |
2936 if (l1a_l1s_com.l1s_en_task[PNP] != TASK_ENABLED) | 1773 if (l1a_l1s_com.l1s_en_task[PNP] != TASK_ENABLED) |
2937 return ((UWORD32)(-1)); // no activity planned //omaps00090550 | 1774 return (-1); // no activity planned |
2938 | 1775 |
2939 next_gauging = l1s.next_gauging_scheduled_for_PNP - l1s.actual_time.fn ; | 1776 next_gauging = next_gauging_scheduled_for_PNP - l1s.actual_time.fn ; |
2940 if (next_gauging < 0) | 1777 if (next_gauging < 0) |
2941 next_gauging+=MAX_FN; | 1778 next_gauging+=MAX_FN; |
2942 | 1779 |
2943 if (next_gauging <= MIN_SLEEP_TIME) | 1780 if (next_gauging <= MIN_SLEEP_TIME) |
2944 return(0); | 1781 return(0); |
2955 /* */ | 1792 /* */ |
2956 /*-------------------------------------------------------*/ | 1793 /*-------------------------------------------------------*/ |
2957 #if L1_GPRS | 1794 #if L1_GPRS |
2958 BOOL l1s_gauging_decision_with_PNP(void) | 1795 BOOL l1s_gauging_decision_with_PNP(void) |
2959 { | 1796 { |
2960 #define TWO_SECONDS_IN_FRAME (UWORD16)(2000/4.615) | 1797 #define TWO_SECONDS_IN_FRAME (UWORD16)(2000/4.615) |
2961 WORD32 time_to_next_gauging=0; //changed to WORD32- sajal | 1798 |
2962 // It's time to perform the next gauging | 1799 /* reconstructed TCS211 code */ |
2963 time_to_next_gauging = l1s.next_gauging_scheduled_for_PNP - l1s.actual_time.fn; | 1800 if (l1s.actual_time.fn >= next_gauging_scheduled_for_PNP) |
2964 if (time_to_next_gauging < 0) | 1801 { |
2965 { | 1802 next_gauging_scheduled_for_PNP = l1s.actual_time.fn + TWO_SECONDS_IN_FRAME; |
2966 time_to_next_gauging += MAX_FN; | 1803 if (next_gauging_scheduled_for_PNP >= MAX_FN) next_gauging_scheduled_for_PNP -= MAX_FN; |
2967 } | |
2968 | |
2969 if( (time_to_next_gauging == 0) || (time_to_next_gauging > TWO_SECONDS_IN_FRAME)) | |
2970 { | |
2971 | |
2972 l1s.next_gauging_scheduled_for_PNP = l1s.actual_time.fn + TWO_SECONDS_IN_FRAME; | |
2973 if (l1s.next_gauging_scheduled_for_PNP >= MAX_FN) l1s.next_gauging_scheduled_for_PNP -= MAX_FN; | |
2974 return (TRUE); | 1804 return (TRUE); |
2975 } | 1805 } |
2976 | 1806 |
2977 return (FALSE); // do not perform gauging | 1807 return (FALSE); // do not perform gauging |
2978 } | 1808 } |
2996 l1s.pw_mgr.paging_scheduled = FALSE; // reset Flag. | 1826 l1s.pw_mgr.paging_scheduled = FALSE; // reset Flag. |
2997 | 1827 |
2998 // A gauging session is needed : start gauging session with this paging bloc ! | 1828 // A gauging session is needed : start gauging session with this paging bloc ! |
2999 | 1829 |
3000 //Nina modify to save power, not forbid deep sleep, only force gauging in next paging | 1830 //Nina modify to save power, not forbid deep sleep, only force gauging in next paging |
3001 #if 0 | 1831 // FreeCalypso TCS211 reconstruction: Nina's change reverted |
1832 #if 1 | |
3002 if (l1s.pw_mgr.enough_gaug != TRUE) | 1833 if (l1s.pw_mgr.enough_gaug != TRUE) |
3003 time_to_gaug = 0; | 1834 time_to_gaug = 0; |
3004 #else | 1835 #else |
3005 if ((l1s.pw_mgr.enough_gaug != TRUE)||(l1s.force_gauging_next_paging_due_to_CCHR == 1)) | 1836 if ((l1s.pw_mgr.enough_gaug != TRUE)||(l1s.force_gauging_next_paging_due_to_CCHR == 1)) |
3006 { | 1837 { |
3205 } | 2036 } |
3206 } | 2037 } |
3207 | 2038 |
3208 //#pragma GSM_IDLE_DUPLICATE_FOR_INTERNAL_RAM_END | 2039 //#pragma GSM_IDLE_DUPLICATE_FOR_INTERNAL_RAM_END |
3209 #endif | 2040 #endif |
3210 | |
3211 | |
3212 |