FreeCalypso > hg > freecalypso-citrine
comparison L1/include/l1_tabs.h @ 3:f93dab57b032
L1/include: TCS211-based version restored
author | Mychaela Falconia <falcon@freecalypso.org> |
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date | Thu, 09 Jun 2016 00:45:00 +0000 |
parents | 75a11d740a02 |
children |
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2:7c13c26f1aa4 | 3:f93dab57b032 |
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9 /*********************************************************** | 9 /*********************************************************** |
10 * Content: | 10 * Content: |
11 * This file contains the miscelaneous ROM tables. | 11 * This file contains the miscelaneous ROM tables. |
12 ***********************************************************/ | 12 ***********************************************************/ |
13 | 13 |
14 #ifndef L1_TABS_H | 14 #ifdef L1_ASYNC_C |
15 #define L1_TABS_H | 15 /*-----------------------------------------------------------------*/ |
16 | 16 /* Idle Tasks info. (Paging position, extended Paging position...) */ |
17 #ifdef L1_ASYNC_C | 17 /*-----------------------------------------------------------------*/ |
18 /*-----------------------------------------------------------------*/ | 18 /* REM: */ |
19 /* Idle Tasks info. (Paging position, extended Paging position...) */ | 19 /* The "working area" field gives the starting position of an area */ |
20 /*-----------------------------------------------------------------*/ | 20 /* it will be used for neighbour: - FB search, */ |
21 /* REM: */ | 21 /* - SB reading, */ |
22 /* The "working area" field gives the starting position of an area */ | 22 /* The value given for each parameter set takes into account the */ |
23 /* it will be used for neighbour: - FB search, */ | 23 /* size of the "FB search" task and the CBCH task. */ |
24 /* - SB reading, */ | 24 /*-----------------------------------------------------------------*/ |
25 /* The value given for each parameter set takes into account the */ | 25 // NP or EP task size: 1 + 4 + 1 = 6. |
26 /* size of the "FB search" task and the CBCH task. */ | 26 // BCCHS task size: 1 + 4 + 1 = 6. |
27 /*-----------------------------------------------------------------*/ | 27 // FB task size: 1 + 12 + 1 = 14. --+-- FB + SB task take 15 TDMA (pipeline overlay). |
28 // NP or EP task size: 1 + 4 + 1 = 6. | 28 // SB task size: 1 + 2 + 1 = 4. --+ |
29 // BCCHS task size: 1 + 4 + 1 = 6. | 29 // CNF, SB task size: 1 + 2 + 1 = 4. |
30 // FB task size: 1 + 12 + 1 = 14. --+-- FB + SB task take 15 TDMA (pipeline overlay). | 30 // BC (Broad. Channel): 1 + 4 + 1 = 6 |
31 // SB task size: 1 + 2 + 1 = 4. --+ | 31 |
32 // CNF, SB task size: 1 + 2 + 1 = 4. | 32 const T_IDLE_TASK_INFO IDLE_INFO_NCOMB[(MAX_AG_BLKS_RES_NCOMB+1) * (MAX_PG_BLOC_INDEX_NCOMB+1)] = |
33 // BC (Broad. Channel): 1 + 4 + 1 = 6 | 33 // BS_CCCH_SDCCH_COMB = False, BCCH not combined. |
34 | 34 { |
35 const T_IDLE_TASK_INFO IDLE_INFO_NCOMB[(MAX_AG_BLKS_RES_NCOMB+1) * (MAX_PG_BLOC_INDEX_NCOMB+1)] = | 35 // BS_AG_BLKS_RES = 0. |
36 // BS_CCCH_SDCCH_COMB = False, BCCH not combined. | 36 // ------------------- |
37 { | 37 // Paging, Ext Paging |
38 // BS_AG_BLKS_RES = 0. | 38 { CCCH_0, CCCH_2 }, // Paging Block Index = 0. |
39 // ------------------- | 39 { CCCH_1, CCCH_3 }, // Paging Block Index = 1. |
40 // Paging, Ext Paging | 40 { CCCH_2, CCCH_4 }, // Paging Block Index = 2. |
41 { CCCH_0, CCCH_2 }, // Paging Block Index = 0. | 41 { CCCH_3, CCCH_5 }, // Paging Block Index = 3. |
42 { CCCH_1, CCCH_3 }, // Paging Block Index = 1. | 42 { CCCH_4, CCCH_6 }, // Paging Block Index = 4. |
43 { CCCH_2, CCCH_4 }, // Paging Block Index = 2. | 43 { CCCH_5, CCCH_7 }, // Paging Block Index = 5. |
44 { CCCH_3, CCCH_5 }, // Paging Block Index = 3. | 44 { CCCH_6, CCCH_8 }, // Paging Block Index = 6. |
45 { CCCH_4, CCCH_6 }, // Paging Block Index = 4. | 45 { CCCH_7, CCCH_0 }, // Paging Block Index = 7. |
46 { CCCH_5, CCCH_7 }, // Paging Block Index = 5. | 46 { CCCH_8, CCCH_1 }, // Paging Block Index = 8. |
47 { CCCH_6, CCCH_8 }, // Paging Block Index = 6. | 47 |
48 { CCCH_7, CCCH_0 }, // Paging Block Index = 7. | 48 // BS_AG_BLKS_RES = 1. |
49 { CCCH_8, CCCH_1 }, // Paging Block Index = 8. | 49 // ------------------- |
50 | 50 // Paging, Ext Paging |
51 // BS_AG_BLKS_RES = 1. | 51 { CCCH_1, CCCH_3 }, // Paging Block Index = 0. |
52 // ------------------- | 52 { CCCH_2, CCCH_4 }, // Paging Block Index = 1. |
53 // Paging, Ext Paging | 53 { CCCH_3, CCCH_5 }, // Paging Block Index = 2. |
54 { CCCH_1, CCCH_3 }, // Paging Block Index = 0. | 54 { CCCH_4, CCCH_6 }, // Paging Block Index = 3. |
55 { CCCH_2, CCCH_4 }, // Paging Block Index = 1. | 55 { CCCH_5, CCCH_7 }, // Paging Block Index = 4. |
56 { CCCH_3, CCCH_5 }, // Paging Block Index = 2. | 56 { CCCH_6, CCCH_8 }, // Paging Block Index = 5. |
57 { CCCH_4, CCCH_6 }, // Paging Block Index = 3. | 57 { CCCH_7, CCCH_1 }, // Paging Block Index = 6. |
58 { CCCH_5, CCCH_7 }, // Paging Block Index = 4. | 58 { CCCH_8, CCCH_2 }, // Paging Block Index = 7. |
59 { CCCH_6, CCCH_8 }, // Paging Block Index = 5. | 59 { NULL, NULL }, // Paging Block Index = 8. |
60 { CCCH_7, CCCH_1 }, // Paging Block Index = 6. | 60 |
61 { CCCH_8, CCCH_2 }, // Paging Block Index = 7. | 61 // BS_AG_BLKS_RES = 2. |
62 { NULL, NULL }, // Paging Block Index = 8. | 62 // ------------------- |
63 | 63 // Paging, Ext Paging |
64 // BS_AG_BLKS_RES = 2. | 64 { CCCH_2, CCCH_4 }, // Paging Block Index = 0. |
65 // ------------------- | 65 { CCCH_3, CCCH_5 }, // Paging Block Index = 1. |
66 // Paging, Ext Paging | 66 { CCCH_4, CCCH_6 }, // Paging Block Index = 2. |
67 { CCCH_2, CCCH_4 }, // Paging Block Index = 0. | 67 { CCCH_5, CCCH_7 }, // Paging Block Index = 3. |
68 { CCCH_3, CCCH_5 }, // Paging Block Index = 1. | 68 { CCCH_6, CCCH_8 }, // Paging Block Index = 4. |
69 { CCCH_4, CCCH_6 }, // Paging Block Index = 2. | 69 { CCCH_7, CCCH_2 }, // Paging Block Index = 5. |
70 { CCCH_5, CCCH_7 }, // Paging Block Index = 3. | 70 { CCCH_8, CCCH_3 }, // Paging Block Index = 6. |
71 { CCCH_6, CCCH_8 }, // Paging Block Index = 4. | 71 { NULL, NULL }, // Paging Block Index = 7. |
72 { CCCH_7, CCCH_2 }, // Paging Block Index = 5. | 72 { NULL, NULL }, // Paging Block Index = 8. |
73 { CCCH_8, CCCH_3 }, // Paging Block Index = 6. | 73 |
74 { NULL, NULL }, // Paging Block Index = 7. | 74 // BS_AG_BLKS_RES = 3. |
75 { NULL, NULL }, // Paging Block Index = 8. | 75 // ------------------- |
76 | 76 // Paging, Ext Paging, |
77 // BS_AG_BLKS_RES = 3. | 77 { CCCH_3, CCCH_5 }, // Paging Block Index = 0. |
78 // ------------------- | 78 { CCCH_4, CCCH_6 }, // Paging Block Index = 1. |
79 // Paging, Ext Paging, | 79 { CCCH_5, CCCH_7 }, // Paging Block Index = 2. |
80 { CCCH_3, CCCH_5 }, // Paging Block Index = 0. | 80 { CCCH_6, CCCH_8 }, // Paging Block Index = 3. |
81 { CCCH_4, CCCH_6 }, // Paging Block Index = 1. | 81 { CCCH_7, CCCH_3 }, // Paging Block Index = 4. |
82 { CCCH_5, CCCH_7 }, // Paging Block Index = 2. | 82 { CCCH_8, CCCH_4 }, // Paging Block Index = 5. |
83 { CCCH_6, CCCH_8 }, // Paging Block Index = 3. | 83 { NULL, NULL }, // Paging Block Index = 6. |
84 { CCCH_7, CCCH_3 }, // Paging Block Index = 4. | 84 { NULL, NULL }, // Paging Block Index = 7. |
85 { CCCH_8, CCCH_4 }, // Paging Block Index = 5. | 85 { NULL, NULL }, // Paging Block Index = 8. |
86 { NULL, NULL }, // Paging Block Index = 6. | 86 |
87 { NULL, NULL }, // Paging Block Index = 7. | 87 // BS_AG_BLKS_RES = 4. |
88 { NULL, NULL }, // Paging Block Index = 8. | 88 // ------------------- |
89 | 89 // Paging, Ext Paging |
90 // BS_AG_BLKS_RES = 4. | 90 { CCCH_4, CCCH_6 }, // Paging Block Index = 0. |
91 // ------------------- | 91 { CCCH_5, CCCH_7 }, // Paging Block Index = 1. |
92 // Paging, Ext Paging | 92 { CCCH_6, CCCH_8 }, // Paging Block Index = 2. |
93 { CCCH_4, CCCH_6 }, // Paging Block Index = 0. | 93 { CCCH_7, CCCH_4 }, // Paging Block Index = 3. |
94 { CCCH_5, CCCH_7 }, // Paging Block Index = 1. | 94 { CCCH_8, CCCH_5 }, // Paging Block Index = 4. |
95 { CCCH_6, CCCH_8 }, // Paging Block Index = 2. | 95 { NULL, NULL }, // Paging Block Index = 5. |
96 { CCCH_7, CCCH_4 }, // Paging Block Index = 3. | 96 { NULL, NULL }, // Paging Block Index = 6. |
97 { CCCH_8, CCCH_5 }, // Paging Block Index = 4. | 97 { NULL, NULL }, // Paging Block Index = 7. |
98 { NULL, NULL }, // Paging Block Index = 5. | 98 { NULL, NULL }, // Paging Block Index = 8. |
99 { NULL, NULL }, // Paging Block Index = 6. | 99 |
100 { NULL, NULL }, // Paging Block Index = 7. | 100 // BS_AG_BLKS_RES = 5. |
101 { NULL, NULL }, // Paging Block Index = 8. | 101 // ------------------- |
102 | 102 // Paging, Ext Paging |
103 // BS_AG_BLKS_RES = 5. | 103 { CCCH_5, CCCH_7 }, // Paging Block Index = 0. |
104 // ------------------- | 104 { CCCH_6, CCCH_8 }, // Paging Block Index = 1. |
105 // Paging, Ext Paging | 105 { CCCH_7, CCCH_5 }, // Paging Block Index = 2. |
106 { CCCH_5, CCCH_7 }, // Paging Block Index = 0. | 106 { CCCH_8, CCCH_6 }, // Paging Block Index = 3. |
107 { CCCH_6, CCCH_8 }, // Paging Block Index = 1. | 107 { NULL, NULL }, // Paging Block Index = 4. |
108 { CCCH_7, CCCH_5 }, // Paging Block Index = 2. | 108 { NULL, NULL }, // Paging Block Index = 5. |
109 { CCCH_8, CCCH_6 }, // Paging Block Index = 3. | 109 { NULL, NULL }, // Paging Block Index = 6. |
110 { NULL, NULL }, // Paging Block Index = 4. | 110 { NULL, NULL }, // Paging Block Index = 7. |
111 { NULL, NULL }, // Paging Block Index = 5. | 111 { NULL, NULL }, // Paging Block Index = 8. |
112 { NULL, NULL }, // Paging Block Index = 6. | 112 |
113 { NULL, NULL }, // Paging Block Index = 7. | 113 // BS_AG_BLKS_RES = 6. |
114 { NULL, NULL }, // Paging Block Index = 8. | 114 // ------------------- |
115 | 115 // Paging, Ext Paging, |
116 // BS_AG_BLKS_RES = 6. | 116 { CCCH_6, CCCH_8 }, // Paging Block Index = 0. |
117 // ------------------- | 117 { CCCH_7, CCCH_6 }, // Paging Block Index = 1. |
118 // Paging, Ext Paging, | 118 { CCCH_8, CCCH_7 }, // Paging Block Index = 2. |
119 { CCCH_6, CCCH_8 }, // Paging Block Index = 0. | 119 { NULL, NULL }, // Paging Block Index = 3. |
120 { CCCH_7, CCCH_6 }, // Paging Block Index = 1. | 120 { NULL, NULL }, // Paging Block Index = 4. |
121 { CCCH_8, CCCH_7 }, // Paging Block Index = 2. | 121 { NULL, NULL }, // Paging Block Index = 5. |
122 { NULL, NULL }, // Paging Block Index = 3. | 122 { NULL, NULL }, // Paging Block Index = 6. |
123 { NULL, NULL }, // Paging Block Index = 4. | 123 { NULL, NULL }, // Paging Block Index = 7. |
124 { NULL, NULL }, // Paging Block Index = 5. | 124 { NULL, NULL }, // Paging Block Index = 8. |
125 { NULL, NULL }, // Paging Block Index = 6. | 125 |
126 { NULL, NULL }, // Paging Block Index = 7. | 126 // BS_AG_BLKS_RES = 7. |
127 { NULL, NULL }, // Paging Block Index = 8. | 127 // ------------------- |
128 | 128 // Paging, Ext Paging |
129 // BS_AG_BLKS_RES = 7. | 129 { CCCH_7, CCCH_7 }, // Paging Block Index = 0. |
130 // ------------------- | 130 { CCCH_8, CCCH_8 }, // Paging Block Index = 1. |
131 // Paging, Ext Paging | 131 { NULL, NULL }, // Paging Block Index = 2. |
132 { CCCH_7, CCCH_7 }, // Paging Block Index = 0. | 132 { NULL, NULL }, // Paging Block Index = 3. |
133 { CCCH_8, CCCH_8 }, // Paging Block Index = 1. | 133 { NULL, NULL }, // Paging Block Index = 4. |
134 { NULL, NULL }, // Paging Block Index = 2. | 134 { NULL, NULL }, // Paging Block Index = 5. |
135 { NULL, NULL }, // Paging Block Index = 3. | 135 { NULL, NULL }, // Paging Block Index = 6. |
136 { NULL, NULL }, // Paging Block Index = 4. | 136 { NULL, NULL }, // Paging Block Index = 7. |
137 { NULL, NULL }, // Paging Block Index = 5. | 137 { NULL, NULL } // Paging Block Index = 8. |
138 { NULL, NULL }, // Paging Block Index = 6. | 138 }; |
139 { NULL, NULL }, // Paging Block Index = 7. | 139 |
140 { NULL, NULL } // Paging Block Index = 8. | 140 const T_IDLE_TASK_INFO IDLE_INFO_COMB[(MAX_AG_BLKS_RES_COMB+1) * (MAX_PG_BLOC_INDEX_COMB+1)] = |
141 // BS_CCCH_SDCCH_COMB = TRUE, BCCH combined. | |
142 { | |
143 // BS_AG_BLKS_RES = 0. | |
144 // ------------------- | |
145 // Paging, Ext Paging, offset, working_area | |
146 { CCCH_0, CCCH_2 }, // Paging Block Index = 0. | |
147 { CCCH_1, CCCH_0 }, // Paging Block Index = 1. | |
148 { CCCH_2, CCCH_1 }, // Paging Block Index = 2. | |
149 | |
150 // BS_AG_BLKS_RES = 1. | |
151 // ------------------- | |
152 // Paging, Ext Paging, offset, working_area | |
153 { CCCH_1, CCCH_1 }, // Paging Block Index = 0. | |
154 { CCCH_2, CCCH_2 }, // Paging Block Index = 1. | |
155 { NULL, NULL }, // Paging Block Index = 2. | |
156 | |
157 // BS_AG_BLKS_RES = 2. | |
158 // ------------------- | |
159 // Paging, Ext Paging, offset, working_area | |
160 { CCCH_2, CCCH_2 }, // Paging Block Index = 0. | |
161 { NULL, NULL }, // Paging Block Index = 1. | |
162 { NULL, NULL } // Paging Block Index = 2. | |
163 }; | |
164 | |
165 | |
166 /*-------------------------------------*/ | |
167 /* Table giving the number of Paging */ | |
168 /* blocks in a MF51. */ | |
169 /* (called "N div BS_PA_MFRMS" in */ | |
170 /* GSM05.02, Page 21). */ | |
171 /*-------------------------------------*/ | |
172 | |
173 // BS_CCCH_SDCCH_COMB = False, BCCH not combined. | |
174 const UWORD8 NBPCH_IN_MF51_NCOMB[(MAX_AG_BLKS_RES_NCOMB+1)] = | |
175 { | |
176 9, // BS_AG_BLKS_RES = 0. | |
177 8, // BS_AG_BLKS_RES = 1. | |
178 7, // BS_AG_BLKS_RES = 2. | |
179 6, // BS_AG_BLKS_RES = 3. | |
180 5, // BS_AG_BLKS_RES = 4. | |
181 4, // BS_AG_BLKS_RES = 5. | |
182 3, // BS_AG_BLKS_RES = 6. | |
183 2 // BS_AG_BLKS_RES = 7. | |
184 }; | |
185 | |
186 // BS_CCCH_SDCCH_COMB = True, BCCH combined. | |
187 const UWORD8 NBPCH_IN_MF51_COMB[(MAX_AG_BLKS_RES_COMB+1)] = | |
188 { | |
189 3, // BS_AG_BLKS_RES = 0. | |
190 2, // BS_AG_BLKS_RES = 1. | |
191 1 // BS_AG_BLKS_RES = 2. | |
192 }; | |
193 | |
194 // Initial value for Downlink Signalling failure Counter (DSC). | |
195 const UWORD8 DSC_INIT_VALUE[MAX_BS_PA_MFRMS-1] = | |
196 { | |
197 45, // BS_PA_MFRMS = 2. | |
198 30, // BS_PA_MFRMS = 3. | |
199 23, // BS_PA_MFRMS = 4. | |
200 18, // BS_PA_MFRMS = 5. | |
201 15, // BS_PA_MFRMS = 6. | |
202 13, // BS_PA_MFRMS = 7. | |
203 11, // BS_PA_MFRMS = 8. | |
204 10 // BS_PA_MFRMS = 9. | |
205 }; | |
206 | |
207 // REM: 2nd block of SDCCH is always at the same position as the first block | |
208 // but 1 mf51 later. | |
209 // REM: monitoring during SDCCH used a fixe area (FB51/SB51/SBCNF51 tasks). | |
210 // Here is given the area starting position. This position is chosen | |
211 // to allow the equations for SBCNF51 occurence as it is in the l1s | |
212 // scheduler (the area do not overlap the end of 102 multiframe | |
213 // structure). | |
214 // Table for SDCCH description, Down Link & Up link, Not combined case. | |
215 const T_SDCCH_DESC SDCCH_DESC_NCOMB[8] = | |
216 { | |
217 // "dl_D" , "dl_A" , "ul_D" , "ul_A". , "monit. area" | |
218 { 51 - 12 , 32 - 12 , 15 - 12 , 47 - 12 , 70 - 12 }, // SDCCH, D0 | |
219 { 55 - 12 , 36 - 12 , 19 - 12 , 51 - 12 , 74 - 12 }, // SDCCH, D1 | |
220 { 59 - 12 , 40 - 12 , 23 - 12 , 55 - 12 , 78 - 12 }, // SDCCH, D2 | |
221 { 12 - 12 , 44 - 12 , 27 - 12 , 59 - 12 , 82 - 12 }, // SDCCH, D3 | |
222 { 16 - 12 , 83 - 12 , 31 - 12 , 98 - 12 , 35 - 12 }, // SDCCH, D4 | |
223 { 20 - 12 , 87 - 12 , 35 - 12 , 102 - 12 , 39 - 12 }, // SDCCH, D5 | |
224 { 24 - 12 , 91 - 12 , 39 - 12 , 4 - 12 + 102 , 43 - 12 }, // SDCCH, D6 | |
225 { 28 - 12 , 95 - 12 , 43 - 12 , 8 - 12 + 102 , 47 - 12 } // SDCCH, D7 | |
226 }; | |
227 | |
228 // REM: monitoring during SDCCH used a fixe area (FB51/SB51/SBCNF51 tasks). | |
229 // Here is given the area starting position. This position is chosen | |
230 // to allow the equations for SBCNF51 occurence as it is in the l1s | |
231 // scheduler (the area do not overlap the end of 102 multiframe | |
232 // structure). | |
233 // Table for SDCCH description, Down Link & Up link, Combined case. | |
234 const T_SDCCH_DESC SDCCH_DESC_COMB[4] = | |
235 { | |
236 // "dl_D" , "dl_A" , "ul_D" , "ul_A". , "monit. area" | |
237 { 73 - 37 , 42 - 37 , 37 - 37 , 57 - 37 , 92 - 37 }, // SDCCH, D0 | |
238 { 77 - 37 , 46 - 37 , 41 - 37 , 61 - 37 , 96 - 37 }, // SDCCH, D1 | |
239 { 83 - 37 , 93 - 37 , 47 - 37 , 6 - 37 + 102 , 51 - 37 }, // SDCCH, D2 | |
240 { 87 - 37 , 97 - 37 , 51 - 37 , 10 - 37 + 102 , 55 - 37 } // SDCCH, D3 | |
241 }; | |
242 | |
243 // Table for HOPPING SEQUENCE GENERATION ALGORITHM. | |
244 const UWORD8 RNTABLE[114] = | |
245 { | |
246 48, 98, 63, 1, 36, 95, 78, 102, 94, 73, | |
247 0, 64, 25, 81, 76, 59, 124, 23, 104, 100, | |
248 101, 47, 118, 85, 18, 56, 96, 86, 54, 2, | |
249 80, 34, 127, 13, 6, 89, 57, 103, 12, 74, | |
250 55, 111, 75, 38, 109, 71, 112, 29, 11, 88, | |
251 87, 19, 3, 68, 110, 26, 33, 31, 8, 45, | |
252 82, 58, 40, 107, 32, 5, 106, 92, 62, 67, | |
253 77, 108, 122, 37, 60, 66, 121, 42, 51, 126, | |
254 117, 114, 4, 90, 43, 52, 53, 113, 120, 72, | |
255 16, 49, 7, 79, 119, 61, 22, 84, 9, 97, | |
256 91, 15, 21, 24, 46, 39, 93, 105, 65, 70, | |
257 125, 99, 17, 123 | |
258 }; | |
259 | |
260 | |
261 // Table giving the RACH slot positions when COMBINED. | |
262 // Rem: all is shifted left by 1 to map the position of the possible "contoles". | |
263 const UWORD8 COMBINED_RA_DISTRIB[51] = | |
264 { | |
265 0, 0, 0, | |
266 1, 1, | |
267 0, 0, 0, 0, 0, 0, 0, 0, | |
268 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, | |
269 0, 0, 0, 0, 0, 0, 0, 0, | |
270 1, 1, | |
271 0, 0, 0, 0, 0 | |
272 }; | |
273 | |
274 #if !L1_GPRS | |
275 const T_TASK_MFTAB TASK_ROM_MFTAB[NBR_DL_L1S_TASKS] = | |
276 { | |
277 { BLOC_HWTEST, BLOC_HWTEST_SIZE }, // HWTEST | |
278 { BLOC_ADC , BLOC_ADC_SIZE }, // ADC in CS_MODE0 | |
279 { NULL, 0 }, // DEDIC (not meaningfull) | |
280 { BLOC_RAACC, BLOC_RAACC_SIZE }, // RAACC | |
281 { NULL, 0 }, // RAHO (not meaningfull) | |
282 { NULL, 0 }, // NSYNC (not meaningfull) | |
283 { BLOC_FBNEW, BLOC_FBNEW_SIZE }, // FBNEW | |
284 { BLOC_SBCONF, BLOC_SBCONF_SIZE }, // SBCONF | |
285 { BLOC_SB2, BLOC_SB2_SIZE }, // SB2 | |
286 { BLOC_FB26, BLOC_FB26_SIZE }, // FB26 | |
287 { BLOC_SB26, BLOC_SB26_SIZE }, // SB26 | |
288 { BLOC_SBCNF26, BLOC_SBCNF26_SIZE }, // SBCNF26 | |
289 { BLOC_FB51, BLOC_FB51_SIZE }, // FB51 | |
290 { BLOC_SB51, BLOC_SB51_SIZE }, // SB51 | |
291 { BLOC_SBCNF51, BLOC_SBCNF51_SIZE }, // SBCNF51 | |
292 { BLOC_BCCHN, BLOC_BCCHN_SIZE }, // BCCHN | |
293 { BLOC_ALLC, S_RECT4_SIZE }, // ALLC | |
294 { BLOC_EBCCHS, S_RECT4_SIZE }, // EBCCHS | |
295 { BLOC_NBCCHS, S_RECT4_SIZE }, // NBCCHS | |
296 { BLOC_SMSCB, BLOC_SMSCB_SIZE }, // SMSCB | |
297 { BLOC_NP, S_RECT4_SIZE }, // NP | |
298 { BLOC_EP, S_RECT4_SIZE }, // EP | |
299 { BLOC_ADL, S_RECT4_SIZE }, // ADL | |
300 { BLOC_AUL, S_RECT4_SIZE }, // AUL | |
301 { BLOC_DDL, S_RECT4_SIZE }, // DDL | |
302 { BLOC_DUL, S_RECT4_SIZE }, // DUL | |
303 { BLOC_TCHD, BLOC_TCHT_SIZE }, // TCHD | |
304 { BLOC_TCHA, BLOC_TCHA_SIZE }, // TCHA | |
305 { BLOC_TCHTF, BLOC_TCHT_SIZE }, // TCHTF | |
306 { BLOC_TCHTH, BLOC_TCHT_SIZE }, // TCHTH | |
307 { BLOC_BCCHN_TOP,BLOC_BCCHN_TOP_SIZE}, // BCCHN_TOP | |
308 { BLOC_SYNCHRO, BLOC_SYNCHRO_SIZE } // SYNCHRO | |
309 }; | |
310 | |
311 const UWORD8 DSP_TASK_CODE[NBR_DL_L1S_TASKS] = | |
312 { | |
313 CHECKSUM_DSP_TASK,// HWTEST | |
314 0, // DEDIC (not meaningfull) | |
315 0, // ADC (not meaningfull) | |
316 RACH_DSP_TASK, // RAACC | |
317 RACH_DSP_TASK, // RAHO | |
318 0, // NSYNC (not meaningfull) | |
319 FB_DSP_TASK, // FBNEW | |
320 SB_DSP_TASK, // SBCONF | |
321 SB_DSP_TASK, // SB2 | |
322 TCH_FB_DSP_TASK, // FB26 | |
323 TCH_SB_DSP_TASK, // SB26 | |
324 TCH_SB_DSP_TASK, // SBCNF26 | |
325 FB_DSP_TASK, // FB51 | |
326 SB_DSP_TASK, // SB51 | |
327 SB_DSP_TASK, // SBCNF51 | |
328 NBN_DSP_TASK, // BCCHN | |
329 ALLC_DSP_TASK, // ALLC | |
330 NBS_DSP_TASK, // EBCCHS | |
331 NBS_DSP_TASK, // NBCCHS | |
332 DDL_DSP_TASK, // Temporary (BUG IN SIMULATOR) CB_DSP_TASK, // SMSCB | |
333 NP_DSP_TASK, // NP | |
334 EP_DSP_TASK, // EP | |
335 ADL_DSP_TASK, // ADL | |
336 AUL_DSP_TASK, // AUL | |
337 DDL_DSP_TASK, // DDL | |
338 DUL_DSP_TASK, // DUL | |
339 TCHD_DSP_TASK, // TCHD | |
340 TCHA_DSP_TASK, // TCHA | |
341 TCHT_DSP_TASK, // TCHTF | |
342 TCHT_DSP_TASK, // TCHTH | |
343 NBN_DSP_TASK, // BCCHN_TOP == BCCHN | |
344 0, // SYNCHRO (not meaningfull) | |
345 }; | |
346 #else | |
347 const T_TASK_MFTAB TASK_ROM_MFTAB[NBR_DL_L1S_TASKS] = | |
348 { | |
349 { BLOC_HWTEST, BLOC_HWTEST_SIZE }, // HWTEST | |
350 { BLOC_ADC, BLOC_ADC_SIZE }, // ADC in CS_MODE0 | |
351 { NULL, 0 }, // DEDIC (not meaningfull) | |
352 { BLOC_RAACC, BLOC_RAACC_SIZE }, // RAACC | |
353 { NULL, 0 }, // RAHO (not meaningfull) | |
354 { NULL, 0 }, // NSYNC (not meaningfull) | |
355 { BLOC_POLL , BLOC_POLL_SIZE }, // POLL | |
356 { BLOC_PRACH, BLOC_PRACH_SIZE }, // PRACH | |
357 { BLOC_ITMEAS, BLOC_ITMEAS_SIZE }, // ITMEAS | |
358 { BLOC_FBNEW, BLOC_FBNEW_SIZE }, // FBNEW | |
359 { BLOC_SBCONF, BLOC_SBCONF_SIZE }, // SBCONF | |
360 { BLOC_SB2, BLOC_SB2_SIZE }, // SB2 | |
361 { BLOC_PTCCH, BLOC_PTCCH_SIZE }, // PTCCH | |
362 { BLOC_FB26, BLOC_FB26_SIZE }, // FB26 | |
363 { BLOC_SB26, BLOC_SB26_SIZE }, // SB26 | |
364 { BLOC_SBCNF26, BLOC_SBCNF26_SIZE }, // SBCNF26 | |
365 { BLOC_FB51, BLOC_FB51_SIZE }, // FB51 | |
366 { BLOC_SB51, BLOC_SB51_SIZE }, // SB51 | |
367 { BLOC_SBCNF51, BLOC_SBCNF51_SIZE }, // SBCNF51 | |
368 { BLOC_PDTCH, BLOC_PDTCH_SIZE }, // PDTCH | |
369 { BLOC_BCCHN, BLOC_BCCHN_SIZE }, // BCCHN | |
370 { BLOC_ALLC, S_RECT4_SIZE }, // ALLC | |
371 { BLOC_EBCCHS, S_RECT4_SIZE }, // EBCCHS | |
372 { BLOC_NBCCHS, S_RECT4_SIZE }, // NBCCHS | |
373 { BLOC_ADL, S_RECT4_SIZE }, // ADL | |
374 { BLOC_AUL, S_RECT4_SIZE }, // AUL | |
375 { BLOC_DDL, S_RECT4_SIZE }, // DDL | |
376 { BLOC_DUL, S_RECT4_SIZE }, // DUL | |
377 { BLOC_TCHD, BLOC_TCHT_SIZE }, // TCHD | |
378 { BLOC_TCHA, BLOC_TCHA_SIZE }, // TCHA | |
379 { BLOC_TCHTF, BLOC_TCHT_SIZE }, // TCHTF | |
380 { BLOC_TCHTH, BLOC_TCHT_SIZE }, // TCHTH | |
381 { BLOC_PALLC, BLOC_PCCCH_SIZE }, // PALLC | |
382 { BLOC_SMSCB, BLOC_SMSCB_SIZE }, // SMSCB | |
383 { BLOC_PBCCHS, BLOC_PBCCHS_SIZE }, // PBCCHS | |
384 { BLOC_PNP, BLOC_PCCCH_SIZE }, // PNP | |
385 { BLOC_PEP, BLOC_PCCCH_SIZE }, // PEP | |
386 { BLOC_SINGLE, BLOC_SINGLE_SIZE }, // SINGLE | |
387 { BLOC_PBCCHN_TRAN, BLOC_PBCCHN_TRAN_SIZE }, // PBCCHN_TRAN | |
388 { BLOC_PBCCHN_IDLE, BLOC_PBCCHN_IDLE_SIZE }, // PBCCHN_IDLE | |
389 { BLOC_BCCHN_TRAN, BLOC_BCCHN_TRAN_SIZE }, // BCCHN_TRAN | |
390 { BLOC_NP, S_RECT4_SIZE }, // NP | |
391 { BLOC_EP, S_RECT4_SIZE }, // EP | |
392 { BLOC_BCCHN_TOP, BLOC_BCCHN_TOP_SIZE}, // BCCHN_TOP | |
393 { BLOC_SYNCHRO, BLOC_SYNCHRO_SIZE } // SYNCHRO | |
394 }; | |
395 | |
396 const UWORD8 DSP_TASK_CODE[NBR_DL_L1S_TASKS] = | |
397 { | |
398 CHECKSUM_DSP_TASK,// HWTEST | |
399 0, // ADC (not meaningfull) | |
400 0, // DEDIC (not meaningfull) | |
401 RACH_DSP_TASK, // RAACC | |
402 RACH_DSP_TASK, // RAHO | |
403 0, // NSYNC (not meaningfull) | |
404 0, // POLL (not meaningfull) | |
405 0, // PRACH (not meaningfull) | |
406 0, // ITMEAS | |
407 FB_DSP_TASK, // FBNEW | |
408 SB_DSP_TASK, // SBCONF | |
409 SB_DSP_TASK, // SB2 | |
410 PTCCHU_DSP_TASK, // PTCCH | |
411 TCH_FB_DSP_TASK, // FB26 | |
412 TCH_SB_DSP_TASK, // SB26 | |
413 TCH_SB_DSP_TASK, // SBCNF26 | |
414 FB_DSP_TASK, // FB51 | |
415 SB_DSP_TASK, // SB51 | |
416 SB_DSP_TASK, // SBCNF51 | |
417 0, // PDTCH (not meaningfull) | |
418 NBN_DSP_TASK, // BCCHN | |
419 ALLC_DSP_TASK, // ALLC | |
420 NBS_DSP_TASK, // EBCCHS | |
421 NBS_DSP_TASK, // NBCCHS | |
422 ADL_DSP_TASK, // ADL | |
423 AUL_DSP_TASK, // AUL | |
424 DDL_DSP_TASK, // DDL | |
425 DUL_DSP_TASK, // DUL | |
426 TCHD_DSP_TASK, // TCHD | |
427 TCHA_DSP_TASK, // TCHA | |
428 TCHT_DSP_TASK, // TCHTF | |
429 TCHT_DSP_TASK, // TCHTH | |
430 0, // PALLC (not meaningfull) | |
431 DDL_DSP_TASK, // Temporary (BUG IN SIMULATOR) CB_DSP_TASK, // SMSCB | |
432 DDL_DSP_TASK, // PBCCHS (In order to allow PBCCHS running in CS or Idle mode, we have to specify a valid DSP task in order to request a PBCCHS with the GSM scheduler) | |
433 0, // PNP (not meaningfull) | |
434 0, // PEP (not meaningfull) | |
435 0, // SINGLE (not meaningfull) | |
436 0, // PBCCHN_TRAN (not meaningfull) | |
437 DDL_DSP_TASK, // PBCCHN_IDLE (only for GSM scheduler the task used is the same as SMSCB task) | |
438 NBN_DSP_TASK, // BCCHN_TRAN == BCCHN | |
439 NP_DSP_TASK, // NP | |
440 EP_DSP_TASK, // EP | |
441 NBN_DSP_TASK, // BCCHN_TOP == BCCHN | |
442 0 // SYNCHRO (not meaningfull) | |
443 }; | |
444 | |
445 #endif | |
446 | |
447 const UWORD8 REPORTING_PERIOD[] = | |
448 { | |
449 255, // INVALID_CHANNEL -> invalid reporting period | |
450 104, // TCH_F | |
451 104, // TCH_H | |
452 102, // SDCCH_4 | |
453 102 // SDCCH_8 | |
454 }; | |
455 | |
456 const UWORD8 TOA_PERIOD_LEN[] = | |
457 { | |
458 0, // CS_MODE0 not used for histogram filling | |
459 12, // CS_MODE histogram length | |
460 12, // I_MODE histogram length | |
461 12, // CON_EST_MODE1 histogram length | |
462 144, // CON_EST_MODE2 histogram length | |
463 36, // DEDIC_MODE (Full rate) histogram length | |
464 42 // DEDIC_MODE (Half rate) histogram length | |
465 #if L1_GPRS | |
466 ,16 // PACKET TRANSFER MODE histogram length | |
467 #endif | |
468 }; | |
469 | |
470 // #if (STD == GSM) | |
471 const UWORD8 MIN_TXPWR_GSM[] = | |
472 { | |
473 0, // unused. | |
474 0, // Power class = 1, unused for GSM900 | |
475 2, // Power class = 2. | |
476 3, // Power class = 3. | |
477 5, // Power class = 4. | |
478 7 // Power class = 5. | |
141 }; | 479 }; |
142 | 480 // #elif (STD == PCS1900) |
143 const T_IDLE_TASK_INFO IDLE_INFO_COMB[(MAX_AG_BLKS_RES_COMB+1) * (MAX_PG_BLOC_INDEX_COMB+1)] = | 481 const UWORD8 MIN_TXPWR_PCS[] = |
144 // BS_CCCH_SDCCH_COMB = TRUE, BCCH combined. | 482 { |
145 { | 483 0, // unused. |
146 // BS_AG_BLKS_RES = 0. | 484 0, // Power class = 1. |
147 // ------------------- | 485 3, // Power class = 2. |
148 // Paging, Ext Paging, offset, working_area | 486 30 // Power class = 3. |
149 { CCCH_0, CCCH_2 }, // Paging Block Index = 0. | |
150 { CCCH_1, CCCH_0 }, // Paging Block Index = 1. | |
151 { CCCH_2, CCCH_1 }, // Paging Block Index = 2. | |
152 | |
153 // BS_AG_BLKS_RES = 1. | |
154 // ------------------- | |
155 // Paging, Ext Paging, offset, working_area | |
156 { CCCH_1, CCCH_1 }, // Paging Block Index = 0. | |
157 { CCCH_2, CCCH_2 }, // Paging Block Index = 1. | |
158 { NULL, NULL }, // Paging Block Index = 2. | |
159 | |
160 // BS_AG_BLKS_RES = 2. | |
161 // ------------------- | |
162 // Paging, Ext Paging, offset, working_area | |
163 { CCCH_2, CCCH_2 }, // Paging Block Index = 0. | |
164 { NULL, NULL }, // Paging Block Index = 1. | |
165 { NULL, NULL } // Paging Block Index = 2. | |
166 }; | 487 }; |
167 | 488 // #elif (STD == DCS1800) |
168 | 489 const UWORD8 MIN_TXPWR_DCS[] = |
169 /*-------------------------------------*/ | |
170 /* Table giving the number of Paging */ | |
171 /* blocks in a MF51. */ | |
172 /* (called "N div BS_PA_MFRMS" in */ | |
173 /* GSM05.02, Page 21). */ | |
174 /*-------------------------------------*/ | |
175 | |
176 // BS_CCCH_SDCCH_COMB = False, BCCH not combined. | |
177 const UWORD8 NBPCH_IN_MF51_NCOMB[(MAX_AG_BLKS_RES_NCOMB+1)] = | |
178 { | 490 { |
179 9, // BS_AG_BLKS_RES = 0. | 491 0, // unused. |
180 8, // BS_AG_BLKS_RES = 1. | 492 0, // Power class = 1. |
181 7, // BS_AG_BLKS_RES = 2. | 493 3, // Power class = 2. |
182 6, // BS_AG_BLKS_RES = 3. | 494 29 // Power class = 3. |
183 5, // BS_AG_BLKS_RES = 4. | 495 }; |
184 4, // BS_AG_BLKS_RES = 5. | 496 |
185 3, // BS_AG_BLKS_RES = 6. | 497 const UWORD8 MIN_TXPWR_GSM850[] = |
186 2 // BS_AG_BLKS_RES = 7. | |
187 }; | |
188 | |
189 // BS_CCCH_SDCCH_COMB = True, BCCH combined. | |
190 const UWORD8 NBPCH_IN_MF51_COMB[(MAX_AG_BLKS_RES_COMB+1)] = | |
191 { | 498 { |
192 3, // BS_AG_BLKS_RES = 0. | 499 0, // unused. |
193 2, // BS_AG_BLKS_RES = 1. | 500 0, // Power class = 1, unused for GSM900 |
194 1 // BS_AG_BLKS_RES = 2. | 501 2, // Power class = 2. |
195 }; | 502 3, // Power class = 3. |
196 | 503 5, // Power class = 4. |
197 // Initial value for Downlink Signalling failure Counter (DSC). | 504 7 // Power class = 5. |
198 const UWORD8 DSC_INIT_VALUE[MAX_BS_PA_MFRMS-1] = | |
199 { | |
200 45, // BS_PA_MFRMS = 2. | |
201 30, // BS_PA_MFRMS = 3. | |
202 23, // BS_PA_MFRMS = 4. | |
203 18, // BS_PA_MFRMS = 5. | |
204 15, // BS_PA_MFRMS = 6. | |
205 13, // BS_PA_MFRMS = 7. | |
206 11, // BS_PA_MFRMS = 8. | |
207 10 // BS_PA_MFRMS = 9. | |
208 }; | 505 }; |
209 | 506 |
210 // REM: 2nd block of SDCCH is always at the same position as the first block | 507 // #elif (STD == DUAL) |
211 // but 1 mf51 later. | 508 // const UWORD8 MIN_TXPWR_GSM[] = |
212 // REM: monitoring during SDCCH used a fixe area (FB51/SB51/SBCNF51 tasks). | 509 // { |
213 // Here is given the area starting position. This position is chosen | 510 // 0, // unused. |
214 // to allow the equations for SBCNF51 occurence as it is in the l1s | 511 // 0, // Power class = 1, unused for GSM900 |
215 // scheduler (the area do not overlap the end of 102 multiframe | 512 // 2, // Power class = 2. |
216 // structure). | 513 // 3, // Power class = 3. |
217 // Table for SDCCH description, Down Link & Up link, Not combined case. | 514 // 5, // Power class = 4. |
218 const T_SDCCH_DESC SDCCH_DESC_NCOMB[8] = | 515 // 7 // Power class = 5. |
219 { | 516 // }; |
220 // "dl_D" , "dl_A" , "ul_D" , "ul_A". , "monit. area" | 517 // const UWORD8 MIN_TXPWR_DCS[] = |
221 { 51 - 12 , 32 - 12 , 15 - 12 , 47 - 12 , 70 - 12 }, // SDCCH, D0 | 518 // { |
222 { 55 - 12 , 36 - 12 , 19 - 12 , 51 - 12 , 74 - 12 }, // SDCCH, D1 | 519 // 0, // unused. |
223 { 59 - 12 , 40 - 12 , 23 - 12 , 55 - 12 , 78 - 12 }, // SDCCH, D2 | 520 // 0, // Power class = 1. |
224 { 12 - 12 , 44 - 12 , 27 - 12 , 59 - 12 , 82 - 12 }, // SDCCH, D3 | 521 // 3, // Power class = 2. |
225 { 16 - 12 , 83 - 12 , 31 - 12 , 98 - 12 , 35 - 12 }, // SDCCH, D4 | 522 // 29 // Power class = 3. |
226 { 20 - 12 , 87 - 12 , 35 - 12 , 102 - 12 , 39 - 12 }, // SDCCH, D5 | 523 // }; |
227 { 24 - 12 , 91 - 12 , 39 - 12 , 4 - 12 + 102 , 43 - 12 }, // SDCCH, D6 | 524 // #endif |
228 { 28 - 12 , 95 - 12 , 43 - 12 , 8 - 12 + 102 , 47 - 12 } // SDCCH, D7 | 525 |
229 }; | 526 const UWORD8 GAUG_VS_PAGING_RATE[] = |
230 | 527 { |
231 // REM: monitoring during SDCCH used a fixe area (FB51/SB51/SBCNF51 tasks). | 528 4, // bs_pa_mfrms = 2, 1 gauging every 4 Paging blocs |
232 // Here is given the area starting position. This position is chosen | 529 3, // bs_pa_mfrms = 3, 1 gauging every 3 Paging blocs |
233 // to allow the equations for SBCNF51 occurence as it is in the l1s | 530 2, // bs_pa_mfrms = 4, 1 gauging every 2 Paging blocs |
234 // scheduler (the area do not overlap the end of 102 multiframe | 531 1, // bs_pa_mfrms = 5, 1 gauging every 1 Paging bloc |
235 // structure). | 532 1, // bs_pa_mfrms = 6, 1 gauging every 1 Paging bloc |
236 // Table for SDCCH description, Down Link & Up link, Combined case. | 533 1, // bs_pa_mfrms = 7, 1 gauging every 1 Paging bloc |
237 const T_SDCCH_DESC SDCCH_DESC_COMB[4] = | 534 1, // bs_pa_mfrms = 8, 1 gauging every 1 Paging bloc |
238 { | 535 1 // bs_pa_mfrms = 9, 1 gauging every 1 Paging bloc |
239 // "dl_D" , "dl_A" , "ul_D" , "ul_A". , "monit. area" | 536 }; |
240 { 73 - 37 , 42 - 37 , 37 - 37 , 57 - 37 , 92 - 37 }, // SDCCH, D0 | 537 |
241 { 77 - 37 , 46 - 37 , 41 - 37 , 61 - 37 , 96 - 37 }, // SDCCH, D1 | 538 #else |
242 { 83 - 37 , 93 - 37 , 47 - 37 , 6 - 37 + 102 , 51 - 37 }, // SDCCH, D2 | 539 extern T_IDLE_TASK_INFO IDLE_INFO_COMB[(MAX_AG_BLKS_RES_COMB+1) * (MAX_PG_BLOC_INDEX_COMB+1)]; |
243 { 87 - 37 , 97 - 37 , 51 - 37 , 10 - 37 + 102 , 55 - 37 } // SDCCH, D3 | 540 extern T_IDLE_TASK_INFO IDLE_INFO_NCOMB[(MAX_AG_BLKS_RES_NCOMB+1) * (MAX_PG_BLOC_INDEX_NCOMB+1)]; |
244 }; | 541 extern UWORD8 NBPCH_IN_MF51_NCOMB[(MAX_AG_BLKS_RES_NCOMB+1)]; |
245 | 542 extern UWORD8 NBPCH_IN_MF51_COMB[(MAX_AG_BLKS_RES_COMB+1)]; |
246 // Table for HOPPING SEQUENCE GENERATION ALGORITHM. | 543 extern UWORD8 DSC_INIT_VALUE[MAX_BS_PA_MFRMS-2]; |
247 const UWORD8 RNTABLE[114] = | 544 extern T_SDCCH_DESC SDCCH_DESC_NCOMB[]; |
248 { | 545 extern T_SDCCH_DESC SDCCH_DESC_COMB[]; |
249 48, 98, 63, 1, 36, 95, 78, 102, 94, 73, | 546 extern UWORD8 RNTABLE[114]; |
250 0, 64, 25, 81, 76, 59, 124, 23, 104, 100, | 547 extern UWORD8 COMBINED_RA_DISTRIB[51]; |
251 101, 47, 118, 85, 18, 56, 96, 86, 54, 2, | 548 extern T_TASK_MFTAB TASK_ROM_MFTAB[NBR_DL_L1S_TASKS]; |
252 80, 34, 127, 13, 6, 89, 57, 103, 12, 74, | 549 extern UWORD8 DSP_TASK_CODE[NBR_DL_L1S_TASKS]; |
253 55, 111, 75, 38, 109, 71, 112, 29, 11, 88, | 550 extern UWORD8 REPORTING_PERIOD[]; |
254 87, 19, 3, 68, 110, 26, 33, 31, 8, 45, | 551 extern UWORD8 TOA_PERIOD_LEN[]; |
255 82, 58, 40, 107, 32, 5, 106, 92, 62, 67, | 552 extern UWORD8 MIN_TXPWR_GSM[]; |
256 77, 108, 122, 37, 60, 66, 121, 42, 51, 126, | 553 extern UWORD8 MIN_TXPWR_DCS[]; |
257 117, 114, 4, 90, 43, 52, 53, 113, 120, 72, | 554 extern UWORD8 MIN_TXPWR_PCS[]; |
258 16, 49, 7, 79, 119, 61, 22, 84, 9, 97, | 555 extern UWORD8 MIN_TXPWR_GSM850[]; |
259 91, 15, 21, 24, 46, 39, 93, 105, 65, 70, | 556 extern UWORD8 GAUG_VS_PAGING_RATE[]; |
260 125, 99, 17, 123 | |
261 }; | |
262 | |
263 | |
264 // Table giving the RACH slot positions when COMBINED. | |
265 // Rem: all is shifted left by 1 to map the position of the possible "contoles". | |
266 const UWORD8 COMBINED_RA_DISTRIB[51] = | |
267 { | |
268 0, 0, 0, | |
269 1, 1, | |
270 0, 0, 0, 0, 0, 0, 0, 0, | |
271 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, | |
272 0, 0, 0, 0, 0, 0, 0, 0, | |
273 1, 1, | |
274 0, 0, 0, 0, 0 | |
275 }; | |
276 | |
277 #if !L1_GPRS | |
278 const T_TASK_MFTAB TASK_ROM_MFTAB[NBR_DL_L1S_TASKS] = | |
279 { | |
280 { BLOC_HWTEST, BLOC_HWTEST_SIZE }, // HWTEST | |
281 { BLOC_ADC , BLOC_ADC_SIZE }, // ADC in CS_MODE0 | |
282 { NULL, 0 }, // DEDIC (not meaningfull) | |
283 { BLOC_RAACC, BLOC_RAACC_SIZE }, // RAACC | |
284 { NULL, 0 }, // RAHO (not meaningfull) | |
285 { NULL, 0 }, // NSYNC (not meaningfull) | |
286 { BLOC_FBNEW, BLOC_FBNEW_SIZE }, // FBNEW | |
287 { BLOC_SBCONF, BLOC_SBCONF_SIZE }, // SBCONF | |
288 { BLOC_SB2, BLOC_SB2_SIZE }, // SB2 | |
289 { BLOC_FB26, BLOC_FB26_SIZE }, // FB26 | |
290 { BLOC_SB26, BLOC_SB26_SIZE }, // SB26 | |
291 { BLOC_SBCNF26, BLOC_SBCNF26_SIZE }, // SBCNF26 | |
292 { BLOC_FB51, BLOC_FB51_SIZE }, // FB51 | |
293 { BLOC_SB51, BLOC_SB51_SIZE }, // SB51 | |
294 { BLOC_SBCNF51, BLOC_SBCNF51_SIZE }, // SBCNF51 | |
295 { BLOC_BCCHN, BLOC_BCCHN_SIZE }, // BCCHN | |
296 { BLOC_ALLC, S_RECT4_SIZE }, // ALLC | |
297 { BLOC_EBCCHS, S_RECT4_SIZE }, // EBCCHS | |
298 { BLOC_NBCCHS, S_RECT4_SIZE }, // NBCCHS | |
299 { BLOC_SMSCB, BLOC_SMSCB_SIZE }, // SMSCB | |
300 { BLOC_NP, S_RECT4_SIZE }, // NP | |
301 { BLOC_EP, S_RECT4_SIZE }, // EP | |
302 { BLOC_ADL, S_RECT4_SIZE }, // ADL | |
303 { BLOC_AUL, S_RECT4_SIZE }, // AUL | |
304 { BLOC_DDL, S_RECT4_SIZE }, // DDL | |
305 { BLOC_DUL, S_RECT4_SIZE }, // DUL | |
306 { BLOC_TCHD, BLOC_TCHT_SIZE }, // TCHD | |
307 { BLOC_TCHA, BLOC_TCHA_SIZE }, // TCHA | |
308 { BLOC_TCHTF, BLOC_TCHT_SIZE }, // TCHTF | |
309 { BLOC_TCHTH, BLOC_TCHT_SIZE }, // TCHTH | |
310 { BLOC_BCCHN_TOP,BLOC_BCCHN_TOP_SIZE}, // BCCHN_TOP | |
311 #if ((REL99 == 1) && (FF_BHO == 1)) | |
312 { BLOC_FBSB, BLOC_FBSB_SIZE }, // FBSB | |
313 #endif | 557 #endif |
314 { BLOC_SYNCHRO, BLOC_SYNCHRO_SIZE } // SYNCHRO | |
315 }; | |
316 | |
317 const UWORD8 DSP_TASK_CODE[NBR_DL_L1S_TASKS] = | |
318 { | |
319 CHECKSUM_DSP_TASK,// HWTEST | |
320 0, // DEDIC (not meaningfull) | |
321 0, // ADC (not meaningfull) | |
322 RACH_DSP_TASK, // RAACC | |
323 RACH_DSP_TASK, // RAHO | |
324 0, // NSYNC (not meaningfull) | |
325 FB_DSP_TASK, // FBNEW | |
326 SB_DSP_TASK, // SBCONF | |
327 SB_DSP_TASK, // SB2 | |
328 TCH_FB_DSP_TASK, // FB26 | |
329 TCH_SB_DSP_TASK, // SB26 | |
330 TCH_SB_DSP_TASK, // SBCNF26 | |
331 FB_DSP_TASK, // FB51 | |
332 SB_DSP_TASK, // SB51 | |
333 SB_DSP_TASK, // SBCNF51 | |
334 NBN_DSP_TASK, // BCCHN | |
335 ALLC_DSP_TASK, // ALLC | |
336 NBS_DSP_TASK, // EBCCHS | |
337 NBS_DSP_TASK, // NBCCHS | |
338 DDL_DSP_TASK, // Temporary (BUG IN SIMULATOR) CB_DSP_TASK, // SMSCB | |
339 NP_DSP_TASK, // NP | |
340 EP_DSP_TASK, // EP | |
341 ADL_DSP_TASK, // ADL | |
342 AUL_DSP_TASK, // AUL | |
343 DDL_DSP_TASK, // DDL | |
344 DUL_DSP_TASK, // DUL | |
345 TCHD_DSP_TASK, // TCHD | |
346 TCHA_DSP_TASK, // TCHA | |
347 TCHT_DSP_TASK, // TCHTF | |
348 TCHT_DSP_TASK, // TCHTH | |
349 NBN_DSP_TASK, // BCCHN_TOP == BCCHN | |
350 #if ((REL99 == 1) && (FF_BHO == 1)) | |
351 FBSB_DSP_TASK, // FBSB | |
352 #endif | |
353 0, // SYNCHRO (not meaningfull) | |
354 }; | |
355 #else | |
356 const T_TASK_MFTAB TASK_ROM_MFTAB[NBR_DL_L1S_TASKS] = | |
357 { | |
358 { BLOC_HWTEST, BLOC_HWTEST_SIZE }, // HWTEST | |
359 { BLOC_ADC, BLOC_ADC_SIZE }, // ADC in CS_MODE0 | |
360 { NULL, 0 }, // DEDIC (not meaningfull) | |
361 { BLOC_RAACC, BLOC_RAACC_SIZE }, // RAACC | |
362 { NULL, 0 }, // RAHO (not meaningfull) | |
363 { NULL, 0 }, // NSYNC (not meaningfull) | |
364 { BLOC_POLL , BLOC_POLL_SIZE }, // POLL | |
365 { BLOC_PRACH, BLOC_PRACH_SIZE }, // PRACH | |
366 { BLOC_ITMEAS, BLOC_ITMEAS_SIZE }, // ITMEAS | |
367 { BLOC_FBNEW, BLOC_FBNEW_SIZE }, // FBNEW | |
368 { BLOC_SBCONF, BLOC_SBCONF_SIZE }, // SBCONF | |
369 { BLOC_SB2, BLOC_SB2_SIZE }, // SB2 | |
370 { BLOC_PTCCH, BLOC_PTCCH_SIZE }, // PTCCH | |
371 { BLOC_FB26, BLOC_FB26_SIZE }, // FB26 | |
372 { BLOC_SB26, BLOC_SB26_SIZE }, // SB26 | |
373 { BLOC_SBCNF26, BLOC_SBCNF26_SIZE }, // SBCNF26 | |
374 { BLOC_FB51, BLOC_FB51_SIZE }, // FB51 | |
375 { BLOC_SB51, BLOC_SB51_SIZE }, // SB51 | |
376 { BLOC_SBCNF51, BLOC_SBCNF51_SIZE }, // SBCNF51 | |
377 { BLOC_PDTCH, BLOC_PDTCH_SIZE }, // PDTCH | |
378 { BLOC_BCCHN, BLOC_BCCHN_SIZE }, // BCCHN | |
379 { BLOC_ALLC, S_RECT4_SIZE }, // ALLC | |
380 { BLOC_EBCCHS, S_RECT4_SIZE }, // EBCCHS | |
381 { BLOC_NBCCHS, S_RECT4_SIZE }, // NBCCHS | |
382 { BLOC_ADL, S_RECT4_SIZE }, // ADL | |
383 { BLOC_AUL, S_RECT4_SIZE }, // AUL | |
384 { BLOC_DDL, S_RECT4_SIZE }, // DDL | |
385 { BLOC_DUL, S_RECT4_SIZE }, // DUL | |
386 { BLOC_TCHD, BLOC_TCHT_SIZE }, // TCHD | |
387 { BLOC_TCHA, BLOC_TCHA_SIZE }, // TCHA | |
388 { BLOC_TCHTF, BLOC_TCHT_SIZE }, // TCHTF | |
389 { BLOC_TCHTH, BLOC_TCHT_SIZE }, // TCHTH | |
390 { BLOC_PALLC, BLOC_PCCCH_SIZE }, // PALLC | |
391 { BLOC_SMSCB, BLOC_SMSCB_SIZE }, // SMSCB | |
392 { BLOC_PBCCHS, BLOC_PBCCHS_SIZE }, // PBCCHS | |
393 { BLOC_PNP, BLOC_PCCCH_SIZE }, // PNP | |
394 { BLOC_PEP, BLOC_PCCCH_SIZE }, // PEP | |
395 { BLOC_SINGLE, BLOC_SINGLE_SIZE }, // SINGLE | |
396 { BLOC_PBCCHN_TRAN, BLOC_PBCCHN_TRAN_SIZE }, // PBCCHN_TRAN | |
397 { BLOC_PBCCHN_IDLE, BLOC_PBCCHN_IDLE_SIZE }, // PBCCHN_IDLE | |
398 { BLOC_BCCHN_TRAN, BLOC_BCCHN_TRAN_SIZE }, // BCCHN_TRAN | |
399 { BLOC_NP, S_RECT4_SIZE }, // NP | |
400 { BLOC_EP, S_RECT4_SIZE }, // EP | |
401 { BLOC_BCCHN_TOP, BLOC_BCCHN_TOP_SIZE}, // BCCHN_TOP | |
402 #if ((REL99 == 1) && (FF_BHO == 1)) | |
403 { BLOC_FBSB, BLOC_FBSB_SIZE }, // FBSB | |
404 #endif | |
405 { BLOC_SYNCHRO, BLOC_SYNCHRO_SIZE } // SYNCHRO | |
406 }; | |
407 | |
408 const UWORD8 DSP_TASK_CODE[NBR_DL_L1S_TASKS] = | |
409 { | |
410 CHECKSUM_DSP_TASK,// HWTEST | |
411 0, // ADC (not meaningfull) | |
412 0, // DEDIC (not meaningfull) | |
413 RACH_DSP_TASK, // RAACC | |
414 RACH_DSP_TASK, // RAHO | |
415 0, // NSYNC (not meaningfull) | |
416 0, // POLL (not meaningfull) | |
417 0, // PRACH (not meaningfull) | |
418 0, // ITMEAS | |
419 FB_DSP_TASK, // FBNEW | |
420 SB_DSP_TASK, // SBCONF | |
421 SB_DSP_TASK, // SB2 | |
422 PTCCHU_DSP_TASK, // PTCCH | |
423 TCH_FB_DSP_TASK, // FB26 | |
424 TCH_SB_DSP_TASK, // SB26 | |
425 TCH_SB_DSP_TASK, // SBCNF26 | |
426 FB_DSP_TASK, // FB51 | |
427 SB_DSP_TASK, // SB51 | |
428 SB_DSP_TASK, // SBCNF51 | |
429 0, // PDTCH (not meaningfull) | |
430 NBN_DSP_TASK, // BCCHN | |
431 ALLC_DSP_TASK, // ALLC | |
432 NBS_DSP_TASK, // EBCCHS | |
433 NBS_DSP_TASK, // NBCCHS | |
434 ADL_DSP_TASK, // ADL | |
435 AUL_DSP_TASK, // AUL | |
436 DDL_DSP_TASK, // DDL | |
437 DUL_DSP_TASK, // DUL | |
438 TCHD_DSP_TASK, // TCHD | |
439 TCHA_DSP_TASK, // TCHA | |
440 TCHT_DSP_TASK, // TCHTF | |
441 TCHT_DSP_TASK, // TCHTH | |
442 0, // PALLC (not meaningfull) | |
443 DDL_DSP_TASK, // Temporary (BUG IN SIMULATOR) CB_DSP_TASK, // SMSCB | |
444 DDL_DSP_TASK, // PBCCHS (In order to allow PBCCHS running in CS or Idle mode, we have to specify a valid DSP task in order to request a PBCCHS with the GSM scheduler) | |
445 0, // PNP (not meaningfull) | |
446 0, // PEP (not meaningfull) | |
447 0, // SINGLE (not meaningfull) | |
448 0, // PBCCHN_TRAN (not meaningfull) | |
449 DDL_DSP_TASK, // PBCCHN_IDLE (only for GSM scheduler the task used is the same as SMSCB task) | |
450 NBN_DSP_TASK, // BCCHN_TRAN == BCCHN | |
451 NP_DSP_TASK, // NP | |
452 EP_DSP_TASK, // EP | |
453 NBN_DSP_TASK, // BCCHN_TOP == BCCHN | |
454 #if ((REL99 == 1) && (FF_BHO == 1)) | |
455 FBSB_DSP_TASK, // FBSB | |
456 #endif | |
457 0 // SYNCHRO (not meaningfull) | |
458 }; | |
459 | |
460 #endif | |
461 | |
462 const UWORD8 REPORTING_PERIOD[] = | |
463 { | |
464 255, // INVALID_CHANNEL -> invalid reporting period | |
465 104, // TCH_F | |
466 104, // TCH_H | |
467 102, // SDCCH_4 | |
468 102 // SDCCH_8 | |
469 }; | |
470 | |
471 const UWORD8 TOA_PERIOD_LEN[] = | |
472 { | |
473 0, // CS_MODE0 not used for histogram filling | |
474 12, // CS_MODE histogram length | |
475 12, // I_MODE histogram length | |
476 12, // CON_EST_MODE1 histogram length | |
477 144, // CON_EST_MODE2 histogram length | |
478 36, // DEDIC_MODE (Full rate) histogram length | |
479 42, // DEDIC_MODE (Half rate) histogram length | |
480 #if L1_GPRS | |
481 16, // PACKET TRANSFER MODE histogram length | |
482 #endif | |
483 }; | |
484 | |
485 // #if (STD == GSM) | |
486 const UWORD8 MIN_TXPWR_GSM[] = | |
487 { | |
488 0, // unused. | |
489 0, // Power class = 1, unused for GSM900 | |
490 2, // Power class = 2. | |
491 3, // Power class = 3. | |
492 5, // Power class = 4. | |
493 7 // Power class = 5. | |
494 }; | |
495 // #elif (STD == PCS1900) | |
496 const UWORD8 MIN_TXPWR_PCS[] = | |
497 { | |
498 0, // unused. | |
499 0, // Power class = 1. | |
500 3, // Power class = 2. | |
501 30 // Power class = 3. | |
502 }; | |
503 // #elif (STD == DCS1800) | |
504 const UWORD8 MIN_TXPWR_DCS[] = | |
505 { | |
506 0, // unused. | |
507 0, // Power class = 1. | |
508 3, // Power class = 2. | |
509 29 // Power class = 3. | |
510 }; | |
511 | |
512 const UWORD8 MIN_TXPWR_GSM850[] = | |
513 { | |
514 0, // unused. | |
515 0, // Power class = 1, unused for GSM900 | |
516 2, // Power class = 2. | |
517 3, // Power class = 3. | |
518 5, // Power class = 4. | |
519 7 // Power class = 5. | |
520 }; | |
521 | |
522 // #elif (STD == DUAL) | |
523 // const UWORD8 MIN_TXPWR_GSM[] = | |
524 // { | |
525 // 0, // unused. | |
526 // 0, // Power class = 1, unused for GSM900 | |
527 // 2, // Power class = 2. | |
528 // 3, // Power class = 3. | |
529 // 5, // Power class = 4. | |
530 // 7 // Power class = 5. | |
531 // }; | |
532 // const UWORD8 MIN_TXPWR_DCS[] = | |
533 // { | |
534 // 0, // unused. | |
535 // 0, // Power class = 1. | |
536 // 3, // Power class = 2. | |
537 // 29 // Power class = 3. | |
538 // }; | |
539 // #endif | |
540 | |
541 const UWORD8 GAUG_VS_PAGING_RATE[] = | |
542 { | |
543 4, // bs_pa_mfrms = 2, 1 gauging every 4 Paging blocs | |
544 3, // bs_pa_mfrms = 3, 1 gauging every 3 Paging blocs | |
545 2, // bs_pa_mfrms = 4, 1 gauging every 2 Paging blocs | |
546 1, // bs_pa_mfrms = 5, 1 gauging every 1 Paging bloc | |
547 1, // bs_pa_mfrms = 6, 1 gauging every 1 Paging bloc | |
548 1, // bs_pa_mfrms = 7, 1 gauging every 1 Paging bloc | |
549 1, // bs_pa_mfrms = 8, 1 gauging every 1 Paging bloc | |
550 1 // bs_pa_mfrms = 9, 1 gauging every 1 Paging bloc | |
551 }; | |
552 | |
553 #else | |
554 extern T_IDLE_TASK_INFO IDLE_INFO_COMB[(MAX_AG_BLKS_RES_COMB+1) * (MAX_PG_BLOC_INDEX_COMB+1)]; | |
555 extern T_IDLE_TASK_INFO IDLE_INFO_NCOMB[(MAX_AG_BLKS_RES_NCOMB+1) * (MAX_PG_BLOC_INDEX_NCOMB+1)]; | |
556 extern UWORD8 NBPCH_IN_MF51_NCOMB[(MAX_AG_BLKS_RES_NCOMB+1)]; | |
557 extern UWORD8 NBPCH_IN_MF51_COMB[(MAX_AG_BLKS_RES_COMB+1)]; | |
558 extern UWORD8 DSC_INIT_VALUE[MAX_BS_PA_MFRMS-2]; | |
559 extern T_SDCCH_DESC SDCCH_DESC_NCOMB[]; | |
560 extern T_SDCCH_DESC SDCCH_DESC_COMB[]; | |
561 extern UWORD8 RNTABLE[114]; | |
562 extern UWORD8 COMBINED_RA_DISTRIB[51]; | |
563 extern T_TASK_MFTAB TASK_ROM_MFTAB[NBR_DL_L1S_TASKS]; | |
564 extern UWORD8 DSP_TASK_CODE[NBR_DL_L1S_TASKS]; | |
565 extern UWORD8 REPORTING_PERIOD[]; | |
566 extern UWORD8 TOA_PERIOD_LEN[]; | |
567 extern UWORD8 MIN_TXPWR_GSM[]; | |
568 extern UWORD8 MIN_TXPWR_DCS[]; | |
569 extern UWORD8 MIN_TXPWR_PCS[]; | |
570 extern UWORD8 MIN_TXPWR_GSM850[]; | |
571 extern UWORD8 GAUG_VS_PAGING_RATE[]; | |
572 #endif | |
573 #endif //L1_TABS_H |