FreeCalypso > hg > freecalypso-citrine
comparison L1/include/l1_time.h @ 3:f93dab57b032
L1/include: TCS211-based version restored
author | Mychaela Falconia <falcon@freecalypso.org> |
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date | Thu, 09 Jun 2016 00:45:00 +0000 |
parents | 75a11d740a02 |
children |
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2:7c13c26f1aa4 | 3:f93dab57b032 |
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89 | 89 |
90 | 90 |
91 #define D_NSUBB_IDLE 296L // Nb of 48 samples window for FBNEW task. | 91 #define D_NSUBB_IDLE 296L // Nb of 48 samples window for FBNEW task. |
92 #if (CODE_VERSION==SIMULATION) | 92 #if (CODE_VERSION==SIMULATION) |
93 #define D_NSUBB_DEDIC 31L // Nb of 48 samples window for FB26 task. | 93 #define D_NSUBB_DEDIC 31L // Nb of 48 samples window for FB26 task. |
94 //To simulate the handling of the worst case (FB/SB task with class 12 allocation), | |
95 //this parameter used in the computation of FB26_ACQUIS_DURATION has to fit with the | |
96 //value used outside the PC simulation (D_NSUBB_DEDIC) | |
97 //This value will only be used for mac_mode = Extended Dynamic Allocation to minimize the | |
98 //impact on reference simulation files for other allocation modes | |
99 #if L1_EDA | |
100 #define D_NSUBB_DEDIC_EDA 30L // Nb of 48 samples window for FB26 task. | |
101 #endif | |
102 #else | 94 #else |
103 #if (DSP >= 32) | 95 #if (DSP == 33) || (DSP == 34) || (DSP == 35) || (DSP == 32) || (DSP == 36) |
104 #define D_NSUBB_DEDIC 30L // Nb of 48 samples window for FB26 task. | 96 #define D_NSUBB_DEDIC 30L // Nb of 48 samples window for FB26 task. |
105 #else | 97 #else |
106 #define D_NSUBB_DEDIC 31L // Nb of 48 samples window for FB26 task. | 98 #define D_NSUBB_DEDIC 31L // Nb of 48 samples window for FB26 task. |
107 #endif | 99 #endif |
108 #endif | 100 #endif |
115 #define EXTENDED_TAIL_WIDTH ( 8L * 4L ) | 107 #define EXTENDED_TAIL_WIDTH ( 8L * 4L ) |
116 #define TPU_CLOCK_RANGE ( 5000L ) | 108 #define TPU_CLOCK_RANGE ( 5000L ) |
117 #define SWITCH_TIME ( TPU_CLOCK_RANGE - EPSILON_SYNC ) // = 4990, time for offset change. | 109 #define SWITCH_TIME ( TPU_CLOCK_RANGE - EPSILON_SYNC ) // = 4990, time for offset change. |
118 | 110 |
119 #define PROVISION_TIME ( 66L ) | 111 #define PROVISION_TIME ( 66L ) |
120 | 112 #define EPSILON_SYNC ( 10L ) // synchro change: max TOA shift=8qbits, 2qbits TPU scenario exec. |
121 #ifndef EPSILON_SYNC | 113 #define EPSILON_OFFS ( 2L ) // offset change: 2qbits for TPU scenario exec. |
122 #define EPSILON_SYNC ( 10L ) // synchro change: max TOA shift=8qbits, 2qbits TPU scenario exec. | 114 #define EPSILON_MEAS ( 20L ) // margin kept between RX and PW meas or between PW meas |
123 #endif | 115 #define SERV_OFFS_REST_LOAD ( 1L ) // 1qbit TPU scen exec. for serv. cell offset restore |
124 | |
125 #ifndef EPSILON_OFFS | |
126 #define EPSILON_OFFS ( 2L ) // offset change: 2qbits for TPU scenario exec. | |
127 #endif | |
128 | |
129 #ifndef EPSILON_MEAS | |
130 #define EPSILON_MEAS ( 20L ) // margin kept between RX and PW meas or between PW meas | |
131 #endif | |
132 | |
133 #ifndef SERV_OFFS_REST_LOAD | |
134 #define SERV_OFFS_REST_LOAD ( 1L ) // 1qbit TPU scen exec. for serv. cell offset restore | |
135 #endif | |
136 | |
137 #define TPU_SLEEP_LOAD ( 2L ) // 2qbit TPU scen exec. for TPU sleep | 116 #define TPU_SLEEP_LOAD ( 2L ) // 2qbit TPU scen exec. for TPU sleep |
138 #if (CODE_VERSION==SIMULATION) | 117 #if (CODE_VERSION==SIMULATION) |
139 #define DL_ABB_DELAY ( 32L ) // RX ABB filter delay | 118 #define DL_ABB_DELAY ( 32L ) // RX ABB filter delay |
140 #else | 119 #else |
141 #if (RF_FAM != 61) | 120 #define DL_ABB_DELAY ( 32L + 4L) // RX ABB filter delay |
142 #ifndef DL_ABB_DELAY //Flexi ABB Delays defines it in tpudrvXX.c | |
143 #define DL_ABB_DELAY ( 32L + 4L) // RX ABB filter delay | |
144 #endif | |
145 #endif | |
146 #if (RF_FAM == 61) | |
147 #ifndef DL_ABB_DELAY //Flexi ABB Delays defines it in tpudrvXX.c | |
148 #define DL_ABB_DELAY ( 41L + 4L) // RX DRP filter delay | |
149 #endif | |
150 #endif | |
151 #endif | 121 #endif |
152 | 122 |
153 // DMA threshold used for sample acquisition by the DSP | 123 // DMA threshold used for sample acquisition by the DSP |
154 #if (CODE_VERSION==SIMULATION) | 124 #if (CODE_VERSION==SIMULATION) |
155 #define RX_DMA_THRES ( 1L ) | 125 #define RX_DMA_THRES ( 1L ) |
168 #define RX_DMA_DELAY (RX_DMA_THRES - 1) * 2 | 138 #define RX_DMA_DELAY (RX_DMA_THRES - 1) * 2 |
169 | 139 |
170 #if (CODE_VERSION==SIMULATION) | 140 #if (CODE_VERSION==SIMULATION) |
171 #define TULSET_DURATION ( 16L ) // Uplink power on setup time | 141 #define TULSET_DURATION ( 16L ) // Uplink power on setup time |
172 #define BULRUDEL_DURATION ( 2L ) | 142 #define BULRUDEL_DURATION ( 2L ) |
173 #if ((ANALOG == 1) || (ANALOG == 2) || (ANALOG == 3) || (ANALOG == 11)) | 143 #if ((ANALOG == 1) || (ANALOG == 2) || (ANALOG == 3)) |
174 // 16 qbits are added because the Calibration time is reduced of 4 GSM bit | 144 // 16 qbits are added because the Calibration time is reduced of 4 GSM bit |
175 // due to a slow APC ramp of OMEGA (Cf. START_TX_NB) | 145 // due to a slow APC ramp of OMEGA (Cf. START_TX_NB) |
176 #define UL_VEGA_DELAY ( TULSET_DURATION + BULRUDEL_DURATION +16L ) // = 18qbits, TX Vega delay | 146 #define UL_VEGA_DELAY ( TULSET_DURATION + BULRUDEL_DURATION +16L ) // = 18qbits, TX Vega delay |
177 #endif | 147 #endif |
178 #endif | 148 #endif |
179 | 149 |
180 #define SB_MARGIN ( 23L * 4L ) // = 92 | 150 #define SB_MARGIN ( 23L * 4L ) // = 92 |
181 #define NB_MARGIN ( 3L * 4L ) // = 12 | 151 #define NB_MARGIN ( 3L * 4L ) // = 12 |
182 | 152 #define TA_MAX ( 63L * 4L ) // = 252 |
183 #ifndef TA_MAX //flexi Abb Delays defined in tpudrvXX.h | |
184 #define TA_MAX ( 63L * 4L ) // = 252 | |
185 #endif | |
186 | 153 |
187 #define SB_BURST_DURATION ( TAIL_WIDTH + ( 142L * 4L) ) // = 580, required for Demodulation | 154 #define SB_BURST_DURATION ( TAIL_WIDTH + ( 142L * 4L) ) // = 580, required for Demodulation |
188 #define NB_BURST_DURATION_DL ( TAIL_WIDTH + ( 142L * 4L) ) // = 580, required for Demodulation | 155 #define NB_BURST_DURATION_DL ( TAIL_WIDTH + ( 142L * 4L) ) // = 580, required for Demodulation |
189 #define PW_BURST_DURATION ( 64L * 4L ) // = 256 | 156 #define PW_BURST_DURATION ( 64L * 4L ) // = 256 |
190 #define RA_BURST_DURATION ( EXTENDED_TAIL_WIDTH + TAIL_WIDTH + ( 77L * 4L ) ) // = 352 = 88*4 | 157 #define RA_BURST_DURATION ( EXTENDED_TAIL_WIDTH + TAIL_WIDTH + ( 77L * 4L ) ) // = 352 = 88*4 |
201 //------------------ | 168 //------------------ |
202 #define SB_ACQUIS_DURATION ( SB_MARGIN + SB_BURST_DURATION + SB_MARGIN + DL_ABB_DELAY + RX_DMA_DELAY ) // = 796 + DMA delay | 169 #define SB_ACQUIS_DURATION ( SB_MARGIN + SB_BURST_DURATION + SB_MARGIN + DL_ABB_DELAY + RX_DMA_DELAY ) // = 796 + DMA delay |
203 #define NB_ACQUIS_DURATION ( NB_MARGIN + NB_BURST_DURATION_DL + NB_MARGIN + DL_ABB_DELAY + RX_DMA_DELAY ) // = 636 + DMA delay | 170 #define NB_ACQUIS_DURATION ( NB_MARGIN + NB_BURST_DURATION_DL + NB_MARGIN + DL_ABB_DELAY + RX_DMA_DELAY ) // = 636 + DMA delay |
204 #define PW_ACQUIS_DURATION ( PW_BURST_DURATION + DL_ABB_DELAY + RX_DMA_DELAY ) // = 288 + DMA delay | 171 #define PW_ACQUIS_DURATION ( PW_BURST_DURATION + DL_ABB_DELAY + RX_DMA_DELAY ) // = 288 + DMA delay |
205 #define FB_ACQUIS_DURATION ( ( D_NSUBB_IDLE * 48L * 4L ) + ( 48L * 4L ) + DL_ABB_DELAY + RX_DMA_DELAY ) // = 57056 + DMA delay | 172 #define FB_ACQUIS_DURATION ( ( D_NSUBB_IDLE * 48L * 4L ) + ( 48L * 4L ) + DL_ABB_DELAY + RX_DMA_DELAY ) // = 57056 + DMA delay |
206 #if (L1_EDA) && (CODE_VERSION==SIMULATION) | |
207 #define FB26_ACQUIS_DURATION_DEFAULT ( ( D_NSUBB_DEDIC * 48L * 4L ) + DL_ABB_DELAY + RX_DMA_DELAY) // = 5984 + DMA delay | |
208 #define FB26_ACQUIS_DURATION_FOR_EDA ( ( D_NSUBB_DEDIC_EDA * 48L * 4L ) + DL_ABB_DELAY + RX_DMA_DELAY) // = 5984 + DMA delay | |
209 #else | |
210 #define FB26_ACQUIS_DURATION ( ( D_NSUBB_DEDIC * 48L * 4L ) + DL_ABB_DELAY + RX_DMA_DELAY) // = 5984 + DMA delay | 173 #define FB26_ACQUIS_DURATION ( ( D_NSUBB_DEDIC * 48L * 4L ) + DL_ABB_DELAY + RX_DMA_DELAY) // = 5984 + DMA delay |
211 #endif | |
212 | 174 |
213 #define START_RX_FB ( PROVISION_TIME ) // = 66 | 175 #define START_RX_FB ( PROVISION_TIME ) // = 66 |
214 #define START_RX_SB ( PROVISION_TIME ) // = 66 | 176 #define START_RX_SB ( PROVISION_TIME ) // = 66 |
215 #define START_RX_SNB ( PROVISION_TIME ) // = 66 | 177 #define START_RX_SNB ( PROVISION_TIME ) // = 66 |
216 #define START_RX_PW_1 ( PROVISION_TIME ) // = 66 | 178 #define START_RX_PW_1 ( PROVISION_TIME ) // = 66 |
219 #define START_TX_NB ( 0L ) | 181 #define START_TX_NB ( 0L ) |
220 #define START_TX_RA ( 0L ) | 182 #define START_TX_RA ( 0L ) |
221 | 183 |
222 #define STOP_RX_FB ( (PROVISION_TIME + FB_ACQUIS_DURATION) % TPU_CLOCK_RANGE ) // = 2122 | 184 #define STOP_RX_FB ( (PROVISION_TIME + FB_ACQUIS_DURATION) % TPU_CLOCK_RANGE ) // = 2122 |
223 #define STOP_RX_SB ( (START_RX_SB + SB_ACQUIS_DURATION) % TPU_CLOCK_RANGE ) // = 862 | 185 #define STOP_RX_SB ( (START_RX_SB + SB_ACQUIS_DURATION) % TPU_CLOCK_RANGE ) // = 862 |
224 #if ((REL99 == 1) && (FF_BHO == 1)) | |
225 #define STOP_RX_FBSB ( (STOP_RX_FB + 800L ) % TPU_CLOCK_RANGE ) // = 2922 | |
226 #endif | |
227 #define STOP_RX_SNB ( (START_RX_SNB + NB_ACQUIS_DURATION) % TPU_CLOCK_RANGE ) // = 702 | 186 #define STOP_RX_SNB ( (START_RX_SNB + NB_ACQUIS_DURATION) % TPU_CLOCK_RANGE ) // = 702 |
228 #define STOP_RX_PW_1 ( (START_RX_PW_1 + PW_ACQUIS_DURATION) % TPU_CLOCK_RANGE ) // = 354 | 187 #define STOP_RX_PW_1 ( (START_RX_PW_1 + PW_ACQUIS_DURATION) % TPU_CLOCK_RANGE ) // = 354 |
229 #define STOP_RX_FB26 ( (START_RX_FB26 + FB26_ACQUIS_DURATION) % TPU_CLOCK_RANGE ) // = 4314 | 188 #define STOP_RX_FB26 ( (START_RX_FB26 + FB26_ACQUIS_DURATION) % TPU_CLOCK_RANGE ) // = 4314 |
230 | 189 |
231 #if (REL99 == 1 && FF_RTD == 1) // RTD feature | |
232 #define RTD_UNIT_MARGIN ( ((TPU_CLOCK_RANGE-8)/128L) + 1 ) // unit of RTD is 1/64 TDMA frame | |
233 #define RTD_RIGHT_MARGIN ( (TA_MAX/2L) + (RTD_UNIT_MARGIN) ) | |
234 #define RTD_LEFT_MARGIN ( RTD_RIGHT_MARGIN ) | |
235 #endif | |
236 | 190 |
237 //================================ | 191 //================================ |
238 // Definitions used for GPRS | 192 // Definitions used for GPRS |
239 //================================ | 193 //================================ |
240 | 194 |