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L1/dyn_dwl_cfile: new code compiles
author Mychaela Falconia <falcon@freecalypso.org>
date Fri, 10 Jun 2016 09:13:00 +0000
parents 75a11d740a02
children
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/*
 * These 7 branch instructions, corresponding to ARM exception and interrupt
 * vectors, will be placed in different sections depending on the flashImage
 * vs. ramImage configuration and which target we build for; this little
 * snippet file will be #included where it is needed.
 */

	b	_arm_undefined
	b	_arm_swi
	b	_arm_abort_prefetch
	b	_arm_abort_data
	b	_arm_reserved
	b	_INT_IRQ
	b	_INT_FIQ