FreeCalypso > hg > freecalypso-citrine
changeset 3:f93dab57b032
L1/include: TCS211-based version restored
| author | Mychaela Falconia <falcon@freecalypso.org> |
|---|---|
| date | Thu, 09 Jun 2016 00:45:00 +0000 |
| parents | 7c13c26f1aa4 |
| children | 1a22dd26c8a4 |
| files | L1/include/l1_api_hisr.h L1/include/l1_confg.h L1/include/l1_const.h L1/include/l1_ctl.h L1/include/l1_defty.h L1/include/l1_macro.h L1/include/l1_mftab.h L1/include/l1_msgty.h L1/include/l1_proto.h L1/include/l1_rtt_macro.h L1/include/l1_signa.h L1/include/l1_tabs.h L1/include/l1_time.h L1/include/l1_trace.h L1/include/l1_types.h L1/include/l1_varex.h L1/include/l1_ver.h |
| diffstat | 17 files changed, 2062 insertions(+), 5228 deletions(-) [+] |
line wrap: on
line diff
--- a/L1/include/l1_api_hisr.h Thu Jun 09 00:19:28 2016 +0000 +++ b/L1/include/l1_api_hisr.h Thu Jun 09 00:45:00 2016 +0000 @@ -10,10 +10,11 @@ #ifndef _L1_API_HISR_H_ #define _L1_API_HISR_H_ -#if (L1_DYN_DSP_DWNLD == 1) /* Constants */ #define ID_API_INT 0x4 -#endif + +/* Prototypes */ void l1_trigger_api_interrupt(); +void l1_api_handler(); #endif
--- a/L1/include/l1_confg.h Thu Jun 09 00:19:28 2016 +0000 +++ b/L1/include/l1_confg.h Thu Jun 09 00:45:00 2016 +0000 @@ -3,7 +3,7 @@ * L1_CONFG.H * * Filename l1_confg.h - * Copyright 2003 (C) Texas Instruments + * Copyright 2003 (C) Texas Instruments * ************* Revision Controle System Header *************/ @@ -32,7 +32,7 @@ #define SIMULATION 1 #define NOT_SIMULATION 2 -// RLC functions Version possible choices +// RCL functions Version possible choices //------------------------------ #define POLL_FORCED 0 #define RLC_SCENARIO 1 @@ -40,15 +40,10 @@ // possible choices for UART trace output //------------------------------ -#if (CHIPSET != 15) - #define MODEM_UART 0 - #define IRDA_UART 1 - #if (CHIPSET == 12) - #define MODEM2_UART 2 - #endif -#else - // There is only one UART in Locosto - #define MODEM_UART 0 +#define MODEM_UART 0 +#define IRDA_UART 1 +#if (CHIPSET == 12) + #define MODEM2_UART 2 #endif //============ @@ -59,9 +54,9 @@ #define CODE_VERSION NOT_SIMULATION #else // OP_L1_STANDALONE #ifdef WIN32 - #define CODE_VERSION SIMULATION +#define CODE_VERSION SIMULATION #else // WIN32 - #define CODE_VERSION NOT_SIMULATION +#define CODE_VERSION NOT_SIMULATION #endif // WIN32 #endif // OP_L1_STANDALONE #endif // #if 0 @@ -94,32 +89,14 @@ //--------------------------------------------------------------------------------- #if (CODE_VERSION == SIMULATION) - - #undef FF_L1_IT_DSP_USF - #define FF_L1_IT_DSP_USF 0 - #undef FF_L1_IT_DSP_DTX -#if (AMR == 1) - #define FF_L1_IT_DSP_DTX 1 //it should be 1, sajal- temp made it 0 for build purpose -#else - #define FF_L1_IT_DSP_DTX 0 -#endif - - #define L1_DRP_IQ_SCALING 0 - // Test Scenari... #define SCENARIO_FILE 1 // Test Scenario comes from input files. #define SCENARIO_MEM 0 // Test Scenario comes from RAM. - // In Simulation AUDIO_DEBUG Should be 0 - #define AUDIO_DEBUG 0 - // Traces... #undef TRACE_TYPE #define TRACE_TYPE 5 #define LOGFILE_TRACE 1 // trace in an output logfile - - #define BURST_PARAM_LOG_ENABLE 0 // Burst Param Log Enable - #define FLOWCHART 0 // Message sequence/flow chart trace. #define NUCLEUS_TRACE 0 // Nucleus error trace #define EOTD_TRACE 1 // EOTD log trace @@ -129,15 +106,11 @@ // Control algorithms... #define AFC_ALGO 1 // AFC algorithm. -#if (L1_SAIC != 0) - #define TOA_ALGO 2 // TOA algorithm. -#else #define TOA_ALGO 1 // TOA algorithm. -#endif #define AGC_ALGO 1 // AGC algorithm. #define TA_ALGO 0 // TA (Timing Advance) algorithm. #undef VCXO_ALGO - #define VCXO_ALGO 1 // VCXO algo + #define VCXO_ALGO 0 // VCXO algo #undef DCO_ALGO #define DCO_ALGO 0 // DCO algo (TIDE) #undef ORDER2_TX_TEMP_CAL @@ -154,11 +127,11 @@ #define AUDIO_L1_STANDALONE 0 // Flag to enable the audio simulator used with the L1 stand-alone (works only with the new audio design i.e. AUDIO_TASK=1) #define GTT_SIMULATION 1 // Gtt simulator for the gtt tasks (works only with if L1_GTT=1) - #define TTY_SYNC_MCU 0 // TTY WORKAROUND BUG03401 - #define TTY_SYNC_MCU_2 0 // + #define TTY_SYNC_MCU 1 // TTY WORKAROUND BUG03401 + #define TTY_SYNC_MCU_2 1 // #define L1_GTT_FIFO_TEST_ATOMIC 0 // #define NEW_WKA_PATCH 0 - #define OPTIMISED 0 + #define OPTIMISED 1 #define L1_RECOVERY 0 // L1 recovery @@ -182,61 +155,12 @@ #undef OP_WCP #define OP_WCP 0 // No WCP integration - - #undef L1_DRP - #define L1_DRP 0 // L1 supporting DRP interface - - #undef DRP_MEM_SIMULATION - #define DRP_MEM_SIMULATION 0 //--------------------------------------------------------------------------------- // Test with H/W platform. //--------------------------------------------------------------------------------- - - #if (GSM_IDLE_RAM == 1) - #define GSM_IDLE_RAM_DEBUG 0 - #endif - - #define AFC_BYPASS_MODE 0 - #define PWMEAS_IF_MODE_FORCE 0 -// WA for OMAPS00099442 must be disabled in PC simulation - #undef L1_FF_WA_OMAPS00099442 - #define L1_FF_WA_OMAPS00099442 0 - #elif (CODE_VERSION == NOT_SIMULATION) - #define L1_DRP_IQ_SCALING 1 - // In Target AUDIO_DEBUG could be turned ON to debug any AUDIO ON/OFF issues - #define AUDIO_DEBUG 0 - - #if (GSM_IDLE_RAM == 1) - #if ((CHIPSET == 12) || (CHIPSET == 10)) - #define GSM_IDLE_RAM_DEBUG 1 - #else - #define GSM_IDLE_RAM_DEBUG 0 - #endif - #else - #define GSM_IDLE_RAM_DEBUG 0 - #endif - -//FreeCalypso: L1_VPM commented out, as I suspect it's a LoCosto-ism -//#define L1_VPM 1 - - #if (OP_L1_STANDALONE == 1) - #if (CHIPSET == 15) - #if ((BOARD == 71) && (FLASH == 0)) - // Not possible in I-SAMPLE only RAM configuration as there will - // not be enough memory space - #define BURST_PARAM_LOG_ENABLE 0 - #else - #define BURST_PARAM_LOG_ENABLE 1 - #endif - #else - #define BURST_PARAM_LOG_ENABLE 0 - #endif - #else - #define BURST_PARAM_LOG_ENABLE 0 - #endif - + #define WA_PCTM_AGC_PARAMS 0 // to work by default with 4 parameters to calibration (compatible with PCTM if 1) // Work around about Calypso RevA: the bus is floating (Cf PB01435) // (corrected with Calypso ReV B and Calypso C035) #if (CHIPSET == 7) @@ -245,22 +169,16 @@ #define W_A_CALYPSO_BUG_01435 0 #endif - #if (CHIPSET == 12) // Not needed for CHIPSET =15, as there is no extended page mode in Locosto - #define W_A_CALYPSO_PLUS_SPR_19599 1 - #else - #define W_A_CALYPSO_PLUS_SPR_19599 0 - #endif // for AMR thresolds definition CQ22226 - #define W_A_AMR_THRESHOLDS 1 - #define W_A_PCTM_RX_AGC_GLOBAL_PARAMS 1 // For support of PCTM + #define AMR_THRESHOLDS_WORKAROUND 1 #if (L1_GTT==1) - #define TTY_SYNC_MCU 0 - #define TTY_SYNC_MCU_2 0 + #define TTY_SYNC_MCU 1 + #define TTY_SYNC_MCU_2 1 #define L1_GTT_FIFO_TEST_ATOMIC 0 #define NEW_WKA_PATCH 0 - #define OPTIMISED 0 + #define OPTIMISED 1 #else #define TTY_SYNC_MCU_2 0 #define L1_GTT_FIFO_TEST_ATOMIC 0 @@ -269,28 +187,7 @@ #define OPTIMISED 0 #endif - -/* - * FreeCalypso: these FF_L1_IT_DSP_USF and FF_L1_IT_DSP_DTX features (?) - * are new with the LoCosto L1 headers, i.e., not present in the Leonardo - * headers. I have no idea what they are, and I suspect they may likely - * be something that won't work on our Calypso platform, so I'm disabling - * them for now. - */ - - #undef FF_L1_IT_DSP_USF -#if 0 //(L1_GPRS == 1) - #define FF_L1_IT_DSP_USF 1 -#else - #define FF_L1_IT_DSP_USF 0 -#endif - #undef FF_L1_IT_DSP_DTX -#if 0 //(AMR == 1) - #define FF_L1_IT_DSP_DTX 1 -#else - #define FF_L1_IT_DSP_DTX 0 -#endif - + // Traces... #define NUCLEUS_TRACE 0 // Nucleus error trace #define FLOWCHART 0 // Message sequence/flow chart trace. @@ -310,11 +207,7 @@ // Control algorithms... #define AFC_ALGO 1 // AFC algorithm. //TOA Algorithm needs to be on for TestMode, otherwise no dedic test will be succesful!!! -#if (L1_SAIC != 0) - #define TOA_ALGO 2 // TOA algorithm. -#else #define TOA_ALGO 1 // TOA algorithm. -#endif #define AGC_ALGO 1 // AGC algorithm. #define TA_ALGO 1 // TA (Timing Advance) algorithm. @@ -336,16 +229,10 @@ #define GTT_SIMULATION 0 // Gtt simulator for the gtt tasks (works only with if L1_GTT=1) - #define OP_BT 0 // Simulation of ISLAND (BLUETOOTH) sleep management + #define OP_BT 0 // Simulation of ISLAND (BLUETOOTH) sleep management #define L1_RECOVERY 1 // L1 recovery - #if ((RF_FAM == 60) || (RF_FAM == 61)) - #define L1_DRP 1 // L1 supporting DRP interface - #else - #define L1_DRP 0 // L1 supporting DRP interface - #endif - #define DRP_MEM_SIMULATION 0 // DRP memory simulation OFF by default #if (L1_GPRS == 1) #define RLC_VERSION RLC_SCENARIO @@ -371,16 +258,6 @@ #define DSP_BACKGROUND_TASKS 0 #define RLC_DL_BLOCK_STAT 0 // Default value; Never change it #endif -#define PWMEAS_IF_MODE_FORCE 1 -// WA for OMAPS00099442 (OMAPS0010023 (N12.x), OMAPS000010022 (N5.x)) - // The problem is: When NW is lost due to reception gap or cell border range, - // the MS will try to re-synchronize on the cell with the TPU timing aligned - // with the timing of the cell. So the FB will start within the 92 bits of the TPU window and - // will be missed. This issue is due to a limitation of the legacy FB demodulation algorithm - // WA is to re-initialize the TPU with an arbitrary timing value - #undef L1_FF_WA_OMAPS00099442 - #define L1_FF_WA_OMAPS00099442 1 - #endif // Audio tasks selection @@ -393,60 +270,48 @@ #if (OP_L1_STANDALONE == 1) #define GSMLITE 1 #endif - #if (CODE_VERSION == SIMULATION) - #define L1_VOICE_MEMO 1 - #endif #if ((OP_L1_STANDALONE == 1) || (!GSMLITE)) #define MELODY_E1 1 // Enable melody format E1 feature + #define VOICE_MEMO 1 // Enable voice memorization feature - #if(L1_VOICE_MEMO == 1) - #define VOICE_MEMO 1 // Enable voice memorization feature - #else - #define VOICE_MEMO 0 - #endif #define FIR 1 // Enable FIR feature - #if (DSP >= 33) + #if (DSP == 33) || (DSP == 34) || (DSP == 35) || (DSP == 36) #define AUDIO_MODE 1 // Enable Audio mode feature #else #define AUDIO_MODE 0 // Disable Audio mode feature #endif #else #define MELODY_E1 0 // Disable melody format E1 feature - #if(L1_VOICE_MEMO == 1) - #define VOICE_MEMO 1 // Enable voice memorization feature - #else - #define VOICE_MEMO 0 + #define VOICE_MEMO 0 // Disable voice memorization feature + #if (MELODY_E2) + #define FIR 1 // Enable FIR feature + #else + #define FIR 0 // Disable FIR feature #endif - #if (MELODY_E2) - #define FIR 1 // Enable FIR feature - #else - #define FIR 0 // Disable FIR feature - #endif + #define AUDIO_MODE 0 // Disable Audio mode feature #endif - + // Define CPORT for ESample only + #if ((CHIPSET == 12) && ((DSP == 35) || (DSP == 36))) + #define L1_CPORT 1 // Enable cport feature + #else + #define L1_CPORT 0 // Disable cport feature + #endif #else #define KEYBEEP 0 // Enable keybeep feature #define TONE 0 // Enable tone feature #define MELODY_E1 0 // Enable melody format E1 feature - #define VOICE_MEMO 0 // Enable voice memorization feature + #define VOICE_MEMO 0 // Enable voice memorization feature + #define FIR 0 // Enable FIR feature #define AUDIO_MODE 0 // Enable Audio mode feature + #define L1_CPORT 0 // Enable cport feature #endif -//FreeCalypso: LoCosto-ism below disabled -//#define L1_MIDI_BUFFER 1 - -/* - * L1_CPORT appears in the Leonardo L1 headers, and is enabled only for - * CHIPSET 12. The LoCosto version doesn't have it at all. - */ -#define L1_CPORT 0 - #define L1_AUDIO_BACKGROUND_TASK (SPEECH_RECO | MELODY_E2) // audio background task is used by speech reco and melody_e2 #if (OP_RIV_AUDIO == 1) - #define L1_AUDIO_DRIVER (L1_VOICE_MEMO_AMR | L1_EXT_AUDIO_MGT | L1_MP3) // Riviera audio driver (only Voice Memo AMR is available) + #define L1_AUDIO_DRIVER L1_VOICE_MEMO_AMR // Riviera audio driver (only Voice Memo AMR is available) #endif @@ -460,7 +325,6 @@ // Standard (frequency plan) selections //------------------------------------- -#if(L1_FF_MULTIBAND == 0) // std id is not used if multiband feature is enabled #define GSM 1 // GSM900. #define GSM_E 2 // GSM900 Extended. @@ -471,27 +335,12 @@ #define GSM850 7 // GSM850 Band #define DUAL_US 8 // PCS1900 + GSM850 -#endif // L1_FF_MULTIBAND - /*------------------------------------*/ /* Power Management */ /*------------------------------------*/ #define PWR_MNGT 1 // POWER management active if l1_config.pwr_mngt=1 -/*------------------------------------*/ -/* BT Audio */ -/*------------------------------------*/ -#if ((L1_MP3 == 1) || (L1_AAC == 1)) -#if (OP_L1_STANDALONE == 0) -#if((PSP_STANDALONE == 1) || (DRP_FW_BUILD == 1)) -#define L1_BT_AUDIO 0 -#else -#define L1_BT_AUDIO 1 -#endif -#else -#define L1_BT_AUDIO 0 -#endif -#endif + /*---------------------------------------------------------------------------*/ /* DSP configurations */ /* ------------------ */ @@ -552,11 +401,11 @@ // In case of the melody E2 the DSP trace must be disable because the // melody instrument waves are overlayed with DSP trace buffer - // DSP debug trace API buffer config + // DSP debug trace API buufer config #define C_DEBUG_BUFFER_ADD 0x17ff // Address of DSP write pointer... data are just after. #define C_DEBUG_BUFFER_SIZE 7 // Real size is incremented by 1 for DSP write pointer. #else - // DSP debug trace API buffer config + // DSP debug trace API buufer config #define C_DEBUG_BUFFER_ADD 0x17ff // Address of DSP write pointer... data are just after. #define C_DEBUG_BUFFER_SIZE 2047 // Real size is incremented by 1 for DSP write pointer. #endif @@ -619,8 +468,12 @@ #define C_PLL_CONFIG 0x154 // For VTCXO = 13 MHz and max DSP speed = 84.5 Mips #define VOC FR_HR_EFR // FR + HR + EFR (normaly FR_EFR : PBs). #define AEC 1 // AEC/NS not supported. - #define L1_NEW_AEC 1 - + #if (OP_RIV_AUDIO == 0) + #define L1_NEW_AEC 1 + #else + // Available but not yet tuned with Riviera AUDIO + #define L1_NEW_AEC 0 + #endif #if ((L1_NEW_AEC) && (!AEC)) // First undef the flag to avoid warnings at compilation time #undef AEC @@ -638,10 +491,14 @@ #define W_A_DSP_SR_BGD 1 // Work around about the DSP speech reco background task. - #if (CODE_VERSION == NOT_SIMULATION) + #if ( (CHIPSET != 12) && (CODE_VERSION == NOT_SIMULATION)) + #define W_A_DSP_IDLE3 1 // Work around to report DSP state to the ARM for Deep Sleep + // management. - // DSP_IDLE3 is not supported in simulation + + // DSP_IDLE3 is not supported in simulation + #else #define W_A_DSP_IDLE3 0 #endif @@ -669,7 +526,7 @@ // In case of the melody E2 the DSP trace must be disable because the // melody instrument waves are overlayed with DSP trace buffer - // DSP debug trace API buffer config + // DSP debug trace API buufer config #define C_DEBUG_BUFFER_ADD 0x17ff // Address of DSP write pointer... data are just after. #define C_DEBUG_BUFFER_SIZE 7 // Real size is incremented by 1 for DSP write pointer. @@ -683,7 +540,7 @@ // Currently not supported ! #endif #else - // DSP debug trace API buffer config + // DSP debug trace API buufer config #define C_DEBUG_BUFFER_ADD 0x17ff // Address of DSP write pointer... data are just after. #define C_DEBUG_BUFFER_SIZE 2047 // Real size is incremented by 1 for DSP write pointer. @@ -693,7 +550,7 @@ #define C_DEBUG_TRACE_TYPE 0x0012 // Level = BASIC; Features = Buffer Header. #if (C_DEBUG_TRACE_TYPE != 0) && ((TRACE_TYPE == 1) || (TRACE_TYPE == 4)) - #define DSP_DEBUG_TRACE_ENABLE 1 // Enable DSP debug trace dumping capability (supported since patch 2090) + #define DSP_DEBUG_TRACE_ENABLE 1 // Enable DSP debug trace dumping capability (supported since patch 2090) #endif #endif /* d_error_status */ @@ -703,7 +560,7 @@ #define D_ERROR_STATUS_TRACE_ENABLE 1 // Enable d_error_status checking capability (supported since patch 2090) // masks to apply on d_error_status bit field for DSP patch 0x2061 or 0x2062 - #define DSP_DEBUG_GSM_MASK 0x08BD // L1_MCU-SPR-15852 + #define DSP_DEBUG_GSM_MASK 0x0000 #define DSP_DEBUG_GPRS_MASK 0x0f3d #endif @@ -719,8 +576,12 @@ #define C_PLL_CONFIG 0x154 // For VTCXO = 13 MHz and max DSP speed = 84.5 Mips #define VOC FR_HR_EFR // FR + HR + EFR (normaly FR_EFR : PBs). #define AEC 1 // AEC/NS not supported. - #define L1_NEW_AEC 1 - + #if (OP_RIV_AUDIO == 0) + #define L1_NEW_AEC 1 + #else + // Available but not yet tuned with Riviera AUDIO + #define L1_NEW_AEC 0 + #endif #if ((L1_NEW_AEC) && (!AEC)) // First undef the flag to avoid warnings at compilation time #undef AEC @@ -737,10 +598,14 @@ #define W_A_DSP_SR_BGD 1 // Work around about the DSP speech reco background task. - #if (CODE_VERSION == NOT_SIMULATION) - #define W_A_DSP_IDLE3 1 // Work around to report DSP state to the ARM for Deep Sleep - // management. - // DSP_IDLE3 is not supported in simulation + #if ( (CHIPSET != 12) && (CODE_VERSION == NOT_SIMULATION)) + + #define W_A_DSP_IDLE3 1 // Work around to report DSP state to the ARM for Deep Sleep + + // management. + + // DSP_IDLE3 is not supported in simulation + #else #define W_A_DSP_IDLE3 0 #endif @@ -767,7 +632,7 @@ // In case of the melody E2 the DSP trace must be disable because the // melody instrument waves are overlayed with DSP trace buffer - // DSP debug trace API buffer config + // DSP debug trace API buufer config #define C_DEBUG_BUFFER_ADD 0x17ff // Address of DSP write pointer... data are just after. #define C_DEBUG_BUFFER_SIZE 7 // Real size is incremented by 1 for DSP write pointer. @@ -781,7 +646,7 @@ // Currently not supported ! #endif #else - // DSP debug trace API buffer config + // DSP debug trace API buufer config #define C_DEBUG_BUFFER_ADD 0x17ff // Address of DSP write pointer... data are just after. #define C_DEBUG_BUFFER_SIZE 2047 // Real size is incremented by 1 for DSP write pointer. @@ -791,7 +656,7 @@ #define C_DEBUG_TRACE_TYPE 0x0012 // Level = BASIC; Features = Buffer Header. #if (C_DEBUG_TRACE_TYPE != 0) && ((TRACE_TYPE == 1) || (TRACE_TYPE == 4)) - #define DSP_DEBUG_TRACE_ENABLE 1 // Enable DSP debug trace dumping capability (supported since patch 2090) + #define DSP_DEBUG_TRACE_ENABLE 1 // Enable DSP debug trace dumping capability (supported since patch 2090) #endif // AMR trace @@ -804,8 +669,8 @@ #if ((TRACE_TYPE == 1) || (TRACE_TYPE == 4)) #define D_ERROR_STATUS_TRACE_ENABLE 1 // Enable d_error_status checking capability (supported since patch 2090) - // masks to apply on d_error_status bit field for DSP patch 0x2061 or 0x2062 - #define DSP_DEBUG_GSM_MASK 0x08BD // L1_MCU-SPR-15852 + // masks to apply on d_error_status bit field + #define DSP_DEBUG_GSM_MASK 0x0000 #define DSP_DEBUG_GPRS_MASK 0x0f3d #endif @@ -816,8 +681,12 @@ #define C_PLL_CONFIG 0x154 // For VTCXO = 13 MHz and max DSP speed = 84.5 Mips #define VOC FR_HR_EFR // FR + HR + EFR (normaly FR_EFR : PBs). #define AEC 1 // AEC/NS not supported. - #define L1_NEW_AEC 1 - + #if (OP_RIV_AUDIO == 0) + #define L1_NEW_AEC 1 + #else + // Available but not yet tuned with Riviera AUDIO + #define L1_NEW_AEC 0 + #endif #if ((L1_NEW_AEC) && (!AEC)) // First undef the flag to avoid warnings at compilation time #undef AEC @@ -826,7 +695,7 @@ #define MAP 3 #define FF_L1_TCH_VOCODER_CONTROL 1 - #define W_A_WAIT_DSP_RESTART_AFTER_VOCODER_ENABLE 1 + #define L1M_WAIT_DSP_RESTART_AFTER_VOCODER_ENABLE 1 #define DSP_START 0x7000 @@ -837,22 +706,18 @@ #define W_A_DSP_SR_BGD 1 // Work around about the DSP speech reco background task. - #if (CODE_VERSION == NOT_SIMULATION) - #if (CHIPSET != 12) - #define W_A_DSP_IDLE3 1 // Work around to report DSP state to the ARM for Deep Sleep - // management. - // DSP_IDLE3 is not supported in simulation - #else - #define W_A_DSP_IDLE3 0 // Work around to report DSP state to the ARM for Deep Sleep - // management. - // DSP_IDLE3 is not supported in simulation - #endif // CHIPSET 12 + #if ( (CHIPSET != 12) && (CODE_VERSION == NOT_SIMULATION)) + + #define W_A_DSP_IDLE3 1 // Work around to report DSP state to the ARM for Deep Sleep + + // management. + + // DSP_IDLE3 is not supported in simulation + #else - #define W_A_DSP_IDLE3 0 + #define W_A_DSP_IDLE3 0 #endif - #define W_A_DSP_PR20037 1 - // DSP software work-around config // bit0 - Work-around to support CRTG. // bit1 - DMA reset on critical DMA still running cases, refer to REQ01260. @@ -875,7 +740,7 @@ // In case of the melody E2 the DSP trace must be disable because the // melody instrument waves are overlayed with DSP trace buffer - // DSP debug trace API buffer config + // DSP debug trace API buufer config #define C_DEBUG_BUFFER_ADD 0x17ff // Address of DSP write pointer... data are just after. #define C_DEBUG_BUFFER_SIZE 7 // Real size is incremented by 1 for DSP write pointer. @@ -889,7 +754,7 @@ // Currently not supported ! #endif #else - // DSP debug trace API buffer config + // DSP debug trace API buufer config #define C_DEBUG_BUFFER_ADD 0x17ff // Address of DSP write pointer... data are just after. #define C_DEBUG_BUFFER_SIZE 2047 // Real size is incremented by 1 for DSP write pointer. @@ -899,7 +764,7 @@ #define C_DEBUG_TRACE_TYPE 0x0012 // Level = BASIC; Features = Timer + Buffer Header + Burst. #if (C_DEBUG_TRACE_TYPE != 0) && ((TRACE_TYPE == 1) || (TRACE_TYPE == 4)) - #define DSP_DEBUG_TRACE_ENABLE 1 // Enable DSP debug trace dumping capability (supported since patch 2090) + #define DSP_DEBUG_TRACE_ENABLE 1 // Enable DSP debug trace dumping capability (supported since patch 2090) #endif // AMR trace @@ -913,27 +778,15 @@ #define D_ERROR_STATUS_TRACE_ENABLE 1 // Enable d_error_status checking capability (supported since patch 2090) // masks to apply on d_error_status bit field for DSP patch 0x2061 or 0x2062 - #define DSP_DEBUG_GSM_MASK 0x08BD // L1_MCU-SPR-15852 + #define DSP_DEBUG_GSM_MASK 0x08BD #define DSP_DEBUG_GPRS_MASK 0x0f3d #endif -#elif (DSP >= 36) // ROM Code GPRS AMR. - - #if ((L1_PCM_EXTRACTION) && (SPEECH_RECO)) - #error "PCM extraction and Speech recognition not supported simultaneously" - #endif - +#elif (DSP == 36) // ROM Code GPRS AMR. #define CLKMOD1 0x4006 // ... #define CLKMOD2 0x4116 // ...65 Mips pll free #define CLKSTART 0x29 // ...65 Mips #define C_PLL_CONFIG 0x154 // For VTCXO = 13 MHz and max DSP speed = 84.5 Mips #define VOC FR_HR_EFR // FR + HR + EFR (normaly FR_EFR : PBs). - -#if 0 - /* what we got with LoCosto L1 headers */ - #define AEC 0 // AEC/NS not supported. - #define L1_NEW_AEC 0 -#else - /* what we are used to from the Leonardo version */ #define AEC 1 // AEC/NS not supported. #if (OP_RIV_AUDIO == 0) #define L1_NEW_AEC 1 @@ -941,8 +794,6 @@ // Available but not yet tuned with Riviera AUDIO #define L1_NEW_AEC 0 #endif -#endif - #if ((L1_NEW_AEC) && (!AEC)) // First undef the flag to avoid warnings at compilation time #undef AEC @@ -952,7 +803,7 @@ #undef L1_AMR_NSYNC #define L1_AMR_NSYNC 1 #define FF_L1_TCH_VOCODER_CONTROL 1 - #define W_A_WAIT_DSP_RESTART_AFTER_VOCODER_ENABLE 1 + #define L1M_WAIT_DSP_RESTART_AFTER_VOCODER_ENABLE 1 #define DSP_START 0x7000 @@ -963,22 +814,18 @@ #define W_A_DSP_SR_BGD 1 // Work around about the DSP speech reco background task. - #if (CODE_VERSION == NOT_SIMULATION) - #if ((CHIPSET != 12) && (CHIPSET != 15)) - #define W_A_DSP_IDLE3 1 // Work around to report DSP state to the ARM for Deep Sleep - // management. - // DSP_IDLE3 is not supported in simulation - #else // CHIPSET 12 - #define W_A_DSP_IDLE3 0 // Work around to report DSP state to the ARM for Deep Sleep - // management. - // DSP_IDLE3 is not supported in simulation - #endif // CHIPSET 12 - #else // CODE_VERSION + #if ( (CHIPSET != 12) && (CODE_VERSION == NOT_SIMULATION)) + + #define W_A_DSP_IDLE3 1 // Work around to report DSP state to the ARM for Deep Sleep + + // management. + + // DSP_IDLE3 is not supported in simulation + + #else #define W_A_DSP_IDLE3 0 #endif - #define W_A_DSP_PR20037 1 - // DSP software work-around config // bit0 - Work-around to support CRTG. // bit1 - DMA reset on critical DMA still running cases, refer to REQ01260. @@ -992,42 +839,50 @@ #elif (ANALOG == 3) // SYREN #define C_DSP_SW_WORK_AROUND 0x000E + #endif - #elif (ANALOG == 11) // TRITON - #define C_DSP_SW_WORK_AROUND 0x000E - + // This workaround should be enabled only for H2-sample on full build config + #if (OP_L1_STANDALONE==1) + #define RAZ_VULSWITCH_REGAUDIO 0 #endif /* DSP debug trace configuration */ /*-------------------------------*/ - // Note: - // In case of melody E2, MP3, AAC or Dyn Dwnld ACTIVITY the DSP trace is automatically disabled - // because the melody instrument waves are overlayed with DSP trace buffer (supported since patch 7c20) + #if (MELODY_E2) + // In case of the melody E2 the DSP trace must be disable because the + // melody instrument waves are overlayed with DSP trace buffer - // DSP debug trace API buffer config + // DSP debug trace API buufer config #define C_DEBUG_BUFFER_ADD 0x17ff // Address of DSP write pointer... data are just after. - #define C_DEBUG_BUFFER_SIZE 2047 // Real size is incremented by 1 for DSP write pointer. + #define C_DEBUG_BUFFER_SIZE 7 // Real size is incremented by 1 for DSP write pointer. // DSP debug trace type config // |<-------------- Features -------------->|<---------- Levels ----------->| // [15-8:UNUSED|7:TIMER|6:BURST|5:BUFFER|4:BUFFER HEADER|3:UNUSED|2:KERNEL|1:BASIC|0:ISR] - - #if (TRACE_TYPE == 1) || (TRACE_TYPE == 4)// C_DEBUG_TRACE_TYPE 0x0012 changed from 0x0054 for DSP load reduce - #define C_DEBUG_TRACE_TYPE 0x0012 // Level = KERNEL; Features = Timer, Burst, Buffer Header. - #else - #define C_DEBUG_TRACE_TYPE 0x0000 // Level = KERNEL; Features = Timer, Burst, Buffer Header. - #endif - + #define C_DEBUG_TRACE_TYPE 0x0000 // Level = BASIC; Features = Timer + Buffer Header + Burst. #if (C_DEBUG_TRACE_TYPE != 0) && ((TRACE_TYPE == 1) || (TRACE_TYPE == 4)) #define DSP_DEBUG_TRACE_ENABLE 1 // Enable DSP debug trace dumping capability // Currently not supported ! #endif + #else + // DSP debug trace API buufer config + #define C_DEBUG_BUFFER_ADD 0x17ff // Address of DSP write pointer... data are just after. + #define C_DEBUG_BUFFER_SIZE 2047 // Real size is incremented by 1 for DSP write pointer. + + // DSP debug trace type config + // |<-------------- Features -------------->|<---------- Levels ----------->| + // [15-8:UNUSED|7:TIMER|6:BURST|5:BUFFER|4:BUFFER HEADER|3:UNUSED|2:KERNEL|1:BASIC|0:ISR] + #define C_DEBUG_TRACE_TYPE 0x0012 // Level = BASIC; Features = Buffer Header. + + #if (C_DEBUG_TRACE_TYPE != 0) && ((TRACE_TYPE == 1) || (TRACE_TYPE == 4)) + #define DSP_DEBUG_TRACE_ENABLE 1 // Enable DSP debug trace dumping capability (supported since patch 2090) + #endif // AMR trace #define C_AMR_TRACE_ID 55 - + #endif /* d_error_status */ /*-------------------------------*/ @@ -1035,7 +890,7 @@ #define D_ERROR_STATUS_TRACE_ENABLE 1 // Enable d_error_status checking capability (supported since patch 2090) // masks to apply on d_error_status bit field for DSP patch 0x2061 or 0x2062 - #define DSP_DEBUG_GSM_MASK 0x08BD // L1_MCU-SPR-15852 + #define DSP_DEBUG_GSM_MASK 0x08BD #define DSP_DEBUG_GPRS_MASK 0x0f3d #endif #endif // DSP @@ -1090,11 +945,9 @@ #ifndef FF_L1_TCH_VOCODER_CONTROL #define FF_L1_TCH_VOCODER_CONTROL 0 - #define W_A_WAIT_DSP_RESTART_AFTER_VOCODER_ENABLE 0 - #define W_A_DSP_PR20037 0 + #define L1M_WAIT_DSP_RESTART_AFTER_VOCODER_ENABLE 0 #endif - /*------------------------------------*/ /* Download */ /*------------------------------------*/ @@ -1125,40 +978,17 @@ // MAC-S status reporting to Layer 1 #define MACS_STATUS 0 // MAC-S STATUS activated if set to 1 -/* - * Possible choice for dll_dcch_downlink interface (with FN or without FN) - * 0=without, 1=with FN parameter - * - * FreeCalypso note: the Leonardo version had this setting set to 1, i.e., - * 3 arguments to dll_dcch_downlink(). We don't have any source or even - * header files for the Leonardo version of DL, but disassembly shows - * that dll_dcch_downlink() does expect the FN parameter. The source for - * DL from LoCosto also has a SEND_FN_TO_L2_IN_DCCH configurable setting, - * and it is set to 1 in the dl.h local header. But here is the kicker: - * the LoCosto version of this l1_confg.h header has the setting set to 0! - * - * I couldn't believe my eyes, so I disassembled the binary objects present - * in the copy of the LoCosto source from scottn.us: yes, indeed that - * code version contains an outright bug in that L1 does not pass the - * 3rd argument (in ARM register r2), but DL expects it to be there. - * (Thus DL is getting whatever "garbage" happens to be in r2 as the FN - * parameter. I did not take the time to investigate what the downstream - * effects are.) - * - * For FreeCalypso I'm setting SEND_FN_TO_L2_IN_DCCH to 1, both here - * in L1 and in DL, where it was already set. - */ -#define SEND_FN_TO_L2_IN_DCCH 1 -/* - * FreeCalypso change: I'm disabling L1_CHECK_COMPATIBLE (a new "feature" - * added with LoCosto version of L1, not present in the Leonardo version) - * because l1_async.c fails to compile with it enabled. Examination of - * the code reveals that this "compatibility check" involves things - * which we won't be enabling any time soon, if ever. - */ -#define L1_CHECK_COMPATIBLE 0 //Check L1A message compatiblity +// Possible choice for dll_dcch_downlink interface (with FN or without FN) +#define SEND_FN_TO_L2_IN_DCCH 1 /* 0=without, 1=with FN parameter */ //--------------------------------------------------------------------------------- +// Neighbor Cell RXLEV indication +#if ((OP_L1_STANDALONE==1) && (CODE_VERSION == NOT_SIMULATION)) + #define L1_MPHC_RXLEV_IND_REPORT_SORT 1 +#else + #define L1_MPHC_RXLEV_IND_REPORT_SORT 0 +#endif + #endif /* __L1_CONFG_H__ */
--- a/L1/include/l1_const.h Thu Jun 09 00:19:28 2016 +0000 +++ b/L1/include/l1_const.h Thu Jun 09 00:45:00 2016 +0000 @@ -6,8 +6,6 @@ * Copyright 2003 (C) Texas Instruments * ************* Revision Controle System Header *************/ -#ifndef L1_CONST_H -#define L1_CONST_H #ifdef __MSDOS__ // Running BORLANDC compiler. #ifdef MVC @@ -59,7 +57,7 @@ //----------------------------- // POWER MANAGEMENT............ //----------------------------- -#define MIN_SLEEP_TIME (SETUP_FRAME+2+l1_config.params.rf_wakeup_tpu_scenario_duration) //HW WAKE-UP+MIN_SLEEP(2)+AFC RESTORE(rf_wakeup_tpu_scenario_duration) +#define MIN_SLEEP_TIME (SETUP_FRAME+2+l1_config.params.setup_afc_and_rf) //HW WAKE-UP+MIN_SLEEP(2)+AFC RESTORE(2) #define TPU_LOAD 01 #define TPU_FREEZE 02 @@ -75,9 +73,6 @@ #define MAX_BAD_GAUGING 3 // GAUG_IN_32T = (HF in clock of 13Mhz*dpll) * ( LF in Khz) -// Leonardo version had it set to 1348, but TCS3.2 (LoCosto) has it set -// to 605 instead. I'll revert it to the Leonardo value for now. -// -- Space Falcon #define GAUG_IN_32T 1348 // gauging duration is 1348*T32 measured on eva4 // DSP state need to be used to enter Deep Sleep mode @@ -159,6 +154,13 @@ #define TCH_FS_BLEN 378 // TCH FULL SPEECH block length #define TCH_HS_BLEN 211 // TCH HALF SPEECH block length #define TCH_F_D_BLEN 456 // FACCH, TCH_DATA block length + +/* + * FreeCalypso Frankenstein: the following definition was not present in + * our TCS211 version and we had to pull it from the LoCosto version for + * l1_cmplx.c to compile. However, the comment in the place where it is + * used says that it "valuable for code running on target with DSP 3606." + */ #define MIN_ACCEPTABLE_SNR_FOR_SB 200 // threshold under which a SB shall be considered as not found // Define max PM/TDMA according to DSP code and TPU RAM size @@ -173,9 +175,9 @@ #define NB_MEAS_MAX 4 #define NB_MEAS_MAX_GPRS 4 -#elif ((CHIPSET == 5) || (CHIPSET == 6) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 9) || (CHIPSET == 10) || (CHIPSET == 11) || (CHIPSET == 12) || (CHIPSET == 15)) +#elif ((CHIPSET == 5) || (CHIPSET == 6) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 9) || (CHIPSET == 10) || (CHIPSET == 11) || (CHIPSET == 12)) - #if (DSP >= 33) + #if (DSP == 33) || (DSP == 34) || (DSP == 35) || (DSP == 36) // DSP code 33: upto 8 PMs with GSM and GPRS scheduler @@ -217,77 +219,279 @@ //---------------------------------------- // LAYER 1 Asynchronous processes names... //---------------------------------------- -#define NBR_L1A_PROCESSES 63 +#if (TESTMODE) && !(L1_GPRS) + #if (AUDIO_TASK == 1) + #if (L1_GTT) + #if (OP_L1_STANDALONE == 1) + #define NBR_L1A_PROCESSES 45 + #else + #define NBR_L1A_PROCESSES 44 + #endif + #else + #if (OP_L1_STANDALONE == 1) + #define NBR_L1A_PROCESSES 44 + #else + #define NBR_L1A_PROCESSES 43 + #endif + #endif + #else + #if (L1_GTT) + #if (OP_L1_STANDALONE == 1) + #define NBR_L1A_PROCESSES 27 + #else + #define NBR_L1A_PROCESSES 26 + #endif + #else + #if (OP_L1_STANDALONE == 1) + #define NBR_L1A_PROCESSES 26 + #else + #define NBR_L1A_PROCESSES 25 + #endif + #endif +#endif +#endif -#define FULL_MEAS 0 // l1a_full_list_meas_process(msg) -#define CS_NORM 1 // l1a_cs_bcch_process(msg) -#define I_6MP 2 // l1a_idle_6strongest_monitoring_process(msg) -#define I_SCP 3 // l1a_idle_serving_cell_paging_process(msg) -#define I_SCB 4 // l1a_idle_serving_cell_bcch_reading_process(msg) -#define I_SMSCB 5 // l1a_idle_smscb_process(msg) -#define CR_B 6 // l1a_cres_process(msg) -#define ACCESS 7 // l1a_access_process(msg) -#define DEDICATED 8 // l1a_dedicated_process(msg) -#define I_FULL_MEAS 9 // l1a_dedicated_process(msg) -#define I_NMEAS 10 // l1a_idle_ba_meas_process(msg) -#define DEDIC_6 11 // l1a_dedic6_process(msg) -#define D_NMEAS 12 // l1a_dedic_ba_list_meas_process(msg) -#define HW_TEST 13 // l1a_test_process(msg) -#define I_BCCHN 14 // l1a_idle_neighbour_cell_bcch_reading_process(msg) -#define I_ADC 15 // l1a_mmi_adc_req(msg) -#define TMODE_FB0 16 // l1a_tmode_fb0_process(msg) -#define TMODE_FB1 17 // l1a_tmode_fb1_process(msg) -#define TMODE_SB 18 // l1a_tmode_sb_process(msg) -#define TMODE_BCCH 19 // l1a_tmode_bcch_reading_process(msg) -#define TMODE_RA 20 // l1a_tmode_access_process(msg) -#define TMODE_DEDICATED 21 // l1a_tmode_dedicated_process(msg) -#define TMODE_FULL_MEAS 22 // l1a_tmode_full_list_meas_process(msg) -#define TMODE_PM 23 // l1a_tmode_meas_process(msg) -#define TMODE_TRANSFER 24 // l1a_tmode_transfer_process(msg) -#define L1A_KEYBEEP_STATE 25 // l1a_mmi_keybeep_process(msg) -#define L1A_TONE_STATE 26 // l1a_mmi_tone_process(msg) -#define L1A_MELODY0_STATE 27 // l1a_mmi_melody0_process(msg) -#define L1A_MELODY1_STATE 28 // l1a_mmi_melody1_process(msg) -#define L1A_VM_PLAY_STATE 29 // l1a_mmi_vm_playing_process(msg) -#define L1A_VM_RECORD_STATE 30 // l1a_mmi_vm_recording_process(msg) -#define L1A_SR_ENROLL_STATE 31 // l1a_mmi_sr_enroll_process(msg) -#define L1A_SR_UPDATE_STATE 32 // l1a_mmi_sr_update_process(msg) -#define L1A_SR_RECO_STATE 33 // l1a_mmi_sr_reco_process(msg) -#define L1A_SR_UPDATE_CHECK_STATE 34 // l1a_mmi_sr_update_check_process(msg) -#define L1A_AEC_STATE 35 // l1a_mmi_aec_process(msg) -#define L1A_FIR_STATE 36 // l1a_mmi_fir_process(msg) -#define L1A_AUDIO_MODE_STATE 37 // l1a_mmi_audio_mode_process(msg) -#define L1A_MELODY0_E2_STATE 38 // l1a_mmi_melody0_e2_process(msg) -#define L1A_MELODY1_E2_STATE 39 // l1a_mmi_melody1_e2_process(msg) -#define L1A_VM_AMR_PLAY_STATE 40 // l1a_mmi_vm_amr_playing_process(msg) -#define L1A_VM_AMR_RECORD_STATE 41 // l1a_mmi_vm_amr_recording_process(msg) -#define L1A_CPORT_STATE 42 // l1a_mmi_cport_process(msg) -#define L1A_AUDIO_ONOFF_STATE 43 // l1a_mmi_audio_onoff_process(msg) -#define L1A_GTT_STATE 44 // l1a_mmi_gtt_process(msg) -#define INIT_L1 45 // l1a_init_layer1_process(msg) -#define HSW_CONF 46 // l1a_test_config_process(msg) -#define L1A_MP3_STATE 47 // l1a_mmi_mp3_process(msg) -#define TMODE_AUDIO_STEREOPATH_DRV_STATE 48 // l1a_tmode_audio_stereopath_process(msg) -#define L1A_EXT_AUDIO_MGT_STATE 49 // l1a_mmi_ext_audio_mgt_process(msg) -#define L1A_ANR_STATE 50 // l1a_mmi_anr_process(msg) -#define L1A_IIR_STATE 51 // l1a_mmi_iir_process(msg) -#define L1A_LIMITER_STATE 52 // l1a_mmi_limiter_process(msg) -#define L1A_ES_STATE 53 // l1a_mmi_es_process(msg) -#define L1A_MIDI_STATE 54 // l1a_mmi_midi_process(msg) -#define L1A_AGC_UL_STATE 55 // l1a_mmi_agc_ul_process(msg) -#define L1A_AGC_DL_STATE 56 // l1a_mmi_agc_dl_process(msg) -#define L1A_DRC_STATE 57 // l1a_mmi_drc_process(msg) -#define L1A_WCM_STATE 58 // l1a_mmi_wcm_process(msg) -#define L1A_AAC_STATE 59 // l1a_mmi_aac_process(msg) -#if (L1_VOCODER_IF_CHANGE == 1) -#define L1A_VOCODER_CFG_STATE 60 // l1a_mmi_vocoder_cfg_process +#if (TESTMODE) && (L1_GPRS) + #if (AUDIO_TASK == 1) + #if (L1_GTT) + #if (OP_L1_STANDALONE == 1) + #define NBR_L1A_PROCESSES 46 + #else + #define NBR_L1A_PROCESSES 45 + #endif + #else + #if (OP_L1_STANDALONE == 1) + #define NBR_L1A_PROCESSES 45 + #else + #define NBR_L1A_PROCESSES 44 + #endif + #endif + #else + #if (L1_GTT) + #if (OP_L1_STANDALONE == 1) + #define NBR_L1A_PROCESSES 28 + #else + #define NBR_L1A_PROCESSES 27 + #endif + #else + #if (OP_L1_STANDALONE == 1) + #define NBR_L1A_PROCESSES 27 + #else + #define NBR_L1A_PROCESSES 26 + #endif + #endif +#endif #endif -#if (L1_PCM_EXTRACTION) -#define L1A_PCM_DOWNLOAD_STATE 61 -#define L1A_PCM_UPLOAD_STATE 62 + +#if !(TESTMODE) + #if (AUDIO_TASK == 1) + #if (L1_GTT) + #if (OP_L1_STANDALONE == 1) + #define NBR_L1A_PROCESSES 37 + #else + #define NBR_L1A_PROCESSES 36 + #endif + #else + #if (OP_L1_STANDALONE == 1) + #define NBR_L1A_PROCESSES 36 + #else + #define NBR_L1A_PROCESSES 35 + #endif + #endif + #else + #if (L1_GTT) + #if (OP_L1_STANDALONE == 1) + #define NBR_L1A_PROCESSES 19 + #else + #define NBR_L1A_PROCESSES 18 + #endif + #else + #if (OP_L1_STANDALONE == 1) + #define NBR_L1A_PROCESSES 18 + #else + #define NBR_L1A_PROCESSES 17 + #endif + #endif +#endif #endif +#define FULL_MEAS 0 // l1a_full_list_meas_process(msg) +#define CS_NORM 1 // l1a_cs_bcch_process(msg) +#define I_6MP 2 // l1a_idle_6strongest_monitoring_process(msg) +#define I_SCP 3 // l1a_idle_serving_cell_paging_process(msg) +#define I_SCB 4 // l1a_idle_serving_cell_bcch_reading_process(msg) +#define I_SMSCB 5 // l1a_idle_smscb_process(msg) +#define CR_B 6 // l1a_cres_process(msg) +#define ACCESS 7 // l1a_access_process(msg) +#define DEDICATED 8 // l1a_dedicated_process(msg) +#define I_FULL_MEAS 9 // l1a_dedicated_process(msg) +#define I_NMEAS 10 // l1a_idle_ba_meas_process(msg) +#define DEDIC_6 11 // l1a_dedic6_process(msg) +#define D_NMEAS 12 // l1a_dedic_ba_list_meas_process(msg) +#define HW_TEST 13 // l1a_test_process(msg) +#define I_BCCHN 14 // l1a_idle_neighbour_cell_bcch_reading_process(msg) +#define I_ADC 15 // l1a_mmi_adc_req(msg) + +#if (TESTMODE) && !(L1_GPRS) + #define TMODE_FB0 16 // l1a_tmode_fb0_process(msg) + #define TMODE_FB1 17 // l1a_tmode_fb1_process(msg) + #define TMODE_SB 18 // l1a_tmode_sb_process(msg) + #define TMODE_BCCH 19 // l1a_tmode_bcch_reading_process(msg) + #define TMODE_RA 20 // l1a_tmode_access_process(msg) + #define TMODE_DEDICATED 21 // l1a_tmode_dedicated_process(msg) + #define TMODE_FULL_MEAS 22 // l1a_tmode_full_list_meas_process(msg) + #define TMODE_PM 23 // l1a_tmode_meas_process(msg) + #if (AUDIO_TASK == 1) + #define L1A_KEYBEEP_STATE 24 // l1a_mmi_keybeep_process(msg) + #define L1A_TONE_STATE 25 // l1a_mmi_tone_process(msg) + #define L1A_MELODY0_STATE 26 // l1a_mmi_melody0_process(msg) + #define L1A_MELODY1_STATE 27 // l1a_mmi_melody1_process(msg) + #define L1A_VM_PLAY_STATE 28 // l1a_mmi_vm_playing_process(msg) + #define L1A_VM_RECORD_STATE 29 // l1a_mmi_vm_recording_process(msg) + #define L1A_SR_ENROLL_STATE 30 // l1a_mmi_sr_enroll_process(msg) + #define L1A_SR_UPDATE_STATE 31 // l1a_mmi_sr_update_process(msg) + #define L1A_SR_RECO_STATE 32 // l1a_mmi_sr_reco_process(msg) + #define L1A_SR_UPDATE_CHECK_STATE 33 // l1a_mmi_sr_update_check_process(msg) + #define L1A_AEC_STATE 34 // l1a_mmi_aec_process(msg) + #define L1A_FIR_STATE 35 // l1a_mmi_fir_process(msg) + #define L1A_AUDIO_MODE_STATE 36 // l1a_mmi_audio_mode_process(msg) + #define L1A_MELODY0_E2_STATE 37 // l1a_mmi_melody0_e2_process(msg) + #define L1A_MELODY1_E2_STATE 38 // l1a_mmi_melody1_e2_process(msg) + #define L1A_VM_AMR_PLAY_STATE 39 // l1a_mmi_vm_amr_playing_process(msg) + #define L1A_VM_AMR_RECORD_STATE 40 // l1a_mmi_vm_amr_recording_process(msg) + #define L1A_CPORT_STATE 41 // l1a_mmi_cport_process(msg) + #if (L1_GTT == 1) + #define L1A_GTT_STATE 42 // l1a_mmi_gtt_process(msg) + #define INIT_L1 43 // l1a_init_layer1_process(msg) + #if (OP_L1_STANDALONE == 1) + #define HSW_CONF 44 // l1a_test_config_process(msg) + #endif + #else + #define INIT_L1 42 // l1a_init_layer1_process(msg) + #if (OP_L1_STANDALONE == 1) + #define HSW_CONF 43 // l1a_test_config_process(msg) + #endif + #endif + #else + #if (L1_GTT == 1) + #define L1A_GTT_STATE 24 // l1a_mmi_gtt_process(msg) + #define INIT_L1 25 // l1a_init_layer1_process(msg) + #if (OP_L1_STANDALONE == 1) + #define HSW_CONF 26 // l1a_test_config_process(msg) + #endif + #else + #define INIT_L1 24 // l1a_init_layer1_process(msg) + #if (OP_L1_STANDALONE == 1) + #define HSW_CONF 25 // l1a_test_config_process(msg) + #endif + #endif + #endif +#endif + +#if (TESTMODE) && (L1_GPRS) + #define TMODE_FB0 16 // l1a_tmode_fb0_process(msg) + #define TMODE_FB1 17 // l1a_tmode_fb1_process(msg) + #define TMODE_SB 18 // l1a_tmode_sb_process(msg) + #define TMODE_BCCH 19 // l1a_tmode_bcch_reading_process(msg) + #define TMODE_RA 20 // l1a_tmode_access_process(msg) + #define TMODE_DEDICATED 21 // l1a_tmode_dedicated_process(msg) + #define TMODE_FULL_MEAS 22 // l1a_tmode_full_list_meas_process(msg) + #define TMODE_PM 23 // l1a_tmode_meas_process(msg) + #define TMODE_TRANSFER 24 // l1a_tmode_transfer_process(msg) + #if (AUDIO_TASK == 1) + #define L1A_KEYBEEP_STATE 25 // l1a_mmi_keybeep_process(msg) + #define L1A_TONE_STATE 26 // l1a_mmi_tone_process(msg) + #define L1A_MELODY0_STATE 27 // l1a_mmi_melody0_process(msg) + #define L1A_MELODY1_STATE 28 // l1a_mmi_melody1_process(msg) + #define L1A_VM_PLAY_STATE 29 // l1a_mmi_vm_playing_process(msg) + #define L1A_VM_RECORD_STATE 30 // l1a_mmi_vm_recording_process(msg) + #define L1A_SR_ENROLL_STATE 31 // l1a_mmi_sr_enroll_process(msg) + #define L1A_SR_UPDATE_STATE 32 // l1a_mmi_sr_update_process(msg) + #define L1A_SR_RECO_STATE 33 // l1a_mmi_sr_reco_process(msg) + #define L1A_SR_UPDATE_CHECK_STATE 34 // l1a_mmi_sr_update_check_process(msg) + #define L1A_AEC_STATE 35 // l1a_mmi_aec_process(msg) + #define L1A_FIR_STATE 36 // l1a_mmi_fir_process(msg) + #define L1A_AUDIO_MODE_STATE 37 // l1a_mmi_audio_mode_process(msg) + #define L1A_MELODY0_E2_STATE 38 // l1a_mmi_melody0_e2_process(msg) + #define L1A_MELODY1_E2_STATE 39 // l1a_mmi_melody1_e2_process(msg) + #define L1A_VM_AMR_PLAY_STATE 40 // l1a_mmi_vm_amr_playing_process(msg) + #define L1A_VM_AMR_RECORD_STATE 41 // l1a_mmi_vm_amr_recording_process(msg) + #define L1A_CPORT_STATE 42 // l1a_mmi_cport_process(msg) + #if (L1_GTT == 1) + #define L1A_GTT_STATE 43 + #define INIT_L1 44 // l1a_init_layer1_process(msg) + #if (OP_L1_STANDALONE == 1) + #define HSW_CONF 45 // l1a_test_config_process(msg) + #endif + #else + #define INIT_L1 43 // l1a_init_layer1_process(msg) + #if (OP_L1_STANDALONE == 1) + #define HSW_CONF 44 // l1a_test_config_process(msg) + #endif + #endif + #else + #if (L1_GTT == 1) + #define L1A_GTT_STATE 25 + #define INIT_L1 26 // l1a_init_layer1_process(msg) + #if (OP_L1_STANDALONE == 1) + #define HSW_CONF 27 // l1a_test_config_process(msg) + #endif + #else + #define INIT_L1 25 // l1a_init_layer1_process(msg) + #if (OP_L1_STANDALONE == 1) + #define HSW_CONF 26 // l1a_test_config_process(msg) + #endif + #endif + #endif +#endif + +#if !(TESTMODE) && (AUDIO_TASK == 1) + #define L1A_KEYBEEP_STATE 16 // l1a_mmi_keybeep_process(msg) + #define L1A_TONE_STATE 17 // l1a_mmi_tone_process(msg) + #define L1A_MELODY0_STATE 18 // l1a_mmi_melody0_process(msg) + #define L1A_MELODY1_STATE 19 // l1a_mmi_melody1_process(msg) + #define L1A_VM_PLAY_STATE 20 // l1a_mmi_vm_playing_process(msg) + #define L1A_VM_RECORD_STATE 21 // l1a_mmi_vm_recording_process(msg) + #define L1A_SR_ENROLL_STATE 22 // l1a_mmi_sr_enroll_process(msg) + #define L1A_SR_UPDATE_STATE 23 // l1a_mmi_sr_update_process(msg) + #define L1A_SR_RECO_STATE 24 // l1a_mmi_sr_reco_process(msg) + #define L1A_SR_UPDATE_CHECK_STATE 25 // l1a_mmi_sr_update_check_process(msg) + #define L1A_AEC_STATE 26 // l1a_mmi_aec_process(msg) + #define L1A_FIR_STATE 27 // l1a_mmi_fir_process(msg) + #define L1A_AUDIO_MODE_STATE 28 // l1a_mmi_audio_mode_process(msg) + #define L1A_MELODY0_E2_STATE 29 // l1a_mmi_melody0_e2_process(msg) + #define L1A_MELODY1_E2_STATE 30 // l1a_mmi_melody1_e2_process(msg) + #define L1A_VM_AMR_PLAY_STATE 31 // l1a_mmi_vm_amr_playing_process(msg) + #define L1A_VM_AMR_RECORD_STATE 32 // l1a_mmi_vm_amr_recording_process(msg) + #define L1A_CPORT_STATE 33 // l1a_mmi_cport_process(msg) + #if (L1_GTT == 1) + #define L1A_GTT_STATE 34 // l1a_mmi_tty_process(msg) + #define INIT_L1 35 // l1a_init_layer1_process(msg) + #if (OP_L1_STANDALONE == 1) + #define HSW_CONF 36 // l1a_test_config_process(msg) + #endif + #else + #define INIT_L1 34 // l1a_init_layer1_process(msg) + #if (OP_L1_STANDALONE == 1) + #define HSW_CONF 35 // l1a_test_config_process(msg) + #endif + #endif +#elif !(TESTMODE) && !(AUDIO_TASK == 1) + #if (L1_GTT == 1) + #define L1A_GTT_STATE 16 // l1a_mmi_tty_process(msg) + #define INIT_L1 17 // l1a_init_layer1_process(msg) + #if (OP_L1_STANDALONE == 1) + #define HSW_CONF 18 // l1a_test_config_process(msg) + #endif + #else + #define INIT_L1 16 // l1a_init_layer1_process(msg) + #if (OP_L1_STANDALONE == 1) + #define HSW_CONF 17 // l1a_test_config_process(msg) + #endif + #endif +#endif + #if TESTMODE #define TMODE_UPLINK (1<<0) #define TMODE_DOWNLINK (1<<1) @@ -307,18 +511,9 @@ // Tasks in the order of their priority (low to high). -#if (GSM_IDLE_RAM != 0) - #define INT_RAM_GSM_IDLE_L1S_PROCESSES1 0x00000618 // PNP, PEP, NP, EP only are supported -#endif - - #if !L1_GPRS -#if ((REL99 == 1) && (FF_BHO == 1)) - #define NBR_DL_L1S_TASKS 33 -#else //#if ((REL99 == 1) && (FF_BHO == 1)) #define NBR_DL_L1S_TASKS 32 -#endif //#if ((REL99 == 1) && (FF_BHO == 1)) //GSM_TASKS/ #define HWTEST 0 // DSP checksum reading @@ -352,25 +547,13 @@ #define TCHTF 28 // TCH Full rate #define TCHTH 29 // TCH Half rate #define BCCHN_TOP 30 // BCCH Neighbour TOP priority in Idle mode -#if ((REL99 == 1) && (FF_BHO == 1)) - #define FBSB 31 // Freq + Synchro Burst Reading in Blind Handover - #define SYNCHRO 32 // synchro task: L1S reset -#else //#if ((REL99 == 1) && (FF_BHO == 1)) #define SYNCHRO 31 // synchro task: L1S reset -#endif //#if ((REL99 == 1) && (FF_BHO == 1)) //END_GSM_TASKS/ #else -#if ((REL99 == 1) && (FF_BHO == 1)) - #define NBR_DL_L1S_TASKS 46 -#else //#if ((REL99 == 1) && (FF_BHO == 1)) #define NBR_DL_L1S_TASKS 45 -#endif //#if ((REL99 == 1) && (FF_BHO == 1)) -#if (FF_REPEATED_SACCH == 1 ) - #define REPEATED_SACCH_ENABLE 1 -#endif /* FF_REPEATED_SACCH */ //GPRS_TASKS/ #define HWTEST 0 // DSP checksum reading #define ADC_CSMODE0 1 // ADC task in CS_MODE0 mode @@ -382,7 +565,7 @@ #define PRACH 7 // Packet Random Access Channel #define ITMEAS 8 // Interference measurements #define FBNEW 9 // Frequency burst search (Idle mode) - #define SBCONF 10 // Synchro. burst confirmation + #define SBCONF 10 // Synchro. burst confirmation #define SB2 11 // Synchro. burst read (1 frame uncertainty / SB position) #define PTCCH 12 // Packet Timing Advance control channel #define FB26 13 // Frequency burst search, dedic/transfer mode MF26 or MF52 @@ -416,20 +599,11 @@ #define NP 41 // Normal paging Reading #define EP 42 // Extended paging Reading #define BCCHN_TOP 43 // BCCH Neighbour TOP priority in Idle mode -#if ((REL99 == 1) && (FF_BHO == 1)) - #define FBSB 44 // Freq + Synchro Burst Reading in Blind Handover - #define SYNCHRO 45 // synchro task: L1S reset -#else //#if ((REL99 == 1) && (FF_BHO == 1)) #define SYNCHRO 44 // synchro task: L1S reset -#endif //#if ((REL99 == 1) && (FF_BHO == 1)) //END_GPRS_TASKS/ #endif -#if (GSM_IDLE_RAM != 0) - #define SIZE_TAB_L1S_MONITOR (((NBR_DL_L1S_TASKS-1) >> 5) + 1) -#endif - //------------------------------------ // LAYER 1 API //------------------------------------ @@ -437,42 +611,27 @@ #define MCSI_PORT2 1 -#if (W_A_DSP_PR20037 == 1) - //--------------------------------- - // DSP vocoder Enable/ Disable - //--------------------------------- - #if (FF_L1_TCH_VOCODER_CONTROL == 1) - #if (L1_VOCODER_IF_CHANGE == 0) - #define TCH_VOCODER_DISABLE_REQ 0 - #define TCH_VOCODER_ENABLE_REQ 1 - #define TCH_VOCODER_ENABLED 2 - #define TCH_VOCODER_DISABLED 3 - #else - #define TCH_VOCODER_RESET_COMMAND 0 - #define TCH_VOCODER_ENABLE_COMMAND 1 - #define TCH_VOCODER_DISABLE_COMMAND 2 - #endif // L1_VOCODER_IF_CHANGE == 0 +//--------------------------------- +// DSP vocoder Enable/ Disable +//--------------------------------- - #if (W_A_WAIT_DSP_RESTART_AFTER_VOCODER_ENABLE ==1) - // Number of TDMA wait frames until the DSP output is steady - #define DSP_VOCODER_ON_TRANSITION 165 - #endif - #endif // FF_L1_TCH_VOCODER_CONTROL -#endif // W_A_DSP_PR20037 +#if (L1M_WAIT_DSP_RESTART_AFTER_VOCODER_ENABLE ==1) + #if (FF_L1_TCH_VOCODER_CONTROL == 1) + #define TCH_VOCODER_DISABLE_REQ 0 + #define TCH_VOCODER_ENABLE_REQ 1 + #define TCH_VOCODER_ENABLED 2 + #define TCH_VOCODER_DISABLED 3 + // Number of TDMA wait frames until the DSP output is steady + #define DSP_VOCODER_ON_TRANSITION 165 + #endif // FF_L1_TCH_VOCODER_CONTROL +#endif //--------------------------------- // Handover Finished cause defines. //--------------------------------- #define HO_COMPLETE 0 #define HO_TIMEOUT 1 -#if ((REL99 == 1) && (FF_BHO == 1)) - #define HO_FB_FAIL 2 - #define HO_SB_FAIL 3 - - #define NORMAL_HANDOVER 0 - #define BLIND_HANDOVER 1 -#endif //--------------------------------- // FB detection algorithm defines. @@ -481,13 +640,6 @@ #define FB_MODE_1 1 // FB detec. mode 1. //--------------------------------- -// SB acquisition phase. -//--------------------------------- -#if ((REL99 == 1) && ((FF_BHO == 1) || (FF_RTD == 1))) - #define SB_ACQUISITION_PHASE 5 -#endif - -//--------------------------------- // AFC control defines. //--------------------------------- #define AFC_INIT 1 @@ -500,31 +652,11 @@ #define AFC_INIT_MAX 5 #define AFC_INIT_MIN 6 #endif - -#if 0 -// For Locosto -#define L1_AFC_MANUAL_MODE 0 -#define L1_AFC_SCRIPT_MODE 1 -#define L1_AFC_NONE 2 - -#define L1_CTL_ZERO_IF 2 -#define L1_CTL_LOW_IF 1 - -#define L1_IL_INVALID 0 -#define L1_IL_VALID 1 - -// End Locosto -#endif - //--------------------------------- // TOA control defines. //--------------------------------- #define TOA_INIT 1 #define TOA_RUN 2 -#if (TOA_ALGO == 2) - // In this version TOA is refreshed every 2 seconds - #define L1_TOA_UPDATE_TIME ((UWORD32)(433)) -#endif //--------------------------------- // Neighbour Synchro possible status. @@ -545,20 +677,10 @@ #define MAX_BLOCK_ID ((UWORD32) (3 * (UWORD32) (MAX_FN / 13))) // Block ID corresponding to fn = FN MAX #endif -#if FF_L1_IT_DSP_DTX - // dtx_status states - #define DTX_AVAILABLE 0 - #define DTX_AWAITED 1 - #define DTX_IT_DSP 2 - - // Latency time for Fast DTX availability upon channel start (TDMAs) - #define FAST_DTX_LATENCY 10 //chaged from value-4 -CQ- 74387 -#endif - //-------------------------------------------------------- // standard specific constants used in l1_config.std.xxx //-------------------------------------------------------- -#if (L1_FF_MULTIBAND == 0) + // GSM #define FIRST_ARFCN_GSM 1 // 1st arfcn is 1 @@ -604,385 +726,6 @@ #define BAND1 1 #define BAND2 2 -#else // L1_FF_MULTIBAND == 1 below - -/***** GSM Band Identifiers to be communicated to the L3, these indexes are fixed *****************/ -#define PGSM900 0 -#define GSM850 1 -#define PCS1900 2 -#define DCS1800 3 -#define GSM750 4 -#define GSM480 5 -#define GSM450 6 -#define T_GSM380 7 -#define T_GSM410 8 -#define T_GSM900 9 -#define EGSM900 10 -#define RGSM900 11 - -/***** PGSM900, EGSM900 and RGSM900 are seen a single band GSM900 **********************************/ -#define GSM900 12 - -/***** The total number of bands specified in the 3GPP Specs ***************************************/ -#define NB_MAX_GSM_BANDS 12 - -#if 0 -/********************************* Physical_band_ids to be supported Definition *******************/ -#define RGSM900_SUPPORTED 0 -#define EGSM900_SUPPORTED 1 -#define PGSM900_SUPPORTED 0 -#define GSM850_SUPPORTED 1 -#define PCS1900_SUPPORTED 1 -#define DCS1800_SUPPORTED 1 -#define GSM750_SUPPORTED 0 -#define GSM710_SUPPORTED 0 -#define GSM480_SUPPORTED 0 -#define T_GSM380_SUPPORTED 0 -#define T_GSM410_SUPPORTED 0 -#define GSM450_SUPPORTED 0 -#define T_GSM900_SUPPORTED 0 - -/***** Bands to be supported Eror Cases ******************************************/ - -#if (RGSM900_SUPPORTED + EGSM900_SUPPORTED + PGSM900_SUPPORTED > 1) -#error " Only one of the RGSM900 or EGSM900 or PGSM900 bands is supported" -#endif/*if(RGSM900_SUPPORTED + EGSM900_SUPPORTED + PGSM900_SUPPORTED > 1)*/ - - -/***** GSM900_SUPPORTED means one of P, E or R GSM900 is supported ***/ -#if ((PGSM900_SUPPORTED == 1) || (EGSM900_SUPPORTED == 1) || (RGSM900_SUPPORTED == 1)) -#define GSM900_SUPPORTED 1 -#endif - -#endif // if 0 - -/***** Number of Physical Bands Supported by the L1 Calculation, this constant is less than NB_MAX_GSM_BANDS**********/ -#define NB_MAX_SUPPORTED_BANDS (GSM900_SUPPORTED +\ - GSM850_SUPPORTED + \ - PCS1900_SUPPORTED + \ - DCS1800_SUPPORTED + \ - GSM750_SUPPORTED + \ - GSM480_SUPPORTED + \ - GSM450_SUPPORTED + \ - T_GSM410_SUPPORTED + \ - T_GSM380_SUPPORTED + \ - T_GSM900_SUPPORTED) - -/***** - EGSM and RGSM have two separate ranges of ARFCN's that are considered by L1 as - separate bands. Hence number of supported bands is one more if E or R GSM900 is - supported. -*****/ -#if (PGSM900_SUPPORTED == 1)// This means E or R GSM900 is not supported -#define NB_MAX_EFFECTIVE_SUPPORTED_BANDS NB_MAX_SUPPORTED_BANDS -#endif - -#if ((EGSM900_SUPPORTED == 1) || (RGSM900_SUPPORTED == 1)) -#define NB_MAX_EFFECTIVE_SUPPORTED_BANDS (NB_MAX_SUPPORTED_BANDS + 1) -#endif - -#if 0 -/*The following constants allows the indexing of the physical bands in the MULTIBAND rf table located in l1_cust.c*/ -/*The bands positionning order is related to the bands ENUMERATION here below*/ -/*Changing the bands positions in this table implies changing the the band ENUMERATION in the file l1_const.h*/ -/*Changing the the band ENUMERATION in the file l1_const.h implies changing the bands positions in the table below*/ -enum -{ -#if (GSM900_SUPPORTED == 1) - GSM900_ID, -#endif /*if (GSM900_SUPPORTED == 1)*/ - -#if (GSM850_SUPPORTED == 1) - GSM850_ID, -#endif /*if (GSM850_SUPPORTED == 1)*/ - -#if (DCS1800_SUPPORTED == 1) - DCS1800_ID, -#endif /*if (DCS1800_SUPPORTED == 1)*/ - -#if (PCS1900_SUPPORTED == 1) - PCS1900_ID, -#endif /*if (PCS1900_SUPPORTED == 1)*/ - -#if (GSM750_SUPPORTED == 1) - GSM750_ID, -#endif /*if (GSM750_SUPPORTED == 1)*/ - -#if (GSM480_SUPPORTED == 1) - GSM480_ID, -#endif /*if (GSM480_SUPPORTED == 1)*/ - -#if GSM450_SUPPORTED - GSM450_ID, -#endif /*if (GSM450_SUPPORTED == 1)*/ - -#if (T_GSM410_SUPPORTED == 1) - T_GSM410_ID, -#endif /*if (T_GSM410_SUPPORTED == 1)*/ - -#if (T_GSM380_SUPPORTED == 1) - T_GSM380_ID, -#endif /*if (T_GSM380_SUPPORTED == 1)*/ - -#if (T_GSM900_SUPPORTED == 1) - T_GSM900_ID, -#endif /*if (T_GSM900_SUPPORTED == 1)*/ -}; -#endif -/***********************************Calculation of the number of carriers per Effective Band*********/ -#if 0 - -#if (PGSM900_SUPPORTED == 1) -#define NB_CARRIER_900_LOW_SUB_BAND 124 -#define NB_CARRIER_900_HIGH_SUB_BAND 0 -#endif /*if (PGSM900_SUPPORTED == 1)*/ - -#if (EGSM900_SUPPORTED == 1) -#define NB_CARRIER_900_LOW_SUB_BAND 125 -#define NB_CARRIER_900_HIGH_SUB_BAND 49 -#endif /*if (EGSM900_SUPPORTED == 1)*/ - -#if (RGSM900_SUPPORTED == 1) -#define NB_CARRIER_900_LOW_SUB_BAND 125 -#define NB_CARRIER_900_HIGH_SUB_BAND 69 -#endif /*if (RGSM900_SUPPORTED == 1)*/ - -#define NB_CARRIER_850 124 -#define NB_CARRIER_1800 344 -#define NB_CARRIER_1900 299 -#define NB_CARRIER_750 74 -#define NB_CARRIER_480 35 -#define NB_CARRIER_450 35 -#define NB_CARRIER_T_410 47 -#define NB_CARRIER_T_380 47 -#define NB_CARRIER_T_900 27 - -/****** NBMAX_CARRIER is the total number of carriers supported based on band support *********/ - -#define NBMAX_CARRIER (((NB_CARRIER_900_LOW_SUB_BAND + NB_CARRIER_900_HIGH_SUB_BAND) * GSM900_SUPPORTED) \ - + (NB_CARRIER_850 * GSM850_SUPPORTED) \ - + (NB_CARRIER_1800 * DCS1800_SUPPORTED)\ - + (NB_CARRIER_1900 * PCS1900_SUPPORTED) \ - + (NB_CARRIER_750 * GSM750_SUPPORTED) \ - + (NB_CARRIER_480 * GSM480_SUPPORTED) \ - + (NB_CARRIER_450 * GSM450_SUPPORTED) \ - + (NB_CARRIER_T_410 * T_GSM410_SUPPORTED) \ - + (NB_CARRIER_T_380 * T_GSM380_SUPPORTED) \ - + (NB_CARRIER_T_900 * T_GSM900_SUPPORTED)) - - -/** - The multiband frequency numbers exchanged across L3-L1 I/F are the 3GPP ARFCN numbers - with exceptiopn of 1900 where the numbers start from 1024 onwards. This results in - holes in the numbering given from L3 and hence cannot be used for indexing arrays of - carriers. To index arrays the frequency numbers from L3 are translated to 'operative radio - frequencies'. For any band configuration supported, this is a continuos number from - 0 to NBMAX_CARRIER (The sum of number of carriers in all supported bands) - The defines below are for finding the first operative frequency corresponding to each band -**/ - -#define FIRST_OPERATIVE_RADIO_FREQ_900_LOW_SUB_BAND 0 -#define FIRST_OPERATIVE_RADIO_FREQ_900_HIGH_SUB_BAND (FIRST_OPERATIVE_RADIO_FREQ_900_LOW_SUB_BAND + NB_CARRIER_900_LOW_SUB_BAND) * GSM900_SUPPORTED -#define FIRST_OPERATIVE_RADIO_FREQ_850 (FIRST_OPERATIVE_RADIO_FREQ_900_HIGH_SUB_BAND + NB_CARRIER_900_HIGH_SUB_BAND) * GSM850_SUPPORTED -#define FIRST_OPERATIVE_RADIO_FREQ_1900 (FIRST_OPERATIVE_RADIO_FREQ_850 + NB_CARRIER_850) * PCS1900_SUPPORTED -#define FIRST_OPERATIVE_RADIO_FREQ_1800 (FIRST_OPERATIVE_RADIO_FREQ_1900 + NB_CARRIER_1900) * DCS1800_SUPPORTED -#define FIRST_OPERATIVE_RADIO_FREQ_750 (FIRST_OPERATIVE_RADIO_FREQ_1800 + NB_CARRIER_1800) * GSM750_SUPPORTED -#define FIRST_OPERATIVE_RADIO_FREQ_480 (FIRST_OPERATIVE_RADIO_FREQ_750 + NB_CARRIER_750) * GSM480_SUPPORTED -#define FIRST_OPERATIVE_RADIO_FREQ_450 (FIRST_OPERATIVE_RADIO_FREQ_480 + NB_CARRIER_480) * GSM450_SUPPORTED -#define FIRST_OPERATIVE_RADIO_FREQ_T_410 (FIRST_OPERATIVE_RADIO_FREQ_450 + NB_CARRIER_450) * T_GSM410_SUPPORTED -#define FIRST_OPERATIVE_RADIO_FREQ_T_380 (FIRST_OPERATIVE_RADIO_FREQ_T_410 + NB_CARRIER_T_410) * T_GSM380_SUPPORTED -#define FIRST_OPERATIVE_RADIO_FREQ_T_900 (FIRST_OPERATIVE_RADIO_FREQ_T_380 + NB_CARRIER_T_380) * T_GSM900_SUPPORTED - -/********************** Definition of the first radio freqs as per L3-L1 interface *********/ - -#if (PGSM900_SUPPORTED == 1) -#define FIRST_RADIO_FREQ_900_LOW_SUB_BAND 1 -#define FIRST_RADIO_FREQ_900_HIGH_SUB_BAND 0 -#endif /*if (PGSM900_SUPPORTED == 1)*/ - -#if (EGSM900_SUPPORTED == 1) -#define FIRST_RADIO_FREQ_900_LOW_SUB_BAND 0 -#define FIRST_RADIO_FREQ_900_HIGH_SUB_BAND 975 -#endif /*if (EGSM900_SUPPORTED == 1)*/ - -#if (RGSM900_SUPPORTED == 1) -#define FIRST_RADIO_FREQ_900_LOW_SUB_BAND 0 -#define FIRST_RADIO_FREQ_900_HIGH_SUB_BAND 955 -#endif /* (RGSM900_SUPPORTED == 1)*/ - -#define FIRST_RADIO_FREQ_850 128 -#define FIRST_RADIO_FREQ_1800 512 -#define FIRST_RADIO_FREQ_1900 1024 -#define FIRST_TPU_RADIO_FREQ_1900 512 /* TBD The GSM1900 is the unique band in which the FIRST_TPU_RADIO is not equal to FIRST_RADIO_FREQ*/ - -#endif // if 0 - -#endif // L1_FF_MULTIBAND == 0 - -#if (L1_FF_MULTIBAND == 0) -#else -/* Prototypes */ - -#define l1_multiband_radio_freq_convert_into_effective_band_id(radio_freq) \ - rf_convert_rffreq_to_l1subband(radio_freq) - -#define l1_multiband_radio_freq_convert_into_physical_band_id(radio_freq) \ -((UWORD8)rf_convert_l1freq_to_rf_band_idx(rf_convert_rffreq_to_l1freq(radio_freq))) - -#define l1_multiband_radio_freq_convert_into_operative_radio_freq(radio_freq) \ - rf_convert_rffreq_to_l1freq(radio_freq) - -#if (CODE_VERSION != SIMULATION) -UWORD8 rf_convert_rffreq_to_l1subband(UWORD16 rf_freq); -UWORD8 rf_convert_l1freq_to_l1subband(UWORD16 l1_freq); -WORD8 rf_convert_l1freq_to_rf_band_idx(UWORD16 l1_freq); -UWORD16 rf_convert_l1freq_to_rffreq(UWORD16 l1_freq ); -UWORD16 rf_convert_l1freq_to_rffreq_rfband(UWORD16 l1_freq, WORD8 *rf_band_index); -UWORD16 rf_convert_l1freq_to_arfcn_rfband(UWORD16 l1_freq, WORD8 *rf_band_index); -UWORD16 rf_convert_rffreq_to_l1freq(UWORD16 rf_freq); -UWORD16 rf_convert_rffreq_to_l1freq_rfband(UWORD16 rf_freq, WORD8 *rf_band_index); -UWORD16 rf_convert_tmarfcn_to_l1freq(UWORD16 tm_arfcn, WORD8 * error_flag); -#endif - -/* RF defines */ -/******************************Physical_band_ids to be supported Definition****************************************/ -#define RGSM900_SUPPORTED 0 -#define PGSM900_SUPPORTED 0 -#define GSM750_SUPPORTED 0 -#define GSM710_SUPPORTED 0 -#define GSM480_SUPPORTED 0 -#define T_GSM380_SUPPORTED 0 -#define T_GSM410_SUPPORTED 0 -#define GSM450_SUPPORTED 0 -#define T_GSM900_SUPPORTED 0 -#if 0 -#if (RF_BAND_SYSTEM_INDEX == RF_DCS1800_850_DUALBAND) -#define GSM900_SUPPORTED 0 -#define GSM850_SUPPORTED 1 -#define PCS1900_SUPPORTED 0 -#define DCS1800_SUPPORTED 1 -#elif (RF_BAND_SYSTEM_INDEX == RF_PCS1900_900_DUALBAND) -#define GSM900_SUPPORTED 1 -#define GSM850_SUPPORTED 0 -#define PCS1900_SUPPORTED 1 -#define DCS1800_SUPPORTED 0 -#elif (RF_BAND_SYSTEM_INDEX == RF_US_DUALBAND) -#define GSM900_SUPPORTED 0 -#define GSM850_SUPPORTED 1 -#define PCS1900_SUPPORTED 1 -#define DCS1800_SUPPORTED 0 -#elif (RF_BAND_SYSTEM_INDEX == RF_US_TRIBAND) -#define GSM900_SUPPORTED 0 -#define GSM850_SUPPORTED 1 -#define PCS1900_SUPPORTED 1 -#define DCS1800_SUPPORTED 1 -#elif (RF_BAND_SYSTEM_INDEX == RF_EU_DUALBAND) -#define GSM900_SUPPORTED 1 -#define GSM850_SUPPORTED 0 -#define PCS1900_SUPPORTED 0 -#define DCS1800_SUPPORTED 1 -#elif (RF_BAND_SYSTEM_INDEX == RF_EU_TRIBAND) -#define GSM900_SUPPORTED 1 -#define GSM850_SUPPORTED 0 -#define PCS1900_SUPPORTED 1 -#define DCS1800_SUPPORTED 1 -#elif (RF_BAND_SYSTEM_INDEX == RF_QUADBAND) -#define GSM900_SUPPORTED 1 -#define GSM850_SUPPORTED 1 -#define PCS1900_SUPPORTED 1 -#define DCS1800_SUPPORTED 1 -#endif -#endif // if 0 TBD -#define GSM900_SUPPORTED 1 -#define GSM850_SUPPORTED 1 -#define PCS1900_SUPPORTED 1 -#define DCS1800_SUPPORTED 1 - -/* The physical RF bands are enumerated in order of increasing frequencies */ -/* The same order must be used in l1_rf61, l1_cust, and l1_const */ -enum -{ -#if (GSM900_SUPPORTED == 1) - RF_GSM900, -#endif -#if (GSM850_SUPPORTED == 1) - RF_GSM850, -#endif -#if (DCS1800_SUPPORTED == 1) - RF_DCS1800, -#endif -#if (PCS1900_SUPPORTED == 1) - RF_PCS1900, -#endif - RF_NB_SUPPORTED_BANDS /* The number of supported physical bands */ -}; - -#if GSM900_SUPPORTED -#define RF_NB_SUBBANDS (RF_NB_SUPPORTED_BANDS + 1) -#else -#define RF_NB_SUBBANDS (RF_NB_SUPPORTED_BANDS) -#endif - -/***********************************Calculation of the number of carriers per Effective Band*********/ -#define NB_CHAN_900L 125 -#define NB_CHAN_900H 49 -#define NB_CHAN_850 124 -#define NB_CHAN_1800 374 -#define NB_CHAN_1900 299 - -/** - The multiband frequency numbers exchanged across L3-L1 I/F are the 3GPP ARFCN numbers - except for DCS1900 where the numbers start from 1024 onwards, i.e. ARFCN+512. - L1 cannot have holes in the numbering, so a different L1 internal one is needed to build arrays in L1. - This numbering is similar to ARFCN numbering, except the high part of GSM900 channel numbers - are mapped between low part of GSM900 numbers and the GSM850 numbers. - For any band configuration supported, this is a continuos number from - 0 to NB_CARRIERS (The sum of number of carriers in all supported bands) -**/ -/****** L1_NB_CARRIER is the total number of carriers supported based on band support *********/ -#define L1_FREQ_1ST_900L 0 -#define L1_FREQ_1ST_900H (L1_FREQ_1ST_900L + NB_CHAN_900L * GSM900_SUPPORTED) -#define L1_FREQ_1ST_850 (L1_FREQ_1ST_900H + NB_CHAN_900H * GSM900_SUPPORTED) -#define L1_FREQ_1ST_1800 (L1_FREQ_1ST_850 + NB_CHAN_850 * GSM850_SUPPORTED) -#define L1_FREQ_1ST_1900 (L1_FREQ_1ST_1800 + NB_CHAN_1800 * DCS1800_SUPPORTED) -#define NBMAX_CARRIER (L1_FREQ_1ST_1900 + NB_CHAN_1900 * PCS1900_SUPPORTED) - -#define ARFCN_1ST_900L 0 -#define ARFCN_1ST_900H 975 -#define ARFCN_1ST_850 128 -#define ARFCN_1ST_1800 512 -#define ARFCN_1ST_1900 512 - -#define RF_FREQ_1ST_900L ARFCN_1ST_900L -#define RF_FREQ_1ST_900H ARFCN_1ST_900H -#define RF_FREQ_1ST_850 ARFCN_1ST_850 -#define RF_FREQ_1ST_1800 ARFCN_1ST_1800 -#define RF_FREQ_1ST_1900 (ARFCN_1ST_1900 + 512) - - -typedef struct -{ - UWORD16 first_rf_freq; - UWORD16 last_rf_freq; - UWORD16 first_l1_freq; - WORD16 l1freq2rffreq; -} -T_MULTIBAND_CONVERT; - -typedef struct -{ - UWORD8 power_class; - UWORD8 tx_turning_point; - UWORD8 max_txpwr; - UWORD8 gsm_band_identifier; - char* name; -} -T_MULTIBAND_RF; - -#endif /*if (L1_FF_MULTIBAND == 1)*/ - - - #define NO_TXPWR 255 // sentinal value used with UWORD8 type. @@ -992,6 +735,13 @@ #define RXLEV63 63 // max value for RXLEV. #define IL_MIN 240 // minimum input level is -120 dbm. +//-------------------------------------------------------- +// Max number of cell to report in MPHC_RXLEV_IND. +// Nb cells to check to see if cell of MPHC_NETWORK_SYNC_REQ has been detected +//-------------------------------------------------------- +#define MAX_MEAS_RXLEV_IND_TRACE 10 +#define NB_FQ_TO_CHK 4 + /*--------------------------------------------------------*/ /* Max value for GSM Paging Parameters. */ /*--------------------------------------------------------*/ @@ -1049,15 +799,6 @@ #define CBCH_TB6 0x0010 #define CBCH_TB7 0x0020 -#if FF_TBF -/*--------------------------------------------------------*/ -/* Access burst types on the RACH/PRACH */ -/*--------------------------------------------------------*/ - #define ACC_BURST_8 0 - #define ACC_BURST_11 1 - #define ACC_BURST_11_TS1 2 - #define ACC_BURST_11_TS2 3 -#endif #define CBCH_CONTINUOUS_READING 0 #define CBCH_SCHEDULED 1 #define CBCH_INACTIVE 2 @@ -1104,11 +845,11 @@ #define DEDIC_MODE 5 // functional mode in DEDICATED. #define DEDIC_MODE_HALF_DATA 6 // used only for TOA histogram length purpose. #if L1_GPRS - #define PACKET_TRANSFER_MODE 7 // + #define PACKET_TRANSFER_MODE 7 #endif /*--------------------------------------------------------*/ -/* Error causes for MPHC_NO_BCCH message. */ +/* Error causes for MPHC_NO_BCCH message. */ /*--------------------------------------------------------*/ #define NO_FB_SB 0 // FB or SB not found. #define NCC_NOT_PERMITTED 1 // Synchro OK! but PLMN not permitted. @@ -1137,9 +878,7 @@ #define CTRL_PRACH (TRUE_L << 10) #define CTRL_SYSINGLE (TRUE_L << 11) #endif -#if ((REL99 == 1) && (FF_BHO == 1)) -#define CTRL_FBSB_ABORT (TRUE_L << 12) -#endif + /********************************/ /* MISC management */ @@ -1252,9 +991,6 @@ #define SB_DSP_TASK 6 // Sync. Burst reading task in Idle mode. #define TCH_FB_DSP_TASK 8 // Freq. Burst reading task in Dedicated mode. #define TCH_SB_DSP_TASK 9 // Sync. Burst reading task in Dedicated mode. -#if ((REL99 == 1) && (FF_BHO == 1)) -#define FBSB_DSP_TASK 16 // Freq.+Sync. Burst reading task in Blind Handover. -#endif #define IDLE1 1 // Debug tasks @@ -1269,7 +1005,7 @@ #define TCH_LOOP_A 31 #define TCH_LOOP_B 32 -#if (DSP >= 33) +#if (DSP == 33) || (DSP == 34) || (DSP == 35) || (DSP == 36) #define SC_CHKSUM_VER (DB_W_PAGE_0 + (2 * (0x08DB - 0x800))) #else #define SC_CHKSUM_VER (DB_W_PAGE_0 + (2 * (0x09A0 - 0x800))) @@ -1301,14 +1037,7 @@ //#define D_NSUBB_DEDIC 30L #define D_FB_THR_DET_IACQ 0x3333L #define D_FB_THR_DET_TRACK 0x28f6L - -#if (RF_FAM == 60) -// UPPCosto without dc offset compensation (DSP algo) - #define D_DC_OFF_THRES 0x0000L -#else #define D_DC_OFF_THRES 0x7fffL -#endif - #define D_DUMMY_THRES 17408L #define D_DEM_POND_GEWL 26624L #define D_DEM_POND_RED 20152L @@ -1329,7 +1058,7 @@ #define D_MD_MAX_THR_TCHFS 1700L //(2000L *C_POND_RED) #define D_MD1_MAX_THR_TCHFS 99L //(160L *C_POND_RED) -#if (DSP >= 33) +#if (DSP == 33) || (DSP == 34) || (DSP == 35) || (DSP == 36) // Frequency burst definitions #define D_FB_MARGIN_BEG 24 #define D_FB_MARGIN_END 22 @@ -1341,7 +1070,7 @@ #define D_V42B_RESET_DELAY 10L // Latencies definitions - #if (DSP >= 33) + #if (DSP == 33) || (DSP == 34) || (DSP == 35) || (DSP == 36) // C.f. BUG1404 #define D_LAT_MCU_BRIDGE 0x000FL #else @@ -1358,9 +1087,7 @@ #if (CHIPSET == 4) #define D_MISC_CONFIG 0L -#elif (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 10) || (CHIPSET == 11) || (CHIPSET == 12) || (CHIPSET == 15) - // This variable is basically used for Samson. If SAMSON should be zero. - // A variable for making DSP not go to IDLE3 when DMA is on +#elif (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 10) || (CHIPSET == 11) || (CHIPSET == 12) #define D_MISC_CONFIG 1L #else #define D_MISC_CONFIG 0L @@ -1420,12 +1147,6 @@ // d_ra_act: bit field definition #define B_F48BLK 5 -#if REL99 -#if FF_EMR -#define B_F48BLK_DL 6 -#endif -#endif - // Mask for b_itc information (d_ra_conf) #define CE_MASK 0x04 @@ -1436,12 +1157,12 @@ #define D_TI_VERSION 0 -/*----------------------------------------------------------------------------*/ -/* */ -/* DEFINITIONS FOR DSP <-> MCU COMMUNICATION. */ -/* ++++++++++++++++++++++++++++++++++++++++++ */ -/* */ -/*----------------------------------------------------------------------------*/ +/*------------------------------------------------------------------------------*/ +/* */ +/* DEFINITIONS FOR DSP <-> MCU COMMUNICATION. */ +/* ++++++++++++++++++++++++++++++++++++++++++ */ +/* */ +/*------------------------------------------------------------------------------*/ // COMMUNICATION Interrupt definition //------------------------------------ #define ALL_16BIT 0xffffL @@ -1463,16 +1184,7 @@ #define D_ANGLE 2 // Angle (AFC correction) #define D_SNR 3 // Signal / Noise Ratio. -#if REL99 -#if FF_EMR - #define D_CV_BEP 2 - #define D_MEAN_BEP_MSW 0 - #define D_MEAN_BEP_LSW 1 -#endif -#endif //L1_R99 - // Bit name/position definitions. -#define B_JOINT 4 // Chase combining flag #define B_FIRE0 5 // Fire result bit 0. (00 -> NO ERROR) (01 -> ERROR CORRECTED) #define B_FIRE1 6 // Fire result bit 1. (10 -> ERROR) (11 -> unused) #define B_SCH_CRC 8 // CRC result for SB decoding. (1 for ERROR). @@ -1483,21 +1195,6 @@ #define B_ECRC 9 // Enhanced full rate CRC bit #define B_EMPTY_BLOCK 10 // for voice memo purpose, this bit is used to determine -#if REL99 -#if FF_EMR - #define MEAN_BEP_FORMAT 5 // mean_bep is received in F1.31 format from DSP and should be - // reported in F6.26 format to L2. - #define CV_BEP_FORMAT 5 // cv_bep is received in F3.13 format from DSP and should be - // reported in F8.8 format to L2. - #define B_SID1 4 // SID1 bit. - #define B_M1 0 // M1 bit. - #define B_CE 8 // Connection element - #define B_FCS_OK 3 // Frame check sequence bit - #define WORD_SHIFT 16 // Shift word -#endif -#endif //L1_R99 - - #if (DEBUG_DEDIC_TCH_BLOCK_STAT == 1) #define FACCH_GOOD 10 #define FACCH_BAD 11 @@ -1526,15 +1223,6 @@ // List of possible RX types in RATSCCH block #define C_RATSCCH_GOOD 5 - #if REL99 - #if FF_EMR - #define RATSCCH_GOOD 5 - #define RATSCCH_BAD 6 - #endif - #endif //L1_R99 - - - // List of the possible AMR channel rate #define AMR_CHANNEL_4_75 0 #define AMR_CHANNEL_5_15 1 @@ -1545,7 +1233,6 @@ #define AMR_CHANNEL_10_2 6 #define AMR_CHANNEL_12_2 7 - // Types of RATSCCH blocks #define C_RATSCCH_UNKNOWN 0 #define C_RATSCCH_CMI_PHASE_REQ 1 @@ -1593,85 +1280,20 @@ #define B_BULRAMPDEL_BIS 9 #define B_BULRAMPDEL2_BIS 10 #endif -#if ((RF_FAM == 61) && ((DSP == 38) || (DSP == 39))) - #define B_BULRAMPDEL 3 // Note: this name is changed - #define B_BULRAMPDEL2 2 // Note: this name is changed - #define B_BULRAMPDEL_BIS 9 - #define B_BULRAMPDEL2_BIS 10 -#endif #define B_AFC 4 // "d_ctrl_system" bits positions. #define B_TSQ 0 #define B_BCCH_FREQ_IND 3 #define B_TASK_ABORT 15 // Abort RF tasks for DSP. -#define B_SWH_APPLY_WHITENING 4 // SWH control(enable, disable) - -#if (NEW_SNR_THRESHOLD == 1) && (L1_SAIC == 0) -#error "SNR threshold valid only for SAIC build" -#endif - -//SAIC related -#define B_SWH 1 /* SWH bit position */ -#define B_NEW_POND 2 /* NEW_POND bit position*/ -#define B_SWH_DOUBLE_INTERPOLATION 3 /* Single or Double Interpolation*/ -#define B_SWH_INTERPOLATE 4 /* interpolate or not*/ -#define B_TOA_ALMNT 5 /* New TOA alignment from DSP for non saic mode*/ -#define B_SNR_ALMNT 6 /* New SNR threshold set to 1024 for AFC and TOA*/ - -// DB Area -#define B_SAIC_DB 0 -#define B_NEW_POND_DB 1 -#define B_SWH_DB 4 -#define B_SWH_CHANTAP 12 -#define SAIC_ENABLE_DB ((0x01 << B_SAIC_DB) | (0x01 << B_NEW_POND_DB)) -#if (NEW_SNR_THRESHOLD == 1) -#if (ONE_THIRD_INTRPOL ==1 ) -#define SAIC_INITIAL_VALUE ((1<< B_SWH)|(1<< B_NEW_POND)| (1<< B_SWH_DOUBLE_INTERPOLATION)) | (1 << B_SWH_INTERPOLATE) |(1<< B_TOA_ALMNT) | (1 << B_SNR_ALMNT) -#else /* ONE_THIRD_INTRPOL == 0*/ -#define SAIC_INITIAL_VALUE ((1<< B_SWH)|(1<< B_NEW_POND)| (1 << B_SWH_INTERPOLATE) |(1<< B_TOA_ALMNT) | (1 << B_SNR_ALMNT) -#endif /* ONE_THIRD_INTRPOL*/ -#else /* NEW_SNR_THRESHOLD == 0 */ -#if (ONE_THIRD_INTRPOL ==1 ) -#define SAIC_INITIAL_VALUE ((1<< B_SWH)|(1<< B_NEW_POND)| (1<< B_SWH_DOUBLE_INTERPOLATION)) | (1 << B_SWH_INTERPOLATE) /* added for CQ-95275 & 93303 */ -#else -#define SAIC_INITIAL_VALUE ((1<< B_SWH)|(1<< B_NEW_POND)) | (1 << B_SWH_INTERPOLATE) -#endif//ONE_THIRD_INTRPOL -#endif /*NEW_SNR_THRESHOLD*/ -#if (FF_L1_FAST_DECODING == 1) -#define B_FAST_DECODING_FLAG (5) -#define C_FAST_DECODING_CRC_FIRE1 (0x02) +/* + * FreeCalypso Frankenstein: the following definition has been + * imported from LoCosto version of l1_const.h; it is needed for + * the LoCosto-based C code to compile. + */ +#define C_BA_PM_MEAS (2) -/* Fast decoding states */ -#define C_FAST_DECODING_NONE 0 -#define C_FAST_DECODING_AWAITED 1 -#define C_FAST_DECODING_PROCESSING 2 -#define C_FAST_DECODING_COMPLETE 3 -#define C_FAST_DECODING_FORBIDDEN 4 - -#endif /* FF_L1_FAST_DECODING */ - -#if (FF_L1_FAST_DECODING == 1) -#define C_BA_PM_MEAS (4) -#else -#define C_BA_PM_MEAS (2) -#endif /* FF_L1_FAST_DECODING */ - -#if FF_L1_IT_DSP_USF - // d_dsp_hint_flag word definition - #define B_USF_HINT_ISSUED 0 - #define B_NON_USF_HINT_ISSUED 1 -#endif -#if FF_L1_IT_DSP_DTX - // d_fast_dtx_hint word definition- now d_fast_dtx_hint is not used- same as- d_dsp_hint_flag - #define B_DTX_HINT_ISSUED 0 - #define B_DTX_STATE 1 - - // d_tch_mode_ext word definition - #define B_FAST_DTX_ENABLED 0 - #define B_NON_USF_HINT_ISSUED 1 -#endif // **************************************************************** // POLESTAR EVABOARD 3 REGISTERS & ADRESSES DEFINITIONS // **************************************************************** @@ -1682,9 +1304,7 @@ #define DB_SIZE (4*20L) // 4 pages of 20 words... - #if (DSP >= 33) - #define MCU_API_BASE_ADDRESS 0xFFD00000L - #define DSP_API_BASE_ADDRESS 0x800 + #if (DSP == 33) || (DSP == 34) || (DSP == 35) || (DSP == 36) #define DB_W_PAGE_0 0xFFD00000L // DB page 0 write : 20 words long #define DB_W_PAGE_1 0xFFD00028L // DB page 1 write : 20 words long #define DB_R_PAGE_0 0xFFD00050L // DB page 0 read : 20 words long @@ -1696,19 +1316,7 @@ #define DB2_R_PAGE_0 0xFFD00184L #define DB2_R_PAGE_1 0xFFD00188L #endif - - #if (DSP >= 38) - /* DSP CPU load measurement */ - #define DSP_CPU_LOAD_MCU_API_BASE_ADDRESS 0xFFD01DE0L - #define DSP_CPU_LOAD_DB_W_PAGE_0 0xFFD01DE0L // DB page 0 write : 4 words long - #define DSP_CPU_LOAD_DB_W_PAGE_1 0xFFD01DE8L // DB page 1 write : 4 words long - #define DSP_CPU_LOAD_MCU_W_CTRL 0xFFD01DF0L // DSP CPU load feature control - #define DSP_CPU_LOAD_MCU_W_TDMA_FN 0xFFD01DF2L // MCU TDMA frame number - #endif - #else - #define MCU_API_BASE_ADDRESS 0xFFD00000L - #define DSP_API_BASE_ADDRESS 0x800 #define DB_W_PAGE_0 0xFFD00000L // DB page 0 write : 20 words long #define DB_W_PAGE_1 0xFFD00028L // DB page 1 write : 20 words long #define DB_R_PAGE_0 0xFFD00050L // DB page 0 read : 20 words long @@ -1717,12 +1325,6 @@ #define PARAM_ADR 0xFFD002b8L // PARAM start address : 57 words #endif - #if (DSP == 38) || (DSP == 39) - // a DB common is used by the GSM and GPRS for the common feature - #define DB_COMMON_W_PAGE_0 0xFFD00760L // DB common page 0 - #define DB_COMMON_W_PAGE_1 0xFFD00780L // DB common page 1 - #endif - // **************************************************************** // ADC reading definitions // **************************************************************** @@ -1788,14 +1390,5 @@ #define THR_MASK 0x003F #define HYST_MASK 0x000F #define CMIP_MASK 0x0001 - #endif -#if (L1_RF_KBD_FIX == 1) - -#define FRAME_DURATION 5000 -#define CUST_DEBOUNCE_TIME 64 - -#endif - -#endif // L1_CONST_H
--- a/L1/include/l1_ctl.h Thu Jun 09 00:19:28 2016 +0000 +++ b/L1/include/l1_ctl.h Thu Jun 09 00:45:00 2016 +0000 @@ -1,55 +1,35 @@ /************* Revision Controle System Header ************* - * GSM Layer 1 software + * GSM Layer 1 software * L1_CTL.H * * Filename l1_ctl.h - * Copyright 2003 (C) Texas Instruments + * Copyright 2003 (C) Texas Instruments * ************* Revision Controle System Header *************/ /************************************/ /* Automatic timing control (TOA) */ /************************************/ -#define C_RED 1 // Factor used to reduce the maximum accumulated values. - // Default : 1/2 -#define C_GEW 1 // Weighting factor. Default : 1/2 +#define C_RED 1 // Factor used to reduce the maximum accumulated values. + // Default : 1/2 +#define C_GEW 1 // Weighting factor. Default : 1/2 #define C_SNRGR 2560 // 2.5 F6.10 #define C_SNR_THR 8192 // 8 F6.10 -#define TOA_HISTO_LEN 11 // Histogram length - -#define IL_FOR_RXLEV_SNR 220 // RX POWER LEVEL //increased from 210 to 220 +#define TOA_HISTO_LEN 11 // Histogram length -#if (TOA_ALGO == 2) - #define L1_TOA_SCALING_CONSTANT (32768) // L1_TOA_SCALING_CONSTANT - #define L1_TOA_LAMBDA (0x7800) // 0.9375 represented in Q15 i.e. 0.9375*32768 - #define L1_TOA_ONE_MINUS_LAMBDA (0x0800) // 0.0625 represented in Q15 i.e. 0.0625*32768 - #define L1_TOA_THRESHOLD_15 (0x1333) // 0.15 in Q15 - #define L1_TOA_THRESHOLD_20 (0x1999) // 0.20 in Q15 - #define L1_TOA_THRESHOLD_25 (0x2000) // 0.25 in Q15 - #define L1_TOA_THRESHOLD_30 (0x2666) // 0.30 in Q15 - #if (CODE_VERSION == SIMULATION) - #define L1_TOA_SNR_THRESHOLD (0) // For simulator the threshold is made zero to facilitate - // TOA testing in simulator - #else - #if (NEW_SNR_THRESHOLD == 0) - #define L1_TOA_SNR_THRESHOLD (480) // 0x1E0 in F6.10 is equal to 0.46875 - #else - #define L1_TOA_SNR_THRESHOLD (2048) // 0x1E0 in F6.10 is equal to 0.46875 - #endif /* NEW_SNR_THRESHOLD*/ +/* + * FreeCalypso Frankenstein: the following definition has been added + * from LoCosto version of this file, as it is used by l1_cmplx.c + * fairly extensively. + * + * Disassembly-matching reconstruction has revealed that the constant + * in question was originally 210 in the TCS211 version, and then + * increased to 220 in the LoCosto source. We currently seek to match + * TCS211 without any changes, hence we are setting it back to 210. + */ +#define IL_FOR_RXLEV_SNR 210 // RX POWER LEVEL - #endif - #if (CODE_VERSION == SIMULATION) - #define L1_TOA_EXPECTED_TOA (14) // Expected TOA on the MCU side - #else - #define L1_TOA_EXPECTED_TOA (14) // Expected TOA on the MCU side - #endif -#endif - -#if (NEW_SNR_THRESHOLD == 1) - #define SAIC_OFF (0) - #define SAIC_ON (1) -#endif /* NEW_SNR_THRESHOLD */ /************************************/ /* Automatic Gain Control (AGC) */ /************************************/ @@ -60,56 +40,30 @@ /************************************/ /* Automatic frequency compensation */ /************************************/ -#if (L1_SAIC == 1) -#define C_thr_snr 2048// 1/0.4 * 2**10 - CQ no- 76320 -#else -#define C_thr_snr 2560 // 1/0.4 * 2**10 -#endif -#define C_thr_P 524288L // 0.5 * 2**20 -#define C_cov_start 838861L // 0.8 * 2**20 -#define C_a0_kalman 10486L // 0.01 * 2**20 -#define C_g_kalman 53687091L// 0.05 * 2**30 +#define C_thr_snr 2560 // 1/0.4 * 2**10 +#define C_thr_P 524288L // 0.5 * 2**20 +#define C_cov_start 838861L // 0.8 * 2**20 +#define C_a0_kalman 10486L // 0.01 * 2**20 +#define C_g_kalman 53687091L// 0.05 * 2**30 #define C_N_del 2 // delay of frequency control loop - // due to C W R pipeline -#define C_Q 3L // 0.000003 * 2**20 -#define C_thr_K 209715L // 0.2 * 2**20 + // due to C W R pipeline +#define C_Q 3L // 0.000003 * 2**20 +#define C_thr_K 209715L // 0.2 * 2**20 #define C_thr_phi 328 // 0.01 * 2**15 #if (VCXO_ALGO == 1) #define C_WIN_AVG_SIZE_M 64 // average size M #define C_PSI_AVG_SIZE_D 32 // distance size D #define C_MSIZE (C_WIN_AVG_SIZE_M * C_PSI_AVG_SIZE_D) // Data history for predictor - #define C_RGAP_BAD_SNR_COUNT_B 32 // bad SNR count B + #define C_RGAP_BAD_SNR_COUNT_B 32 // bad SNR count B #define ALGO_AFC_RXGAP 1 // reception gap algo #define ALGO_AFC_KALMAN 1 // Kalman filter #define ALGO_AFC_LQG_PREDICTOR 2 // LQG filter + rgap predictor #define ALGO_AFC_KALMAN_PREDICTOR 3 // Kalman filter + rgap predictor #endif -#if ((ANALOG == 1) || (ANALOG == 2) || (ANALOG == 3) || (ANALOG == 11)) +#if ((ANALOG == 1) || (ANALOG == 2) || (ANALOG == 3)) // clipping related to AFC DAC linearity range - #define C_max_step 32000 // 4000 * 2**3 - #define C_min_step -32000 // -4000 * 2**3 + #define C_max_step 32000 // 4000 * 2**3 + #define C_min_step -32000 // -4000 * 2**3 #endif - -/***************************************************/ -/* SAIC (Single Antenna Interference Cancellation) */ -/***************************************************/ - -#if (L1_SAIC != 0) -#define L1_SAIC_GENIE_GSM_GPRS_IDLE_THRESHOLD 192 // Input Level Threshold for GSM/GPRS Idle. - #define L1_SAIC_GENIE_GSM_DEDIC_THRESHOLD 192 // Input Level Threshold for GSM Dedicated. - #define L1_SAIC_GENIE_GPRS_PCKT_TRAN_THRESHOLD 192 // Input Level Threshold for GPRS Packet Transfer -#endif - - -#define L1_SAIC_HARDWARE_FILTER (1) -#define L1_SAIC_PROGRAMMABLE_FILTER (0) - -//Locosto. For Locosto psi_quant = F14.2 else F13.3 -#if(RF_FAM == 61) -#define CONVERT_PSI_QUANT(value) (value >> 2) -#else -#define CONVERT_PSI_QUANT(value) (value >> 3) -#endif -
--- a/L1/include/l1_defty.h Thu Jun 09 00:19:28 2016 +0000 +++ b/L1/include/l1_defty.h Thu Jun 09 00:45:00 2016 +0000 @@ -3,33 +3,12 @@ * L1_DEFTY.H * * Filename l1_defty.h - * Copyright 2003 (C) Texas Instruments + * Copyright 2003 (C) Texas Instruments * ************* Revision Controle System Header *************/ - -#if (L1_RF_KBD_FIX == 1) -#include "l1_macro.h" - -#if(OP_L1_STANDALONE == 0) -#include "kpd/kpd_scan_functions.h" -#endif - -#endif - -#include "../../gpf/inc/cust_os.h" #if(L1_DYN_DSP_DWNLD == 1) #include "../dyn_dwl_include/l1_dyn_dwl_defty.h" #endif -#if (L1_AAC == 1) //ADDED for AAC -sajal - #include "l1aac_defty.h" -#endif - -typedef struct -{ - UWORD8 enable; // activation of FACCH test - UWORD8 period; // period of FACCH test -} -T_FACCH_TEST_PARAMS; typedef struct { @@ -47,27 +26,6 @@ typedef struct { - UWORD8 srr; /* SACCH Repetition Request - UL */ - UWORD8 sro; /* SACCH Repetition Order - DL */ - UWORD8 buffer[22+1]; /* New uplink buffer to save the repetition block data in case of retransmission */ - BOOL buffer_empty; /* It is equal to 1 if the UL repetion buffer should be empty otherwise 0 */ -} -T_REPEAT_SACCH; - -typedef struct -{ - API buffer[12]; /* New buffer to save the DL data for comparison */ - UWORD8 buffer_empty; /* To indicate the saved buffer */ -}T_REPEAT_FACCH_PIPELINE; -typedef struct -{ - T_REPEAT_FACCH_PIPELINE pipeline[2]; - UWORD8 counter; - UWORD8 counter_candidate; -} T_REPEAT_FACCH; - -typedef struct -{ BOOL status; UWORD16 radio_freq; UWORD32 fn_offset; @@ -82,26 +40,10 @@ #if (L1_12NEIGH ==1) UWORD32 fn_offset_mem; UWORD32 time_alignmt_mem; -#endif // (L1_12NEIGH ==1) -#if ((REL99 == 1) && ((FF_BHO == 1) || (FF_RTD == 1))) - UWORD8 nb_fb_attempt ; - UWORD8 fb26_position; // used for RTD feature #endif } T_NCELL_SINGLE; -#if ((REL99 == 1) && (FF_BHO == 1)) -typedef struct -{ - UWORD8 fb_found_attempt; - UWORD16 radio_freq; - UWORD32 fn_offset; - UWORD32 time_alignmt; - UWORD32 fb_toa; -} -T_BHO_PARAM; -#endif // #if ((REL99 == 1) && (FF_BHO == 1)) - typedef struct { UWORD8 active_neigh_id_norm; @@ -187,11 +129,7 @@ typedef struct { -#if(L1_A5_3 == 1 && OP_L1_STANDALONE != 1) - UWORD8 A[15+1]; -#else UWORD8 A[7+1]; -#endif } T_ENCRYPTION_KEY; @@ -327,6 +265,14 @@ typedef struct { + T_CHANNEL_DESCRIPTION channel_desc; + T_MOBILE_ALLOCATION frequency_list; + T_STARTING_TIME starting_time; +} +T_MPHC_CHANGE_FREQUENCY; + +typedef struct +{ UWORD8 subchannel; UWORD8 channel_mode; #if (AMR == 1) @@ -337,6 +283,14 @@ typedef struct { + UWORD8 cipher_mode; + UWORD8 a5_algorithm; + T_ENCRYPTION_KEY new_ciph_param; +} +T_MPHC_SET_CIPHERING_REQ; + +typedef struct +{ UWORD8 sub_channel; UWORD8 frame_erasure; } @@ -399,34 +353,6 @@ } T_TASK_MFTAB; - -#if (GSM_IDLE_RAM != 0) - typedef struct - { - BOOL l1s_full_exec; - BOOL trff_ctrl_enable_cause_int; - WORD32 hw_timer; - WORD32 os_load; - UWORD32 sleep_mode; - -#if GSM_IDLE_RAM_DEBUG - UWORD32 killing_flash_access; - UWORD32 killing_ext_ram_access; - UWORD32 irq; - UWORD32 fiq; - UWORD32 nb_inth; - -#if (CHIPSET == 10) && (OP_WCP == 1) - UWORD16 TC_true_control; -#endif // CHIPSET && OP_WCP -#endif // GSM_IDLE_RAM_DEBUG - UWORD32 task_bitmap_idle_ram[SIZE_TAB_L1S_MONITOR]; - UWORD32 mem_task_bitmap_idle_ram[SIZE_TAB_L1S_MONITOR]; - } - T_L1S_GSM_IDLE_INTRAM; -#endif // GSM_IDLE_RAM - - /***********************************************************/ /* TPU controle register components definition. */ /***********************************************************/ @@ -468,103 +394,73 @@ typedef struct { - API d_task_d; // 0x0800 (0) Downlink task command. - API d_burst_d; // 0x0801 (1) Downlink burst identifier. - API d_task_u; // 0x0802 (2) Uplink task command. - API d_burst_u; // 0x0803 (3) Uplink burst identifier. - API d_task_md; // 0x0804 (4) Downlink Monitoring (FB/SB) command. -#if (DSP >= 33) - API d_background; // 0x0805 (5) Background tasks + API d_task_d; // (0) Downlink task command. + API d_burst_d; // (1) Downlink burst identifier. + API d_task_u; // (2) Uplink task command. + API d_burst_u; // (3) Uplink burst identifier. + API d_task_md; // (4) Downlink Monitoring (FB/SB) command. +#if (DSP == 33) || (DSP == 34) || (DSP == 35) || (DSP == 36) + API d_background; // (5) Background tasks #else - API d_reserved; // 0x0805 (5) Reserved + API d_reserved; // (5) Reserved #endif - API d_debug; // 0x0806 (6) Debug/Acknowledge/general purpose word. - API d_task_ra; // 0x0807 (7) RA task command. - API d_fn; // 0x0808 (8) FN, in Rep. period and FN%104, used for TRAFFIC/TCH only. + API d_debug; // (6) Debug/Acknowledge/general purpose word. + API d_task_ra; // (7) RA task command. + API d_fn; // (8) FN, in Rep. period and FN%104, used for TRAFFIC/TCH only. // bit [0..7] -> b_fn_report, FN in the normalized reporting period. // bit [8..15] -> b_fn_sid, FN % 104, used for SID positionning. - API d_ctrl_tch; // 0x0809 (9) Tch channel description. + API d_ctrl_tch; // (9) Tch channel description. // bit [0..3] -> b_chan_mode, channel mode. // bit [4..5] -> b_chan_type, channel type. // bit [6] -> reset SACCH - // bit [7] -> vocoder O + // bit [7] -> vocoder ON // bit [8] -> b_sync_tch_ul, synchro. TCH/UL. // bit [9] -> b_sync_tch_dl, synchro. TCH/DL. // bit [10] -> b_stop_tch_ul, stop TCH/UL. // bit [11] -> b_stop_tch_dl, stop TCH/DL. // bit [12.13] -> b_tch_loop, tch loops A/B/C. - API hole; // 0x080A (10) unused hole. - -#if ((ANALOG == 1) || (ANALOG == 2) || (ANALOG == 3) || (ANALOG == 11)) - API d_ctrl_abb; // 0x080B (11) Bit field indicating the analog baseband register to send. + API hole; // (10) unused hole. + +#if ((ANALOG == 1) || (ANALOG == 2) || (ANALOG == 3)) + API d_ctrl_abb; // (11) Bit field indicating the analog baseband register to send. // bit [0] -> b_ramp: the ramp information(a_ramp[]) is located in NDB // bit [1.2] -> unused // bit [3] -> b_apcdel: delays-register in NDB // bit [4] -> b_afc: freq control register in DB // bit [5..15] -> unused #endif - API a_a5fn[2]; // 0x080C (12..13) Encryption Frame number. + API a_a5fn[2]; // (12..13) Encryption Frame number. // word 0, bit [0..4] -> T2. // word 0, bit [5..10] -> T3. // word 1, bit [0..11] -> T1. - API d_power_ctl; // 0x080E (14) Power level control. - API d_afc; // 0x080F (15) AFC value (enabled by "b_afc" in "d_ctrl_TCM4400 or in d_ctrl_abb"). - API d_ctrl_system; // 0x0810 (16) Controle Register for RESET/RESUME. + API d_power_ctl; // (14) Power level control. + API d_afc; // (15) AFC value (enabled by "b_afc" in "d_ctrl_TCM4400 or in d_ctrl_abb"). + API d_ctrl_system; // (16) Controle Register for RESET/RESUME. // bit [0..2] -> b_tsq, training sequence. // bit [3] -> b_bcch_freq_ind, BCCH frequency indication. // bit [15] -> b_task_abort, DSP task abort command. - // bit [4] -> B_SWH_APPLY_WHITENING, Apply whitening. -//#if (((DSP == 36)||(DSP == 37)||(DSP == 38) || (DSP == 39))) -// API d_swh_ApplyWhitening_db; // 0x0811 SWH Whitening Activation Flag -//#endif } T_DB_MCU_TO_DSP; -#if (DSP == 38) || (DSP == 39) - // DB COMMON to GSM and GPRS - typedef struct - { - API d_dco_algo_ctrl_nb; // DRP DCO enable/disable for normal burst - API d_dco_algo_ctrl_sb; // DRP DCO enable/disable for synchro burst - API d_dco_algo_ctrl_pw; // DRP DCO enable/disable for power burst - API d_swh_ctrl_db; - API d_fast_paging_ctrl; - } - T_DB_COMMON_MCU_TO_DSP; -#endif // DSP == 38 || DSP == 39 - -/* DSP CPU load measurement */ -#if (DSP == 38) || (DSP == 39) - // DB COMMON to GSM and GPRS - typedef struct - { - API d_dsp_fgd_tsk_tim0; - API d_dsp_fgd_tsk_tim1; - API d_tdma_dsp_fn; - API d_dsp_page_read; - } - T_DB_MCU_TO_DSP_CPU_LOAD; -#endif // DSP == 38 || DSP == 39 - typedef struct { - API d_task_d; // 0x0828 (0) Downlink task command. - API d_burst_d; // 0x0829 (1) Downlink burst identifier. - API d_task_u; // 0x082A (2) Uplink task command. - API d_burst_u; // 0x082B (3) Uplink burst identifier. - API d_task_md; // 0x082C (4) Downlink Monitoring (FB/SB) task command. -#if (DSP >= 33) - API d_background; // 0x082D (5) Background tasks + API d_task_d; // (0) Downlink task command. + API d_burst_d; // (1) Downlink burst identifier. + API d_task_u; // (2) Uplink task command. + API d_burst_u; // (3) Uplink burst identifier. + API d_task_md; // (4) Downlink Monitoring (FB/SB) task command. +#if (DSP == 33) || (DSP == 34) || (DSP == 35) || (DSP == 36) + API d_background; // (5) Background tasks #else - API d_reserved; // 0x082D (5) Reserved + API d_reserved; // (5) Reserved #endif - API d_debug; // 0x082E (6) Debug/Acknowledge/general purpose word. - API d_task_ra; // 0x082F (7) RA task command. - -#if (DSP >= 33) - API a_serv_demod[4]; // 0x0830 ( 8..11) Serv. cell demod. result, array of 4 words (D_TOA,D_PM,D_ANGLE,D_SNR). - API a_pm[3]; // 0x0834 (12..14) Power measurement results, array of 3 words. - API a_sch[5]; // 0x0837 (15..19) Header + SB information, array of 5 words. + API d_debug; // (6) Debug/Acknowledge/general purpose word. + API d_task_ra; // (7) RA task command. + +#if (DSP == 33) || (DSP == 34) || (DSP == 35) || (DSP == 36) + API a_serv_demod[4]; // ( 8..11) Serv. cell demod. result, array of 4 words (D_TOA,D_PM,D_ANGLE,D_SNR). + API a_pm[3]; // (12..14) Power measurement results, array of 3 words. + API a_sch[5]; // (15..19) Header + SB information, array of 5 words. #else API a_pm[3]; // ( 8..10) Power measurement results, array of 3 words. API a_serv_demod[4]; // (11..14) Serv. cell demod. result, array of 4 words (D_TOA,D_PM,D_ANGLE,D_SNR). @@ -573,744 +469,7 @@ } T_DB_DSP_TO_MCU; -#if (DSP == 38) || (DSP == 39) - typedef struct - { - // MISC Tasks - API d_dsp_page; // 0x08D4 - - // DSP status returned (DSP --> MCU). - API d_error_status; // 0x08D5 - - // RIF control (MCU -> DSP). // following is removed for Locosto - API d_spcx_rif_hole; // 0x08D6 - - - API d_tch_mode; // 0x08D7 TCH mode register. - // bit [0..1] -> b_dai_mode. - // bit [2] -> b_dtx. - - API d_debug1; // 0x08D8 bit 0 at 1 enable dsp f_tx delay for Omega - - API d_dsp_test; // 0x08D9 - - // Words dedicated to Software version (DSP code + Patch) - API d_version_number1; // 0x08DA - API d_version_number2; // 0x08DB - - API d_debug_ptr; // 0x08DC - API d_debug_bk; // 0x08DD - - API d_pll_config; // 0x08DE - - // GSM/GPRS DSP Debug trace support - API p_debug_buffer; // 0x08DF - API d_debug_buffer_size; // 0x08E0 - API d_debug_trace_type; // 0x08E1 - - #if (W_A_DSP_IDLE3 == 1) - // DSP report its state: 0 run, 1 Idle1, 2 Idle2, 3 Idle3. - API d_dsp_state; // 0x08E2 - // 5 words are reserved for any possible mapping modification - API d_hole1_ndb[2]; // 0x08E3 - #else - // 6 words are reserved for any possible mapping modification - API d_hole1_ndb[3]; - #endif - - #if (AMR == 1) - API p_debug_amr; // 0x08E5??? DSP doc says reserved - #else - API d_hole_debug_amr; - #endif - - API d_dsp_iq_scaling_factor; // 0x08E6 - API d_mcsi_select; // 0x08E7 - - // New words APCDEL1 and APCDEL2 for 2TX: TX/PRACH combinations - API d_apcdel1_bis; // 0x08E8 - API d_apcdel2_bis; - // New registers due to IOTA analog base band - API d_apcdel2; - - - API d_vbctrl2_hole; // 0x08EB - API d_bulgcal_hole; // 0x08EC - // Analog Based Band - removed in ROM 38 - API d_afcctladd_hole; // 0x08ED - API d_vbuctrl_hole; // 0x08EE - removed in ROM38 - API d_vbdctrl_hole; // 0x08EF - removed in ROM38 - - API d_apcdel1; // 0x08F0 - // New Variables Added due to the APC Switch - // But for when DSP is in Idle3 all writes from MCU to APC are routed via DSP - API d_apclev; // APCLEV - 0x08F1 (In ROM36 - apcoff ) - // NOTE: Used Only in Test mode - // Only when l1_config.tmode.rf_params.down_up == TMODE_UPLINK; - API d_apcctrl2; // APCCTRL2 - 0x08F2 (In ROM36 - bulioff) - API d_bulqoff_hole; // 0x08F3 - API d_dai_onoff; // 0x08F4 - API d_auxdac_hole; // 0x08F5 - - API d_vbctrl_hole; // 0x08F6 - removed in ROM38 - - API d_bbctrl_hole; // 0x08F7 - removed in ROM38 - - // Monitoring tasks control (MCU <- DSP) - // FB task - API d_fb_det; // 0x08F8 FB detection result. (1 for FOUND). - API d_fb_mode; // Mode for FB detection algorithm. - API a_sync_demod[4]; // FB/SB demod. result, (D_TOA,D_PM,D_ANGLE,D_SNR). - - // SB Task - API a_sch26[5]; // 0x08FE Header + SB information, array of 5 words. - - API d_audio_gain_ul; // 0x0903 - API d_audio_gain_dl; // 0x0904 - - // Controller of the melody E2 audio compressor - removed in ROM 38 - API d_audio_compressor_ctrl_hole; // 0x0905 - removed in ROM37,38 - - // AUDIO module - API d_audio_init; // 0x0906 - API d_audio_status; // - - // Audio tasks - // TONES (MCU -> DSP) - API d_toneskb_init; - API d_toneskb_status; - API d_k_x1_t0; - API d_k_x1_t1; - API d_k_x1_t2; - API d_pe_rep; - API d_pe_off; - API d_se_off; - API d_bu_off; // 0x0910 - API d_t0_on; - API d_t0_off; - API d_t1_on; - API d_t1_off; - API d_t2_on; - API d_t2_off; - API d_k_x1_kt0; - API d_k_x1_kt1; - API d_dur_kb; - API d_shiftdl; - API d_shiftul; // 0x091B - - API d_aec_18_hole; // 0x091C - - API d_es_level_api; - API d_mu_api; - - // Melody Ringer module - API d_melo_osc_used; // 0x091F - API d_melo_osc_active; // 0x0920 - API a_melo_note0[4]; - API a_melo_note1[4]; - API a_melo_note2[4]; - API a_melo_note3[4]; - API a_melo_note4[4]; - API a_melo_note5[4]; - API a_melo_note6[4]; - API a_melo_note7[4]; - - // selection of the melody format - API d_melody_selection; // 0x0941 - - // Holes due to the format melody E1 - API a_melo_holes[3]; - - // Speech Recognition module - Removed in ROM38 - API d_sr_holes[19]; // 0x0945 - - // Audio buffer - API a_dd_1[22]; // 0x0958 Header + DATA traffic downlink information, sub. chan. 1. - API a_du_1[22]; // 0x096E Header + DATA traffic uplink information, sub. chan. 1. - - // V42bis module - API d_v42b_nego0; // 0x0984 - API d_v42b_nego1; - API d_v42b_control; - API d_v42b_ratio_ind; - API d_mcu_control; - API d_mcu_control_sema; - - // Background tasks - API d_background_enable; // 0x098A - API d_background_abort; - API d_background_state; - API d_max_background; - API a_background_tasks[16]; // 0x098E - API a_back_task_io[16]; //0x099E - - // GEA module defined in l1p_deft.h (the following section is overlaid with GPRS NDB memory) - API d_gea_mode_ovly_hole; // 0x09AE - API a_gea_kc_ovly_hole[4]; // 0x09AF - - API d_hole3_ndb[6]; //0x09B3 - API d_dsp_aud_hint_flag; // 0x09B9; - - // word used for the init of USF threshold - API d_thr_usf_detect; // 0x09BA - - // Encryption module - API d_a5mode; // Encryption Mode. - - API d_sched_mode_gprs_ovly; // 0x09Bc -#if (FF_L1_IT_DSP_USF == 1) || (FF_L1_IT_DSP_DTX == 1) - API d_hole1_fast_ndb[1]; // 0x09BD; - API d_dsp_hint_flag; // 0x09BE; //used for fast usf and fast dtx and other dyn dwn - // 6 words are reserved for any possible mapping modification - #if FF_L1_IT_DSP_DTX - API d_fast_dtx_enable;//used for enabling fast dtx- 0x09BF - API d_fast_dtx_enc_data;//fast usf written by DSP to indicate tx data is there or not- 0x09C0 - #else // FF_L1_IT_DSP_DTX - API d_hole3_fast_ndb[2]; // 0x09BF - #endif // FF_L1_IT_DSP_USF - #if (FF_L1_FAST_DECODING == 1) - API d_fast_paging_data; // 0x9C1 - #else - API d_hole_fast_paging_ndb; - #endif /* FF_L1_FAST_DECODING*/ -#else - // 7 words are reserved for any possible mapping modification - API d_hole4_ndb[5]; // 0x09BD -#endif - - // Ramp definition for Omega device - API a_ramp_hole[16]; //0x09C2 - - // CCCH/SACCH downlink information...(!!) - API a_cd[15]; //0x09D2 Header + CCCH/SACCH downlink information. - - // FACCH downlink information........(!!) - API a_fd[15]; // 0x09E1 Header + FACCH downlink information. - - // Traffic downlink data frames......(!!) - API a_dd_0[22]; // 0x09F0 Header + DATA traffic downlink information, sub. chan. 0. - - // CCCH/SACCH uplink information.....(!!) - API a_cu[15]; // 0x0A06 Header + CCCH/SACCH uplink information. - - // FACCH downlink information........(!!) - API a_fu[15]; // 0x0A15 Header + FACCH uplink information - - // Traffic downlink data frames......(!!) - API a_du_0[22]; // 0x0A24 Header + DATA traffic uplink information, sub. chan. 0. - - // Random access.....................(MCU -> DSP). - API d_rach; // 0x0A3A RACH information. - - //...................................(MCU -> DSP). - API a_kc[4]; // 0x0A3B Encryption Key Code. - - // Integrated Data Services module - API d_ra_conf; - API d_ra_act; - API d_ra_test; - API d_ra_statu; - API d_ra_statd; - API d_fax; - API a_data_buf_ul[21]; // 0x0A45 - API a_data_buf_dl[37]; // 0x0A5A - - API a_sr_holes0[422]; // 0x0A7F - - #if (L1_AEC == 1) - #if (L1_NEW_AEC) - API d_cont_filter; - API d_granularity_att; - API d_coef_smooth; - API d_es_level_max; - API d_fact_vad; - API d_thrs_abs; - API d_fact_asd_fil; - API d_fact_asd_mut; - API d_far_end_pow_h; - API d_far_end_pow_l; - API d_far_end_noise_h; - API d_far_end_noise_l; - #else - API a_sr_hole1[12]; - #endif - #else - API a_sr_hole2[12]; - #endif - - // Speech recognition model - API a_sr_holes1[145]; // 0x0C31 - - // Correction of PR G23M/L1_MCU-SPR-15494 - API d_cport_init; // 0x0CC2 - API d_cport_ctrl; - API a_cport_cfr[2]; - API d_cport_tcl_tadt; - API d_cport_tdat; - API d_cport_tvs; - API d_cport_status; - API d_cport_reg_value; - API a_cport_holes[1011]; - - API a_model_holes[1041]; - - // EOTD buffer -#if (L1_EOTD==1) - API d_eotd_first; - API d_eotd_max; - API d_eotd_nrj_high; - API d_eotd_nrj_low; - API a_eotd_crosscor[18]; -#else - API a_eotd_holes[22]; -#endif - // AMR ver 1.0 buffers - API a_amr_config[4]; // 0x14E5 - API a_ratscch_ul[6]; - API a_ratscch_dl[6]; - API d_amr_snr_est; // estimation of the SNR of the AMR speech block - #if (L1_VOICE_MEMO_AMR) - API d_amms_ul_voc; - #else - API a_voice_memo_amr_holes[1]; - #endif - API d_thr_onset_afs; // thresh detection ONSET AFS - API d_thr_sid_first_afs; // thresh detection SID_FIRST AFS - API d_thr_ratscch_afs; // thresh detection RATSCCH AFS - API d_thr_update_afs; // thresh detection SID_UPDATE AFS - API d_thr_onset_ahs; // thresh detection ONSET AHS - API d_thr_sid_ahs; // thresh detection SID frames AHS - API d_thr_ratscch_marker; // thresh detection RATSCCH MARKER - API d_thr_sp_dgr; // thresh detection SPEECH DEGRADED/NO_DATA - API d_thr_soft_bits; // 0x14FF - - - API a_amrschd_debug[30]; // 0x1500 - #if (W_A_AMR_THRESHOLDS) - API a_d_macc_thr_afs[8]; // 0x151E - API a_d_macc_thr_ahs[6]; // 0x1526 - #else - API d_holes[14]; // 0x151E - #endif - - // There is no melody E2 in DSP ROM38 as of now -> Only Holes - API d_melody_e2_holes[17]; // 0x152C - - - API d_vol_ul_level_hole; // 0x153D - API d_vol_dl_level_hole; // 0x153E - API d_vol_speed_hole; // 0x153F - API d_sidetone_level_hole; // 0x1540 - - // Audio control area - API d_es_ctrl; // 0x1541 - API d_anr_ul_ctrl; - API d_aec_ul_ctrl; - API d_agc_ul_ctrl; - //API d_aqi_ctrl_hole1[4]; // Reserved for future UL modules earlier code now modified and added d_vad_noise_ene_ndb - API d_aqi_ctrl_hole1[1]; // Reserved for future UL modules - - API d_vad_noise_ene_ndb[2]; //NAVC API address-0x1546-MSB, 0x1547-LSB-> 2-WORDs - - API d_navc_ctrl_status; // NAVC control - - API d_iir_dl_ctrl; // 0x1549 - API d_lim_dl_ctrl; - API d_drc_dl_ctrl; - API d_agc_dl_ctrl; - API d_audio_apps_ctrl; // Reserved for future DL modules - API d_audio_apps_status; - API d_aqi_status; - -#if (L1_IIR == 1) - API d_iir_input_scaling; // 0x1550 - API d_iir_fir_scaling; // - API d_iir_input_gain_scaling; // - API d_iir_output_gain_scaling; // - API d_iir_output_gain; // - API d_iir_feedback; // - API d_iir_nb_iir_blocks; // - API d_iir_nb_fir_coefs; // - API a_iir_iir_coefs[80]; // 0x1558 - API a_iir_fir_coefs[32]; // 0x15A8 - - #if (L1_ANR == 1) - API d_anr_min_gain; - API d_anr_vad_thr; - API d_anr_gamma_slow; - API d_anr_gamma_fast; - API d_anr_gamma_gain_slow; - API d_anr_gamma_gain_fast; - API d_anr_thr2; - API d_anr_thr4; - API d_anr_thr5; - API d_anr_mean_ratio_thr1; - API d_anr_mean_ratio_thr2; - API d_anr_mean_ratio_thr3; - API d_anr_mean_ratio_thr4; - API d_anr_div_factor_shift; - API d_anr_ns_level; - #else - API d_anr_hole[15]; - #endif - - -#elif (L1_IIR == 2) //Srart address= 0x1550. - API d_iir4x_control; - API d_iir4x_frame_size; - API d_iir4x_fir_swap; - API d_iir4x_fir_enable; - API d_iir4x_fir_length; - API_SIGNED d_iir4x_fir_shift; - API_SIGNED a_iir4x_fir_taps[40]; - API d_iir4x_sos_enable; - API d_iir4x_sos_number; - API_SIGNED d_iir4x_sos_fact_1; - API_SIGNED d_iir4x_sos_fact_form_1; - API_SIGNED a_iir4x_sos_den_1[2]; - API_SIGNED a_iir4x_sos_num_1[3]; - API_SIGNED d_iir4x_sos_num_form_1; - API_SIGNED d_iir4x_sos_fact_2; - API_SIGNED d_iir4x_sos_fact_form_2; - API_SIGNED a_iir4x_sos_den_2[2]; - API_SIGNED a_iir4x_sos_num_2[3]; - API_SIGNED d_iir4x_sos_num_form_2; - API_SIGNED d_iir4x_sos_fact_3; - API_SIGNED d_iir4x_sos_fact_form_3; - API_SIGNED a_iir4x_sos_den_3[2]; - API_SIGNED a_iir4x_sos_num_3[3]; - API_SIGNED d_iir4x_sos_num_form_3; - API_SIGNED d_iir4x_sos_fact_4; - API_SIGNED d_iir4x_sos_fact_form_4; - API_SIGNED a_iir4x_sos_den_4[2]; - API_SIGNED a_iir4x_sos_num_4[3]; - API_SIGNED d_iir4x_sos_num_form_4; - API_SIGNED d_iir4x_sos_fact_5; - API_SIGNED d_iir4x_sos_fact_form_5; - API_SIGNED a_iir4x_sos_den_5[2]; - API_SIGNED a_iir4x_sos_num_5[3]; - API_SIGNED d_iir4x_sos_num_form_5; - API_SIGNED d_iir4x_sos_fact_6; - API_SIGNED d_iir4x_sos_fact_form_6; - API_SIGNED a_iir4x_sos_den_6[2]; - API_SIGNED a_iir4x_sos_num_6[3]; - API_SIGNED d_iir4x_sos_num_form_6; - API_SIGNED d_iir4x_gain; //End address= 0x15B0 - - - #if (L1_AGC_UL == 1) //Start address= 0x15B1 - // AGC uplink - API d_agc_ul_control; - API d_agc_ul_frame_size; - API_SIGNED d_agc_ul_targeted_level; - API_SIGNED d_agc_ul_signal_up; - API_SIGNED d_agc_ul_signal_down; - API_SIGNED d_agc_ul_max_scale; - API_SIGNED d_agc_ul_gain_smooth_alpha; - API_SIGNED d_agc_ul_gain_smooth_alpha_fast; - API_SIGNED d_agc_ul_gain_smooth_beta; - API_SIGNED d_agc_ul_gain_smooth_beta_fast; - API_SIGNED d_agc_ul_gain_intp_flag; - #else - API d_agc_ul_holes[11]; - #endif //End address= 0x15BB - - #if (L1_AGC_DL == 1) - // AGC downlink - API d_agc_dl_control; //Start Address= 0x15BC - API d_agc_dl_frame_size; - API_SIGNED d_agc_dl_targeted_level; - API_SIGNED d_agc_dl_signal_up; - API_SIGNED d_agc_dl_signal_down; - API_SIGNED d_agc_dl_max_scale; - API_SIGNED d_agc_dl_gain_smooth_alpha; - API_SIGNED d_agc_dl_gain_smooth_alpha_fast; - API_SIGNED d_agc_dl_gain_smooth_beta; - API_SIGNED d_agc_dl_gain_smooth_beta_fast; - API_SIGNED d_agc_dl_gain_intp_flag; - #else - API d_agc_dl_holes[11]; - #endif //End address= 0x15C6 - - - #if(L1_AEC == 2) - API d_aec_mode; //Start address= 0x15C7 - API d_mu; - API d_cont_filter; - API d_scale_input_ul; - API d_scale_input_dl; - API d_div_dmax; - API d_div_swap_good; - API d_div_swap_bad; - API d_block_init; - API d_fact_vad; - API d_fact_asd_fil; - API d_fact_asd_mut; - API d_thrs_abs; - API d_es_level_max; - API d_granularity_att; - API d_coef_smooth; //End address= 0x15D6 - - #else - - #if (L1_ANR == 1) - API d_iir_holes[1]; - - API d_anr_min_gain; - API d_anr_vad_thr; - API d_anr_gamma_slow; - API d_anr_gamma_fast; - API d_anr_gamma_gain_slow; - API d_anr_gamma_gain_fast; - API d_anr_thr2; - API d_anr_thr4; - API d_anr_thr5; - API d_anr_mean_ratio_thr1; - API d_anr_mean_ratio_thr2; - API d_anr_mean_ratio_thr3; - API d_anr_mean_ratio_thr4; - API d_anr_div_factor_shift; - API d_anr_ns_level; - #else - API d_iir_anr_hole[16]; - #endif - #endif - - - #else - API d_iir_holes_1[97]; - #if (L1_AGC_UL == 1) - // AGC uplink - API d_agc_ul_control; - API d_agc_ul_frame_size; - API_SIGNED d_agc_ul_targeted_level; - API_SIGNED d_agc_ul_signal_up; - API_SIGNED d_agc_ul_signal_down; - API_SIGNED d_agc_ul_max_scale; - API_SIGNED d_agc_ul_gain_smooth_alpha; - API_SIGNED d_agc_ul_gain_smooth_alpha_fast; - API_SIGNED d_agc_ul_gain_smooth_beta; - API_SIGNED d_agc_ul_gain_smooth_beta_fast; - API_SIGNED d_agc_ul_gain_intp_flag; - #else - API d_agc_ul_holes[11]; - #endif - - #if (L1_AGC_DL == 1) - // AGC downlink - API d_agc_dl_control; - API d_agc_dl_frame_size; - API_SIGNED d_agc_dl_targeted_level; - API_SIGNED d_agc_dl_signal_up; - API_SIGNED d_agc_dl_signal_down; - API_SIGNED d_agc_dl_max_scale; - API_SIGNED d_agc_dl_gain_smooth_alpha; - API_SIGNED d_agc_dl_gain_smooth_alpha_fast; - API_SIGNED d_agc_dl_gain_smooth_beta; - API_SIGNED d_agc_dl_gain_smooth_beta_fast; - API_SIGNED d_agc_dl_gain_intp_flag; - #else - API d_agc_dl_holes[11]; - #endif - - #if(L1_AEC == 2) - API d_aec_mode; - API d_mu; - API d_cont_filter; - API d_scale_input_ul; - API d_scale_input_dl; - API d_div_dmax; - API d_div_swap_good; - API d_div_swap_bad; - API d_block_init; - API d_fact_vad; - API d_fact_asd_fil; - API d_fact_asd_mut; - API d_thrs_abs; - API d_es_level_max; - API d_granularity_att; - API d_coef_smooth; - - #else - - #if(L1_ANR == 1) - API d_iir_holes[1]; - - API d_anr_min_gain; - API d_anr_vad_thr; - API d_anr_gamma_slow; - API d_anr_gamma_fast; - API d_anr_gamma_gain_slow; - API d_anr_gamma_gain_fast; - API d_anr_thr2; - API d_anr_thr4; - API d_anr_thr5; - API d_anr_mean_ratio_thr1; - API d_anr_mean_ratio_thr2; - API d_anr_mean_ratio_thr3; - API d_anr_mean_ratio_thr4; - API d_anr_div_factor_shift; - API d_anr_ns_level; - #else - API d_iir_anr_hole[16]; - #endif - - #endif - -#endif //L1_IIR - - #if (L1_LIMITER == 1) - API a_lim_mul_low[2]; // 0x15D7 - API a_lim_mul_high[2]; - API d_lim_gain_fall_q15; // 0x15DB - API d_lim_gain_rise_q15; // - API d_lim_block_size; // 0x15DD - API d_lim_nb_fir_coefs; // - API d_lim_slope_update_period; - API a_lim_filter_coefs[16]; // 0x15E0 - #else - API d_lim_hole[25]; - #endif - #if (L1_ES == 1) - API d_es_mode; // 0x15F0 - API d_es_gain_dl; - API d_es_gain_ul_1; - API d_es_gain_ul_2; - API d_es_tcl_fe_ls_thr; - API d_es_tcl_dt_ls_thr; - API d_es_tcl_fe_ns_thr; - API d_es_tcl_dt_ns_thr; - API d_es_tcl_ne_thr; - API d_es_ref_ls_pwr; - API d_es_switching_time; - API d_es_switching_time_dt; - API d_es_hang_time; - API a_es_gain_lin_dl_vect[4]; - API a_es_gain_lin_ul_vect[4]; - #else - API d_es_hole[21]; - #endif - - #if (L1_ANR == 2) - API_SIGNED d_anr_ns_level; // start address= 0x1605 - API_SIGNED d_anr_control; - API_SIGNED d_anr_tone_ene_th; - API_SIGNED d_anr_tone_cnt_th; - #else - API d_anr_hole_2[4]; - #endif //End address= 0x1608 - - #if (L1_WCM == 1) // start address= 0x1609 - API_SIGNED d_wcm_mode; - API_SIGNED d_wcm_frame_size; - API_SIGNED d_wcm_num_sub_frames; - API_SIGNED d_wcm_ratio; - API_SIGNED d_wcm_threshold; - API_SIGNED a_wcm_gain[16]; - #else - API_SIGNED d_wcm_holes[21]; - #endif - - API a_tty_holes1[24]; // 0x161E - - #if (L1_GTT == 1) - API d_tty_status; // 0x1636 - API d_ctm_detect_shift; // 0x1637 - API d_tty2x_baudot_mod_amplitude_scale; - API d_tty2x_samples_per_baudot_stop_bit; - API d_tty_reset_buffer_ul; - API d_tty_loop_ctrl; - API p_tty_loop_buffer; - API d_ctm_mod_norm; - API d_tty2x_offset_normalization; - API d_tty2x_threshold_startbit; - API d_tty2x_threshold_diff; // 0x1640 - API d_tty2x_duration_startdetect; // 0x1641 - API d_tty2x_startbit_thres; // 0x1642 - API d_tty2x_hole_init_mute_frame_count; // 0x1643 - API d_tty2x_dl_bypass_mute; // 0x1644 - #else - API a_tty_holes2[15]; - #endif - - API a_tty_fifo_holes[131]; // 0x1645 - - // New DRP Releated Variables Start Here - API a_drp_holes_1[6]; // 0x16C8 - API d_drp_apcctrl2_hole; // 0x16CE - APC control register 2 - API d_drp_afc_add_api; // 0x16CF - Address where AFC value needs to be written - API a_drp_holes_2[12]; // 0x16D0 - API a_drp_ramp[20]; // 0x16DC - Power ramp up/down in DRP registers format - API a_drp_holes_3[271]; // 0x16F0 - - - API d_dsp_write_debug_pointer; // 0x17FF - - #if (MELODY_E2) - API a_dsp_trace[SC_AUDIO_MELODY_E2_MAX_SIZE_OF_DSP_TRACE]; // 0x1800 - API a_melody_e2_instrument_wave[SC_AUDIO_MELODY_E2_MAX_SIZE_OF_INSTRUMENT]; - API a_dsp_after_trace_holes[7440-(SC_AUDIO_MELODY_E2_MAX_SIZE_OF_DSP_TRACE + SC_AUDIO_MELODY_E2_MAX_SIZE_OF_INSTRUMENT)]; - #else - API a_dsp_trace[C_DEBUG_BUFFER_SIZE]; // 0x1800; - API a_dsp_after_trace_holes[7440-C_DEBUG_BUFFER_SIZE]; // 0x1800 + C_DEBUG_BUFFER_SIZE - // In this region MP3 variables are placed + holes - #endif - - #if (L1_PCM_EXTRACTION) - API a_pcm_api_download[160]; - API a_pcm_api_upload[160]; - API a_pcm_holes1[8]; - API d_pcm_api_upload; - API d_pcm_api_download; - API d_pcm_api_error; - API a_pcm_holes2[1181]; - #else - API a_pcm_holes[1512]; - #endif - - #if REL99 - #if FF_EMR - API a_mean_cv_bep_page_0[3];//0x3AF8 - API a_mean_cv_bep_padding_0; - API a_mean_cv_bep_page_1[3]; - API a_mean_cv_bep_padding_1; - API a_emr_holes2[378]; - #endif - #else // L1_R99 - API a_emr_holes1[386]; - #endif // L1_R99 - - // SAIC related - API a_swh_hole[16]; // 0x3C7A - API d_swh_flag_ndb; // 0x3C8A - SWH (whitening) on / off flag - API d_swh_Clipping_Threshold_ndb; // 0x3C8B - Threshold to which the DSP shall clip the SNR - - // A5/3 related - API a_a5_kc[8]; // 0x3C8C - - // DCO related - API d_dco_samples_per_symbol; // 0x3C94 No. of samples per symbol (IQ pair) - API d_dco_fcw; // 0x3C95 Control word to tell the IF Frequency - API a_dco_hole[15]; // 0x3C96 Hole related to DCO - - // A5/3 related - // API a_a5_holes[801]; // 0x3CA5 - - #if ((FF_REPEATED_SACCH == 1) || (FF_REPEATED_DL_FACCH == 1 )) - API a_a5_holes[286]; // 0x3CA5 - API d_chase_comb_ctrl; // 0x3DC3 Control for the chase combine feature - API a_a5_holes1[514]; // 0x3DC4 - #else - // A5/3 related - API a_a5_holes[801]; // 0x3CA5 - #endif /* (FF_REPEATED_SACCH == 1) */ - - - - } - T_NDB_MCU_DSP; - -#elif (DSP == 34) || (DSP == 35) || (DSP == 36) || (DSP == 37) // NDB GSM +#if (DSP == 34) || (DSP == 35) || (DSP == 36) // NDB GSM typedef struct { // MISC Tasks @@ -1360,8 +519,8 @@ API d_hole_debug_amr; #endif - #if ((CHIPSET == 12) || (CHIPSET == 4) || ((CHIPSET == 10) && (OP_WCP == 1))) // Calypso+ or Perseus2 - #if (DSP == 35) || (DSP == 36) || (DSP == 37) + #if (CHIPSET == 12) + #if (DSP == 35) || (DSP == 36) API d_hole2_ndb[1]; API d_mcsi_select; #else @@ -1398,7 +557,7 @@ #elif ((ANALOG == 2) || (ANALOG == 3)) API d_vbctrl1; #endif - + API d_bbctrl; // Monitoring tasks control (MCU <- DSP) @@ -1509,9 +668,11 @@ API d_vauo_onoff; API d_vaus_vol; API d_vaud_pll; - API d_togbr2; + API d_hole3_ndb[1]; #elif ((ANALOG == 1) || (ANALOG == 2)) + API d_hole3_ndb[7]; + #endif // word used for the init of USF threshold @@ -1565,24 +726,18 @@ // GTT API mapping for DSP code 34 (for test only) #if (L1_GTT == 1) API d_tty_status; + API d_tty_detect_thres; API d_ctm_detect_shift; - API d_tty2x_baudot_mod_amplitude_scale; - API d_tty2x_samples_per_baudot_stop_bit; + API d_tty_fa_thres; + API d_tty_mod_norm; API d_tty_reset_buffer_ul; API d_tty_loop_ctrl; API p_tty_loop_buffer; - API d_ctm_mod_norm; - API d_tty2x_offset_normalization; - API d_tty2x_threshold_startbit; - API d_tty2x_threshold_diff; - API d_tty2x_duration_startdetect; - API d_tty2x_startbit_thres; #else - API a_tty_holes[13]; + API a_tty_holes[8]; #endif - API a_sr_holes0[409]; - + API a_sr_holes0[414]; #if (L1_NEW_AEC) // new AEC @@ -1604,9 +759,6 @@ // Speech recognition model API a_sr_holes1[145]; - - // Correction of PR G23M/L1_MCU-SPR-15494 - #if ((CHIPSET == 12) || (CHIPSET == 4) || (CODE_VERSION == SIMULATION)) API d_cport_init; API d_cport_ctrl; API a_cport_cfr[2]; @@ -1617,9 +769,6 @@ API d_cport_reg_value; API a_cport_holes[1011]; - #else // CHIPSET != 12 - API a_cport_holes[1020]; - #endif // CHIPSET == 12 API a_model[1041]; @@ -1643,17 +792,15 @@ #else API a_voice_memo_amr_holes[1]; #endif - API d_thr_onset_afs; // thresh detection ONSET AFS - API d_thr_sid_first_afs; // thresh detection SID_FIRST AFS - API d_thr_ratscch_afs; // thresh detection RATSCCH AFS - API d_thr_update_afs; // thresh detection SID_UPDATE AFS - API d_thr_onset_ahs; // thresh detection ONSET AHS - API d_thr_sid_ahs; // thresh detection SID frames AHS - API d_thr_ratscch_marker; // thresh detection RATSCCH MARKER - API d_thr_sp_dgr; // thresh detection SPEECH DEGRADED/NO_DATA - API d_thr_soft_bits; - - #if ((CODE_VERSION == SIMULATION) || (DSP != 37)) + API d_thr_onset_afs; // thresh detection ONSET AFS + API d_thr_sid_first_afs; // thresh detection SID_FIRST AFS + API d_thr_ratscch_afs; // thresh detection RATSCCH AFS + API d_thr_update_afs; // thresh detection SID_UPDATE AFS + API d_thr_onset_ahs; // thresh detection ONSET AHS + API d_thr_sid_ahs; // thresh detection SID frames AHS + API d_thr_ratscch_marker;// thresh detection RATSCCH MARKER + API d_thr_sp_dgr; // thresh detection SPEECH DEGRADED/NO_DATA + API d_thr_soft_bits; #if (MELODY_E2) API d_melody_e2_osc_stop; API d_melody_e2_osc_active; @@ -1662,136 +809,25 @@ API d_melody_e2_globaltimefactor; API a_melody_e2_instrument_ptr[8]; API d_melody_e2_deltatime; - #else - API d_melody_e2_holes[61]; - #endif - #else // (DSP == 37) - API a_amrschd_debug[30]; // 0x1500 - #if (W_A_AMR_THRESHOLDS) - API a_d_macc_thr_afs[8]; // 0x151E - API a_d_macc_thr_ahs[6]; // 0x1526 - #else - API a_d_macc_thr_holes[14]; // 0x151E - #endif - API d_melody_e2_holes[17]; //0x152C - This is not a melody E2 hole; But named like that; - #endif - - #if ((CHIPSET == 12) || (CHIPSET == 4) || ((CHIPSET == 10) && (OP_WCP == 1)) || (CODE_VERSION == SIMULATION)) // Calypso+ or Perseus2 or Samson - API d_vol_ul_level; - API d_vol_dl_level; - API d_vol_speed; - API d_sidetone_level; - - // Audio control area - API d_es_ctrl; - API d_anr_ul_ctrl; - - #if ((DSP == 36) || (DSP == 37)) - - API d_aqi_ctrl_hole1_1[3]; - #if (L1_SAIC != 0) - API d_swh_flag_ndb; - API d_swh_Clipping_Threshold_ndb; - #else - API d_swh_hole[2]; - #endif - API d_aqi_ctrl_hole1_2[1]; + + #if (AMR_THRESHOLDS_WORKAROUND) + API a_d_macc_thr_afs[8]; + API a_d_macc_thr_ahs[6]; #else - API d_aqi_ctrl_hole1[6]; // Reserved for future UL modules - #endif - API d_iir_dl_ctrl; - API d_lim_dl_ctrl; - API d_aqi_ctrl_hole2[4]; // Reserved for future DL modules - API d_aqi_status; - - #if (L1_IIR == 1) - API d_iir_input_scaling; - API d_iir_fir_scaling; - API d_iir_input_gain_scaling; - API d_iir_output_gain_scaling; - API d_iir_output_gain; - API d_iir_feedback; - API d_iir_nb_iir_blocks; - API d_iir_nb_fir_coefs; - API a_iir_iir_coefs[80]; - API a_iir_fir_coefs[32]; - #else - API d_iir_hole[120]; + API a_melody_e2_holes0[14]; #endif - #if (L1_ANR == 1) - API d_anr_min_gain; - API d_anr_vad_thr; - API d_anr_gamma_slow; - API d_anr_gamma_fast; - API d_anr_gamma_gain_slow; - API d_anr_gamma_gain_fast; - API d_anr_thr2; - API d_anr_thr4; - API d_anr_thr5; - API d_anr_mean_ratio_thr1; - API d_anr_mean_ratio_thr2; - API d_anr_mean_ratio_thr3; - API d_anr_mean_ratio_thr4; - API d_anr_div_factor_shift; - API d_anr_ns_level; - #else - API d_anr_hole[15]; - #endif - - #if (L1_LIMITER == 1) - API a_lim_mul_low[2]; - API a_lim_mul_high[2]; - API d_lim_gain_fall_q15; - API d_lim_gain_rise_q15; - API d_lim_block_size; - API d_lim_nb_fir_coefs; - API d_lim_slope_update_period; - API a_lim_filter_coefs[16]; - #else - API d_lim_hole[25]; - #endif - #if (L1_ES == 1) - API d_es_mode; - API d_es_gain_dl; - API d_es_gain_ul_1; - API d_es_gain_ul_2; - API d_es_tcl_fe_ls_thr; - API d_es_tcl_dt_ls_thr; - API d_es_tcl_fe_ns_thr; - API d_es_tcl_dt_ns_thr; - API d_es_tcl_ne_thr; - API d_es_ref_ls_pwr; - API d_es_switching_time; - API d_es_switching_time_dt; - API d_es_hang_time; - API a_es_gain_lin_dl_vect[4]; - API a_es_gain_lin_ul_vect[4]; - #else - API d_es_hole[21]; - #endif - - #else // CALYPSO+ or PERSEUS2 - API a_calplus_holes[200]; - #endif - - #if (W_A_AMR_THRESHOLDS) - API d_holes[492]; - #if (CODE_VERSION == SIMULATION) || (DSP != 37) - API a_d_macc_thr_afs[8]; // In ROM37 this is moved from 0x17F1 to 0x151E - API a_d_macc_thr_ahs[6]; - #else - API d_holes_rom37[14]; // In ROM37 this is moved from 0x17F1 to 0x151E - #endif - API d_one_hole[1]; - #else - API d_holes[507]; - #endif - - #if (MELODY_E2) + API a_melody_e2_holes1[693]; API a_dsp_trace[SC_AUDIO_MELODY_E2_MAX_SIZE_OF_DSP_TRACE]; API a_melody_e2_instrument_wave[SC_AUDIO_MELODY_E2_MAX_SIZE_OF_INSTRUMENT]; + #else + API d_holes[61]; + #if (AMR_THRESHOLDS_WORKAROUND) + API a_d_macc_thr_afs[8]; + API a_d_macc_thr_ahs[6]; + #endif #endif + } T_NDB_MCU_DSP; #elif (DSP == 33) // NDB GSM @@ -2186,7 +1222,7 @@ #endif API d_bbctrl; - #else + #else #error DSPCODE not supported with given ANALOG #endif //(ANALOG)1, 2 //...................................(MCU -> DSP). @@ -2271,12 +1307,12 @@ #if (L1_EOTD ==1) API a_eotd_hole[369]; - API d_eotd_first; - API d_eotd_max; - API d_eotd_nrj_high; - API d_eotd_nrj_low; - API a_eotd_crosscor[18]; - #endif + API d_eotd_first; + API d_eotd_max; + API d_eotd_nrj_high; + API d_eotd_nrj_low; + API a_eotd_crosscor[18]; +#endif #endif } T_NDB_MCU_DSP; @@ -2414,8 +1450,8 @@ #endif API d_bbctrl; - #else - #error DSPCODE not supported with given ANALOG + #else + #error DSPCODE not supported with given ANALOG #endif //(ANALOG)1, 2 //...................................(MCU -> DSP). API a_sch26[5]; // Header + SB information, array of 5 words. @@ -2503,10 +1539,10 @@ T_NDB_MCU_DSP; #endif -#if (DSP >= 34) +#if (DSP == 34) || (DSP == 35) || (DSP == 36) typedef struct { - API_SIGNED d_transfer_rate; // 0x0C31 + API_SIGNED d_transfer_rate; // Common GSM/GPRS // These words specified the latencies to applies on some peripherics @@ -2522,10 +1558,10 @@ API_SIGNED d_cn_sw_workaround; - API_SIGNED d_hole2_param[4]; // 0x0C39 + API_SIGNED d_hole2_param[4]; //...................................Frequency Burst. - API_SIGNED d_fb_margin_beg; // 0x0C3D + API_SIGNED d_fb_margin_beg; API_SIGNED d_fb_margin_end; API_SIGNED d_nsubb_idle; API_SIGNED d_nsubb_dedic; @@ -2554,7 +1590,7 @@ API_SIGNED d_v42b_reset_delay; //...................................TCH Half Speech. - API_SIGNED d_ldT_hr; // 0x0C53 + API_SIGNED d_ldT_hr; API_SIGNED d_maccthresh_hr; API_SIGNED d_maccthresh1_hr; API_SIGNED d_gu_hr; @@ -2574,7 +1610,7 @@ API_SIGNED c_attmax_efr; //...................................CHED - API_SIGNED d_sd_min_thr_tchfs; // 0x0C63 + API_SIGNED d_sd_min_thr_tchfs; API_SIGNED d_ma_min_thr_tchfs; API_SIGNED d_md_max_thr_tchfs; API_SIGNED d_md1_max_thr_tchfs; @@ -2601,10 +1637,10 @@ API_SIGNED d_mabfi_min_thr_tchhs; // FACCH module - API_SIGNED d_facch_thr; // 0x0C79 + API_SIGNED d_facch_thr; // IDS module - API_SIGNED d_max_ovsp_ul; // + API_SIGNED d_max_ovsp_ul; API_SIGNED d_sync_thres; API_SIGNED d_idle_thres; API_SIGNED d_m1_thres; @@ -2613,7 +1649,7 @@ // FIR coefficients API a_fir_holes[4]; - API a_fir31_uplink[31]; // 0x0C84 + API a_fir31_uplink[31]; API a_fir31_downlink[31]; } T_PARAM_MCU_DSP; @@ -2879,10 +1915,10 @@ UWORD8 fn_in_report; // FN modulo 102 or 104. UWORD16 fn_mod42432; // FN modulo 42432. UWORD8 fn_mod13; // FN modulo 13. - UWORD8 fn_mod13_mod4; // FN modulo 13 modulo 4. #if L1_GPRS UWORD8 fn_mod52; // FN modulo 52. UWORD8 fn_mod104; // FN modulo 104. + UWORD8 fn_mod13_mod4; // FN modulo 13 modulo 4. UWORD32 block_id; // Block ID #endif } @@ -2982,55 +2018,6 @@ } T_SMEAS; - -#if REL99 -#if FF_EMR - typedef struct - { - - WORD16 rxlev_val_acc; // Accumulated value of RXLEV_VAL - UWORD8 rxlev_val_nbr_meas; // Number of RXLEV_VAL value accumulated on block bases - UWORD8 nbr_rcvd_blocks; // Number of correctly decoded blocks excluding SACCH FACCH etc Refer 05.08 - UWORD32 mean_bep_block_acc; // Accumulated value of MEAN_BEP - UWORD16 cv_bep_block_acc; // Accumulated value of CV_BEP - UWORD8 mean_bep_block_num; // Number of blocks over MEAN_BEP is accumulated. - UWORD8 cv_bep_block_num; // Number of blocks over CV_BEP is accumulated. - } - T_SMEAS_EMR; - - typedef struct - { - UWORD8 task; // task id (TCHTH, TCHTF, DDL, ADL, TCHA) - UWORD8 burst_id; // burst ID only used for SDCCH. - UWORD8 channel_mode; // channel mode in case of half / full rate - UWORD8 subchannel; // subchannel number - UWORD32 normalised_fn_mod13_mod4; // used to find block boundary in case of half rate - BOOL facch_present; // necessary for processing to indicate reception of Facch - BOOL facch_fire1; // necessary for processing to indicate good/bad reception of Facch - UWORD8 a_ntd; // used for Data : FCS OK/FCS KO - UWORD8 a_dd_0_blud; // check data/speech block presence on sub 0 - UWORD8 a_dd_0_bfi; // check data/speech block integrity on sub 0 - UWORD8 a_dd_1_blud; // check data/speech block presence on sub 1 - UWORD8 a_dd_1_bfi; // check data/speech block integrity on sub 1 - UWORD8 b_m1; // used for Data 14.4 M1 = 1 for second half block RLP - UWORD8 b_f48blk_dl; // used for Data 4.8 : = 1 for second half block RLP - UWORD8 b_ce; // used for Data : transparent / not transparent - UWORD8 a_cd_fire1; // check SDCCH bloch integrity - UWORD8 sid_present_sub0; // check sid present on sub 0 - UWORD8 sid_present_sub1; // check sid present on sub 1 - #if (AMR ==1) - BOOL amr_facch_present; // necessary for AMR processing to indicate reception of Facch - BOOL amr_facch_fire1; // necessary for AMR processing to indicate good/bad reception of Facch - UWORD8 b_ratscch_blud; // check ratscch present - UWORD8 ratscch_rxtype; // check type of AMR block - UWORD8 amr_rx_type_sub0; // AMR type on sub 0 - UWORD8 amr_rx_type_sub1; // AMR type on sub 1 - #endif - } - T_EMR_PARAMS; -#endif //FF_EMR -#endif //REL99 - /***************************************************************************************/ /* */ /***************************************************************************************/ @@ -3115,13 +2102,13 @@ UWORD8 ms_ctrl_d; UWORD8 ms_ctrl_dd; - UWORD8 used_il [C_BA_PM_MEAS]; - UWORD8 used_il_d [C_BA_PM_MEAS]; - UWORD8 used_il_dd[C_BA_PM_MEAS]; - - UWORD8 used_lna [C_BA_PM_MEAS]; - UWORD8 used_lna_d [C_BA_PM_MEAS]; - UWORD8 used_lna_dd[C_BA_PM_MEAS]; + UWORD8 used_il [2]; + UWORD8 used_il_d [2]; + UWORD8 used_il_dd[2]; + + UWORD8 used_lna [2]; + UWORD8 used_lna_d [2]; + UWORD8 used_lna_dd[2]; T_MEAS_INFO A[32+1]; // list of 32 neighbors + 1 serving. @@ -3237,14 +2224,6 @@ WORD32 ho_acc_to_send; // Set to 4 for SYNC HO and to -1 for ASYNC HO. UWORD8 t3124; // Timer used in Async. Ho. -#if ((REL99 == 1) && (FF_BHO == 1)) - // For blind handover... - BOOL report_time_diff; - BOOL nci; - UWORD8 real_time_difference; - WORD32 HO_SignalCode; -#endif - // For DPAGC algorithms purpose UWORD8 G_all[DPAGC_FIFO_LEN]; UWORD8 G_DTX[DPAGC_FIFO_LEN]; @@ -3299,15 +2278,6 @@ BOOL handover_fail_mode; // Flag used to indicate that the L1 wait for an handover fail request #if (AMR == 1) BOOL sync_amr; // Flag used to tell to the DSP that a new AMR paramters is ready in the NDB. - #endif // (AMR == 1) - - #if ((REL99 == 1) && (FF_BHO == 1)) - // For blind handover... - BOOL handover_type; - BOOL long_rem_handover_type; - UWORD16 bcch_carrier_of_nbr_cell; - UWORD32 fn_offset; - UWORD32 time_alignment; #endif } T_DEDIC_PARAM; @@ -3333,10 +2303,6 @@ UWORD8 Os_ticks_required; // TRUE : Os ticks to recover UWORD8 frame_adjust; // TRUE : adjust 1 frame UWORD32 sleep_duration; // sleep duration computed at wakeup - UWORD32 wakeup_time; // frame number of last wakeup - UWORD16 wake_up_int_id; // Interrupt waking up the target - UWORD8 wakeup_type; // Type of the interrupt - UWORD8 why_big_sleep; // Type of the big sleep // flag for sleep .... UWORD8 sleep_performed; // NONE,SMALL,BIG,DEEP,ALL @@ -3355,9 +2321,10 @@ // trace gauging parameters UWORD8 state; // state of the gauging UWORD32 lf; // Number of the 32KHz - UWORD32 hf; // HF: nb_hf( Number of the 13MHz *6 ) - UWORD32 root; // root & frac: the ratio of the HF & LF in each state. - UWORD32 frac; + UWORD32 hf; // HF: nb_hf( Number of the 13MHz *6 ) + UWORD32 root; // root & frac: the ratio of the HF & LF in each state. + UWORD32 frac; + } T_POWER_MNGT; @@ -3387,28 +2354,6 @@ T_L1S_RECOVER; #endif -#if (TOA_ALGO == 2) - typedef struct - { - WORD16 toa_shift; // TOA, value used to update the TOA - UWORD8 toa_snr_mask; // TOA, mask counter to reject TOA/SNR results. - BOOL toa_update_flag; // FLAG used to indicate when to the TOA module when to update TOA. - // NOTE: Flag set to TRUE in l1s_synch() and reset to FALSE in l1ctl_toa() - UWORD16 toa_frames_counter; // TOA Frames counter - Number of the TDMA frames (or bursts) which are used for TOA - // updation OR number of times l1ctl_toa() function is invoked - // Reset every TOA_PERIOD_LEN[l1_mode] frames - UWORD16 toa_accumul_counter; // Number of TDMA frames (or bursts) which are actually used for TOA tracking - // <= toa_frames_counter, as only if SNR>0.46875 TOA estimated by DSP is used to - // update the tracking algorithm - WORD16 toa_accumul_value; // TOA_tracking_value accumulated over 'toa_accumul_counter' frames - // Based on this value the shift to be applied is decided - UWORD32 toa_update_fn; // a counter which is in direct relation to l1s.actual_time.fn - // and used for TOA tracking in ALL MODES every 433 MF's (approx. 2 seconds) - - }T_TOA_ALGO; -#endif - - /***************************************************************************************/ /* L1S global variable structure... */ /***************************************************************************************/ @@ -3440,15 +2385,11 @@ //----------------------------------------- UWORD32 afc_frame_count; // AFC, Frame count between 2 calls to afc control function. WORD16 afc; // AFC, Common Frequency controle. -#if (TOA_ALGO == 2) - T_TOA_ALGO toa_var; -#else WORD16 toa_shift; // TOA, value used to update the TOA UWORD8 toa_snr_mask; // TOA, mask counter to reject TOA/SNR results. UWORD16 toa_period_count; // TOA frame period used in PACKET TRANSFER MODE BOOL toa_update; // TOA, is set at the end of the update period, toa update occurs on next valid frame -#endif // Flag registers for RF task controle... //----------------------------------------- @@ -3493,9 +2434,10 @@ T_GTT_TEST_L1S gtt_test; #endif #endif - #if (L1_DYN_DSP_DWNLD == 1) - UWORD8 dyn_dwnld_state; // state for L1S DYN DWNLD manager - #endif // L1_DYN_DSP_DWNLD + + #if (L1_DYN_DSP_DWNLD == 1) + UWORD8 dyn_dwnld_state; // state for L1S DYN DWNLD manager + #endif #if (AUDIO_TASK == 1) // Audio task. //----------------------------------------- @@ -3508,16 +2450,13 @@ #if (VOICE_MEMO) T_L1S_VM_TASK voicememo; #endif - #if (L1_PCM_EXTRACTION) - T_L1S_PCM_TASK pcm; - #endif #if (L1_VOICE_MEMO_AMR) T_L1S_VM_AMR_TASK voicememo_amr; #endif #if (SPEECH_RECO) T_L1S_SR_TASK speechreco; #endif - #if (L1_AEC == 1) + #if (AEC) T_L1S_AEC_TASK aec; #endif #if (MELODY_E2) @@ -3525,115 +2464,29 @@ T_L1S_MELODY_E2_TASK melody0_e2; T_L1S_MELODY_E2_TASK melody1_e2; #endif - #if (L1_EXT_AUDIO_MGT == 1) - T_L1S_EXT_AUDIO_MGT_VAR ext_audio_mgt; - #endif - #if (L1_WCM == 1) - T_WCM_ACTION wcm_action; - #endif - #if (L1_AGC_UL == 1) - T_AGC_ACTION agc_ul_action; - #endif - #if (L1_AGC_DL == 1) - T_AGC_ACTION agc_dl_action; - #endif - #if (L1_ANR == 2) - T_ANR_ACTION anr_ul_action; - #endif - #if (L1_IIR == 2) - T_IIR_ACTION iir_dl_action; - #endif - #if (L1_DRC == 1) - T_DRC_ACTION drc_dl_action; - #endif - #endif UWORD8 last_used_txpwr; #if L1_GPRS BOOL ctrl_synch_before; //control of synchro for CCCH reading en TN-2 - UWORD32 next_gauging_scheduled_for_PNP; // gauging for Packet Idle #endif #if L1_RECOVERY T_L1S_RECOVER recovery; #endif BOOL spurious_fb_detected; - + // Handling DTX mode - BOOL dtx_ul_on; //earlier name was- dtx_on + BOOL dtx_ul_on; WORD8 facch_bursts; + // DTX mode in AMR BOOL dtx_amr_dl_on; // set to TRUE when the AMR is in DTX mode in downlink - //+++++++++++++++++ - // GSM IDLE IN RAM - //+++++++++++++++++ - - #if (GSM_IDLE_RAM != 0) - T_L1S_GSM_IDLE_INTRAM gsm_idle_ram_ctl; - - #if (GSM_IDLE_RAM == 1) - // Used to avoid allocation of ext mem data while in L1S_meas_manager (allocate signal long time before sending) - T_RXLEV_MEAS A[8]; - #endif - #endif - - //+++++++++++++++++ - // Triton Audio ON/OFF Changes - //+++++++++++++++++ -#if (L1_AUDIO_MCU_ONOFF == 1) - T_L1S_AUDIO_ONOFF_MANAGER audio_on_off_ctl; -#endif - -#if (ANALOG == 11) -UWORD8 abb_write_done; -#endif -UWORD8 tcr_prog_done; - -#if (L1_RF_KBD_FIX == 1) -UWORD16 total_kbd_on_time; -UWORD8 correction_ratio; //KPD_CORRECTION_RATIO correction_ratio;//omaps00090550 -#endif -#if (L1_GPRS == 1) -BOOL algo_change_synchro_active; -#endif /* FF_L1_FAST_DECODING */ -#if (FF_REPEATED_SACCH == 1) - // Repeated SACCH mode - T_REPEAT_SACCH repeated_sacch; -#endif /* FF_REPEATED_SACCH */ -#if (FF_REPEATED_DL_FACCH == 1) - // Repeated FACCH mode - T_REPEAT_FACCH repeated_facch; -#endif /* FF_REPEATED_DL_FACCH == 1 */ -/* 0 indicates success, non zero value indicates failure */ - UWORD8 boot_result; - //Nina modify to save power, not forbid deep sleep, only force gauging in next paging - UWORD8 force_gauging_next_paging_due_to_CCHR; - } T_L1S_GLOBAL; -#if (AUDIO_TASK == 1) -#if (L1_VOCODER_IF_CHANGE == 1) - typedef struct - { - BOOL enabled; // TRUE if enabled, FALSE if disabled - BOOL automatic_disable; // TRUE if vocoders are automatically disabld via a MPHC_STOP_DEDICATED_REQ, FALSE otherwise. - } T_L1A_VOCODER_CFG_GLOBAL; -#endif // L1_VOCODER_IF_CHANGE == 1 - typedef struct - { - UWORD8 outen1; - UWORD8 outen2; - UWORD8 outen3; - UWORD8 classD; - UWORD8 command_requested; /* updated in L1a task context*/ - UWORD8 command_commited; /* updated in I2c ISR callback context*/ - } T_OUTEN_CFG_TASK; - -#endif // AUDIO_TASK == 1 /***************************************************************************************/ /* L1A global variable structure... */ /***************************************************************************************/ @@ -3651,48 +2504,19 @@ //--------------------------------------------- UWORD8 l1_msg_forwarded; - #if (L1_DYN_DSP_DWNLD == 1) - // Dynamic donload global variables - T_L1A_DYN_DWNLD_GLOBAL dyn_dwnld; - #endif - - // New Vocoder IF global L1A variable: L1A checks if the vocoder has already been enabled/disabled - // in order to robust to possible multiples enabling/disabling messages coming from PS - - #if (L1_VOCODER_IF_CHANGE == 1) - T_L1A_VOCODER_CFG_GLOBAL vocoder_state; - #endif // L1_VOCODER_IF_CHANGE == 1 +#if (L1_DYN_DSP_DWNLD == 1) + // Dynamic donload global variables + T_L1A_DYN_DWNLD_GLOBAL dyn_dwnld; +#endif // signal code indicating the reason of L1C_DEDIC_DONE UWORD32 confirm_SignalCode; -#if (L1_MP3 == 1) - T_L1_MP3_L1A mp3_task; -//ADDED FOR AAC -#endif - -#if (L1_AAC == 1) - T_L1_AAC_L1A aac_task; -#endif -#if(L1_IIR == 2) - xSignalHeaderRec *iir_req_msg_ptr; + // Trace the best frequencies reported in MPHC_RXLEV_IND +#if (L1_MPHC_RXLEV_IND_REPORT_SORT==1) + UWORD16 tab_index[MAX_MEAS_RXLEV_IND_TRACE]; + UWORD16 max_report; //max number of fq reported, can be < MAX_MEAS_RXLEV_IND_TRACE if list is smaller #endif - -#if(L1_DRC == 1) - xSignalHeaderRec *drc_req_msg_ptr; -#endif - -#if(L1_WCM == 1) - xSignalHeaderRec *wcm_req_msg_ptr; -#endif - -#if(L1_CHECK_COMPATIBLE == 1) - BOOL vcr_wait; - BOOL stop_req; - BOOL vcr_msg_param; - BOOL vch_auto_disable; -#endif - } T_L1A_GLOBAL; @@ -3720,10 +2544,6 @@ // Synchro information. //--------------------------------------- - #if L1_FF_WA_OMAPS00099442 - BOOL change_tpu_offset_flag; - #endif - WORD8 tn_difference; // Timeslot difference for next synchro. UWORD8 dl_tn; // Current timeslot for downlink stuffs. #if L1_GPRS @@ -3768,13 +2588,8 @@ // TXPWR management. //------------------- - #if (L1_FF_MULTIBAND == 0) UWORD8 powerclass_band1; // Power class for the MS, given in ACCESS LINK mode (GSM Band). UWORD8 powerclass_band2; // Power class for the MS, given in ACCESS LINK mode (DCS Band). - #else - UWORD8 powerclass[RF_NB_SUPPORTED_BANDS]; - #endif - // Dedicated parameters. //---------------------- @@ -3793,11 +2608,6 @@ T_FULL_LIST full_list; T_FULL_LIST_MEAS *full_list_ptr; -#if ((REL99 == 1) && (FF_BHO == 1)) - // For blind handover... - T_BHO_PARAM nsync_fbsb; -#endif - //+++++++++++++++++++ // L1S scheduler... //+++++++++++++++++++ @@ -3847,19 +2657,13 @@ #if (VOICE_MEMO) T_VM_TASK voicememo_task; #endif - #if (L1_PCM_EXTRACTION) - T_PCM_TASK pcm_task; - #endif #if (L1_VOICE_MEMO_AMR) T_VM_AMR_TASK voicememo_amr_task; #endif #if (SPEECH_RECO) T_SR_TASK speechreco_task; #endif - #if (L1_AEC == 1) - T_AEC_TASK aec_task; - #endif - #if (L1_AEC == 2) + #if (AEC) T_AEC_TASK aec_task; #endif #if (FIR) @@ -3875,82 +2679,8 @@ #if (L1_CPORT == 1) T_CPORT_TASK cport_task; #endif - - #if (L1_EXTERNAL_AUDIO_VOICE_ONOFF == 1 || L1_EXT_MCU_AUDIO_VOICE_ONOFF == 1) - T_AUDIO_ONOFF_TASK audio_onoff_task; - #endif - - BOOL audio_forced_by_l1s; /* This value is used to indicate if the L1S is forcing the audio_on_off feature in the DSP CQ21718 */ - - #if (L1_STEREOPATH == 1) - T_STEREOPATH_DRV_TASK stereopath_drv_task; - #endif - - #if (L1_MP3 == 1) - T_MP3_TASK mp3_task; - #endif - - #if (L1_MIDI == 1) - T_MIDI_TASK midi_task; - #endif -//ADDED FOR AAC - #if (L1_AAC == 1) - T_AAC_TASK aac_task; - #endif - - #if (L1_ANR == 1) - T_ANR_TASK anr_task; - #endif - - #if (L1_ANR == 2) - T_AQI_ANR_TASK anr_task; - #endif - - #if (L1_IIR == 1) - T_IIR_TASK iir_task; - #endif - - #if (L1_AGC_UL == 1) - T_AQI_AGC_UL_TASK agc_ul_task; - #endif - - #if (L1_AGC_DL == 1) - T_AQI_AGC_DL_TASK agc_dl_task; - #endif - - #if (L1_IIR == 2) - T_AQI_IIR_TASK iir_task; - #endif - - #if (L1_DRC == 1) - T_AQI_DRC_TASK drc_task; - #endif - - #if (L1_LIMITER == 1) - T_LIMITER_TASK limiter_task; - #endif - - #if (L1_ES == 1) - T_ES_TASK es_task; - #endif - - #if (L1_WCM == 1) - T_AQI_WCM_TASK wcm_task; - #endif - - //++++++++++++++++++++++++++++++++++++ - // Fake L1S sm for audio IT generation - //++++++++++++++++++++++++++++++++++++ - T_AUDIOIT_TASK audioIt_task; - - /* - * FreeCalypso change: I had to move this part here, or else - * compilation fails w/o AUDIO_TASK - */ - T_OUTEN_CFG_TASK outen_cfg_task; #endif - //+++++++++++++ // GTT task //+++++++++++++ @@ -3960,19 +2690,9 @@ #endif // Dynamic DSP download task - #if (L1_DYN_DSP_DWNLD == 1) - T_DYN_DWNLD_TASK_COMMAND dyn_dwnld_task; - #endif - - #if REL99 - #if FF_EMR - T_SMEAS_EMR Smeas_dedic_emr; - #endif - #endif - - #if (FF_L1_FAST_DECODING == 1) - UWORD8 last_fast_decoding; - #endif /* if (FF_L1_FAST_DECODING == 1) */ + #if (L1_DYN_DSP_DWNLD == 1) + T_DYN_DWNLD_TASK_COMMAND dyn_dwnld_task; + #endif } T_L1A_L1S_COM; @@ -3988,9 +2708,6 @@ T_DB_DSP_TO_MCU *dsp_db_r_ptr; // MCU<->DSP comm. read page (Double Buffered comm. memory). T_DB_MCU_TO_DSP *dsp_db_w_ptr; // MCU<->DSP comm. write page (Double Buffered comm. memory). - #if (DSP ==38) || (DSP == 39) - T_DB_COMMON_MCU_TO_DSP *dsp_db_common_w_ptr; // MCU<->DSP comm. common write page (Double Buffered comm. memory). - #endif T_NDB_MCU_DSP *dsp_ndb_ptr; // MCU<->DSP comm. read/write (Non Double Buffered comm. memory). T_PARAM_MCU_DSP *dsp_param_ptr; // MCU<->DSP comm. read/write (Param comm. memory). @@ -3999,12 +2716,6 @@ T_DB2_DSP_TO_MCU *dsp_db2_current_r_ptr; T_DB2_DSP_TO_MCU *dsp_db2_other_r_ptr; #endif - - /* DSP CPU load measurement */ - /* FreeCalypso change: the necessary #if was missing */ - #if (DSP == 38) || (DSP == 39) - T_DB_MCU_TO_DSP_CPU_LOAD *dsp_cpu_load_db_w_ptr; - #endif } T_L1S_DSP_COM; @@ -4028,7 +2739,6 @@ /***************************************************************************************/ /* L1 configuration structure */ /***************************************************************************************/ -#if (L1_FF_MULTIBAND == 0) typedef struct { @@ -4064,48 +2774,6 @@ } T_L1_STD_CNFG; -#endif // #if (L1_FF_MULTIBAND == 0) - -#if (L1_FF_MULTIBAND == 1) - -#if 0 -typedef struct -{ - UWORD16 nbmax_carrier; - UWORD16 first_radio_freq; - UWORD16 first_tpu_radio_freq; - UWORD16 first_operative_radio_freq; - UWORD8 physical_band_id; -} -T_MULTIBAND_CONVERSION_DATA; - -typedef struct -{ - UWORD16 lna_switch_thr_high; - UWORD16 lna_switch_thr_low; - UWORD16 lna_att; - UWORD16 g_magic; - UWORD8 swap_iq; - UWORD16 cal_freq1; - UWORD8 tx_turning_point; - UWORD8 max_txpwr; - UWORD8 gsm_band_identifier; -} -T_MULTIBAND_RF_DATA; -#endif // if 0 -typedef struct -{ - UWORD8 radio_band; - UWORD8 power_class; - UWORD8 _align0; - UWORD8 _align1; -} -T_L1_MULTIBAND_POWER_CLASS; - - -#endif /*if (L1_FF_MULTIBAND == 1)*/ - - //RF dependent parameter definitions typedef struct { @@ -4143,7 +2811,6 @@ UWORD16 fixed_txpwr; WORD16 eeprom_afc; WORD8 setup_afc_and_rf; - WORD8 rf_wakeup_tpu_scenario_duration; // Duration (in TDMA frames) of TPU scenario for RF wakeup UWORD32 psi_sta_inv; UWORD32 psi_st; @@ -4221,28 +2888,7 @@ UWORD16 vaus_vol; UWORD16 vaud_pll; #endif - #if (ANALOG == 11) - UWORD8 vulgain; - UWORD8 vdlgain; - UWORD8 sidetone; - UWORD8 ctrl1; - UWORD8 ctrl2; - UWORD8 ctrl3; - UWORD8 ctrl4; - UWORD8 ctrl5; - UWORD8 ctrl6; - UWORD8 popauto; - UWORD8 outen1; - UWORD8 outen2; - UWORD8 outen3; - UWORD8 aulga; - UWORD8 aurga; - #endif - #if (RF_FAM == 61) - UWORD16 apcdel1; - UWORD16 apcdel2; - UWORD16 apcctrl2; - #endif + #if L1_GPRS UWORD16 toa_pm_thres; // PM threshold for TOA algorithm feeding in packet transfer mode #endif @@ -4251,157 +2897,43 @@ typedef struct { -#if (L1_FF_MULTIBAND == 0) - T_L1_STD_CNFG std; //standard: GSM,GSM_E,GSM850,DCS,PCS,DUAL,DUALEXT -#endif // L1_FF_MULTIBAND == 0 - - UWORD8 pwr_mngt; //power management active - UWORD8 tx_pwr_code; -#if IDS - UWORD8 ids_enable; -#endif - UWORD16 dwnld; - T_L1_PARAMS params; - double dpll; //dpll factor - -#if TESTMODE - //Define the TestMode flag and TestMode parameters - UWORD8 TestMode; - - UWORD8 agc_enable; - UWORD8 afc_enable; - UWORD8 adc_enable; - #if (FF_REPEATED_SACCH == 1) - UWORD8 repeat_sacch_enable; - #endif /* FF_REPEATED_SACCH == 1 */ - #if (FF_REPEATED_DL_FACCH == 1) - UWORD8 repeat_facch_dl_enable; - #endif /* (FF_REPEATED_DL_FACCH == 1)*/ - - T_TM_PARAMS tmode; //TestMode parameters structure -#endif - - T_FACCH_TEST_PARAMS facch_test; + T_L1_STD_CNFG std; //standard: GSM,GSM_E,GSM850,DCS,PCS,DUAL,DUALEXT + UWORD8 pwr_mngt; //power management active + UWORD8 tx_pwr_code; + UWORD16 dwnld; + T_L1_PARAMS params; + double dpll; //dpll factor + + #if TESTMODE + //Define the TestMode flag and TestMode parameters + UWORD8 TestMode; + + UWORD8 agc_enable; + UWORD8 afc_enable; + UWORD8 adc_enable; + + T_TM_PARAMS tmode; //TestMode parameters structure + #endif + } T_L1_CONFIG; -// SAPI identifier : 0 (Signalling), 3 (Short Messages Services) -#if FF_REPEATED_SACCH -typedef enum -{ - SAPI_0 = 0, - SAPI_3 = 3 -} T_L1_SAPI_ID; -#endif /* FF_REPEATED_SACCH */ /***************************************************************************************/ -/* API HISR -> L1A communication structure... */ +/* API HISR -> L1A communication structure... Defined in case dynamic download is defined */ +/***************************************************************************************/ /***************************************************************************************/ -#if ( (L1_MP3 == 1) || (L1_MIDI == 1) || (L1_AAC == 1) || (L1_DYN_DSP_DWNLD == 1) || (FF_L1_IT_DSP_USF == 1) ) // equivalent to an API_HISR flag - -#if FF_L1_IT_DSP_USF -typedef struct -{ - // Fast USF HISR pending - BOOL pending; -} T_L1A_USF_HISR_COM; -#endif - -#if FF_L1_IT_DSP_DTX +/* Global API HISR -Defined in case dynamic download is defined +/***************************************************************************************/ + + +#if(L1_DYN_DSP_DWNLD==1) typedef struct { - // Fast DTX HISR pending - BOOL pending; - // TX activity programmed in TCH block - BOOL tx_active; - // Fast DTX service is available - BOOL fast_dtx_ready; - // Fast DTX service latency timer - UWORD8 fast_dtx_ready_timer; - // Fast DTX state variable - UWORD8 dtx_status; -} T_L1A_DTX_HISR_COM; -#endif - -#if (FF_L1_FAST_DECODING == 1) -typedef struct -{ - /* Fast Decoding HISR pending */ - BOOL pending; - /* Current CRC */ - BOOL crc_error; - /* Status (IT awaited?) */ - UWORD8 status; - /* Control required during incoming fast API IT? */ - BOOL deferred_control_req; - /* Task using fast decoding */ - UWORD8 task; - /* Burst ID of the task */ - UWORD8 burst_id; - /* Is the decoding of a contiguous block starting? */ - BOOL contiguous_decoding; -} T_L1A_FAST_DECODING_HISR_COM; -#endif /* FF_L1_FAST_DECODING */ + T_L1A_DYN_DWNLD_HISR_COM dyn_dwnld; +} T_L1A_API_HISR_COM; typedef struct { -#if (L1_MP3 == 1) - T_L1A_MP3_HISR_COM mp3; -#endif -#if (L1_MIDI == 1) - T_L1A_MIDI_HISR_COM midi; -//ADDED FOR AAC -#endif -#if (L1_AAC == 1) - T_L1A_AAC_HISR_COM aac; -#endif -#if (L1_DYN_DSP_DWNLD == 1) - T_L1A_DYN_DWNLD_HISR_COM dyn_dwnld; -#endif // L1_DYN_DSP_DWNLD -#if (FF_L1_IT_DSP_USF == 1) - T_L1A_USF_HISR_COM usf; -#endif -#if (FF_L1_IT_DSP_DTX == 1) - T_L1A_DTX_HISR_COM dtx; -#endif -#if (FF_L1_FAST_DECODING == 1) - T_L1A_FAST_DECODING_HISR_COM fast_decoding; -#endif /* FF_L1_FAST_DECODING */ -} T_L1A_API_HISR_COM; - -#if (L1_MP3 == 1) || (L1_MIDI == 1) || (L1_AAC == 1) || (L1_DYN_DSP_DWNLD == 1) -typedef struct -{ -#if (L1_MP3 == 1) - T_L1_MP3_API_HISR mp3; + T_L1_DYN_DWNLD_API_HISR dyn_dwnld; +} T_L1_API_HISR; #endif -#if (L1_MIDI == 1) - T_L1_MIDI_API_HISR midi; -#endif -//ADDED FOR AAC -#if (L1_AAC == 1) - T_L1_AAC_API_HISR aac; -#endif -#if (L1_DYN_DSP_DWNLD == 1) - T_L1_DYN_DWNLD_API_HISR dyn_dwnld; -#endif // L1_DYN_DSP_DWNLD -} T_L1_API_HISR; -#endif // #if (L1_MP3 == 1) || (L1_MIDI == 1) || || (L1_AAC == 1) || (L1_DYN_DSP_DWNLD == 1) - -#endif //(L1_MP3 == 1) || (L1_MIDI == 1) || (L1_DYN_DSP_DWNLD == 1) || (FF_L1_IT_DSP_USF == 1) - -typedef struct -{ - /* 0 indicates success 1 indicates failure */ - UWORD16 boot_result; - UWORD16 drp_maj_ver; - UWORD16 drp_min_ver; - // MCU versions - UWORD16 mcu_tcs_program_release; - UWORD16 mcu_tcs_official; - UWORD16 mcu_tcs_internal; - // DSP versions & checksum - UWORD16 dsp_code_version; - UWORD16 dsp_patch_version; -}T_L1_BOOT_VERSION_CODE; - -
--- a/L1/include/l1_macro.h Thu Jun 09 00:19:28 2016 +0000 +++ b/L1/include/l1_macro.h Thu Jun 09 00:45:00 2016 +0000 @@ -1,17 +1,17 @@ /************* Revision Controle System Header ************* - * GSM Layer 1 software + * GSM Layer 1 software * L1_MACRO.H * * Filename l1_macro.h - * Copyright 2003 (C) Texas Instruments + * Copyright 2003 (C) Texas Instruments * ************* Revision Controle System Header *************/ #include "l1_confg.h" + #if(L1_DYN_DSP_DWNLD == 1) #include "../dyn_dwl_include/l1_dyn_dwl_const.h" #endif -#include "l1_types.h" #if (TRACE_TYPE==5) && NUCLEUS_TRACE //WARNING : this type of trace takes a lot of space in data RAM (~16kB) @@ -72,78 +72,22 @@ /************************************************************/ #define IncMod(operand, increment, modulo) \ if( (operand += increment) >= modulo ) operand -= modulo - + // Define MACRO for selecting the min. time to next task. #define Select_min_time(Task_Time, Min_Time) \ if(Task_Time < Min_Time) Min_Time = Task_Time; + /************************************************************/ /* Macros for MCU/DSP API address conversion . */ /************************************************************/ +#if(L1_DYN_DSP_DWNLD == 1) #define API_address_dsp2mcu(dsp_address) \ (MCU_API_BASE_ADDRESS + ((API)((dsp_address) - DSP_API_BASE_ADDRESS) * 2)) #define API_address_mcu2dsp(mcu_address) \ (DSP_API_BASE_ADDRESS + ((UWORD32)((mcu_address) - MCU_API_BASE_ADDRESS) / 2)) - - - - - /* Added temporirly for RF_KEypad build */ - - #if (L1_RF_KBD_FIX == 1) - - #if(OP_L1_STANDALONE == 1) - -#if 0 - typedef struct - { - // T_RVF_MB_ID prim_id; - // T_RVF_ADDR_ID addr_id; - // BOOL swe_is_initialized; - // T_RVM_RETURN (*error_ft)(T_RVM_NAME swe_name, - // T_RVM_RETURN error_cause, - // T_RVM_ERROR_TYPE error_type, - // T_RVM_STRING error_msg); - #if ((CHIPSET == 12) || (CHIPSET == 15)) - // T_KPD_RECEIVED_KEY_INFO received_key_info[KPD_MAX_DETECTABLE]; - //UINT8 nb_active_keys; - UWORD16 repeat_time; - UWORD16 long_time; - #endif - } T_KPD_ENV_CTRL_BLK_L1; - #endif -// typedef unsigned char KPD_CORRECTION_RATIO; //UWORD8 //omaps00090550 - void kpd_timer_modify(UWORD8 ratio,UWORD32 frameNumber); //omaps00090550 - #define KBR_DEBOUNCING_TIME (MEM_KEYBOARD + 0x02) /* KBR debouncing time reg */ - #define KPD_DEBOUNCING_TIME (0x3F) - #define KBR_LONG_KEY_TIME (MEM_KEYBOARD + 0x04) /* KBR long key time reg */ - #define KBR_TIME_OUT (MEM_KEYBOARD + 0x06) /* KBR Time out reg */ - #define KBR_CTRL_REG (MEM_KEYBOARD + 0x00) /* KBR control reg */ - #define KBR_STATE_MACHINE_STATUS (MEM_KEYBOARD + 0x0E) /* KBR state machine status reg */ - #define KPD_CLK_DIV32 4 - #define KPD_CLOCK_DIVIDER KPD_CLK_DIV32 - - #define SetGroupBits16(registre,position,number,value) {\ - UINT16 tmp=registre;\ - volatile UINT16 tmpvalue;\ - tmpvalue = (value<<(16-(number)));\ - tmpvalue = (tmpvalue>>(16-(number)));\ - tmp&=~((0xFFFF>>(16-(number)))<<(position));\ - tmp|=((tmpvalue&(0xFFFF>>(16-(number))))<<(position));\ - registre=tmp;\ - } - #endif/* #if(OP_L1_STANDALONE == 1) */ - - #endif /* #if (L1_RF_KBD_FIX == 1) */ - /* Added temporirly for RF_KEypad build */ - - - - - -
--- a/L1/include/l1_mftab.h Thu Jun 09 00:19:28 2016 +0000 +++ b/L1/include/l1_mftab.h Thu Jun 09 00:45:00 2016 +0000 @@ -17,594 +17,558 @@ /* Multiframe Blocks for Dynamic MFTAB Building purpose. */ /*******************************************************************************************/ // Multiframe table size.... - -#ifndef L1_MFTAB_H -#define L1_MFTAB_H - - #define BLOC_FBNEW_SIZE 14 + 2 // FB. +#define BLOC_FBNEW_SIZE 14 + 2 // FB. - #define BLOC_SB2_SIZE 5 + 2 // SB2. -#if ((REL99 == 1) && (FF_BHO == 1)) -#define BLOC_FBSB_SIZE 12 + 2 + 2 + 2 // FB + SB + AGC -#endif - #define BLOC_SBCONF_SIZE 4 + 2 // SBCONF. - #define BLOC_BCCHN_SIZE 7 + 2 // BCCHN. - #define BLOC_BCCHN_TOP_SIZE 7 + 2 // BCCHN_TOP (BCCHN top priority) +#define BLOC_SB2_SIZE 5 + 2 // SB2. - #define BLOC_SYNCHRO_SIZE 1 // SYNC. - #define BLOC_ADC_SIZE 1 // ADC in CS_MODE0 - #define BLOC_ABORT_SIZE 3 // ABORT. - #define BLOC_RAACC_SIZE 3 // RAACC. - #define S_RECT4_SIZE 6 // All "rectangular 4" serving tasks: NP/EP/BCCHS/ALLC. - #define BLOC_TCHT_SIZE 3 // TCHTF / TCHTH / TCHD. - #define BLOC_TCHA_SIZE 3 // TCHA. - #define BLOC_SMSCB_SIZE 6 // SMSCB. - #define BLOC_FB51_SIZE 14 // FB51. - #define BLOC_SB51_SIZE 4 // SB51. - #define BLOC_SBCNF51_SIZE 4 // SBCNF51. - #define BLOC_FB26_SIZE 4 // FB26. - #define BLOC_SB26_SIZE 5 // SB26. - #define BLOC_SBCNF26_SIZE 5 // SBCNF26. - #define BLOC_HWTEST_SIZE 4 // HWTEST. - #define BLOC_DUL_ADL_MIXED_SIZED 7 - #if (L1_GPRS) - #define BLOC_BCCHN_TRAN_SIZE 7 // BCCHN_TRAN. - #endif - +#define BLOC_SBCONF_SIZE 4 + 2 // SBCONF. +#define BLOC_BCCHN_SIZE 7 + 2 // BCCHN. +#define BLOC_BCCHN_TOP_SIZE 7 + 2 // BCCHN_TOP (BCCHN top priority) - - #ifdef L1_ASYNC_C - /*----------------------------------------------------*/ - /* TASK: Frequency Burst search... */ - /*----------------------------------------------------*/ - const T_FCT BLOC_FBNEW[] = - { - {l1s_ctrl_msagc,FBNEW,NO_PAR}, {NULL,NO_PAR,NO_PAR}, // frame 1 - {NULL,NO_PAR,NO_PAR}, // frame 2 - {l1s_read_msagc,FBNEW,NO_PAR},{l1s_ctrl_fb,FBNEW,NO_PAR}, {NULL,NO_PAR,NO_PAR}, // frame 3 - {NULL,NO_PAR,NO_PAR}, // frame 4 - {l1s_read_mon_result,FBNEW, 1},{NULL,NO_PAR,NO_PAR}, // frame 5 - {l1s_read_mon_result,FBNEW, 2},{NULL,NO_PAR,NO_PAR}, // frame 6 - {l1s_read_mon_result,FBNEW, 3},{NULL,NO_PAR,NO_PAR}, // frame 7 - {l1s_read_mon_result,FBNEW, 4},{NULL,NO_PAR,NO_PAR}, // frame 8 - {l1s_read_mon_result,FBNEW, 5},{NULL,NO_PAR,NO_PAR}, // frame 9 - {l1s_read_mon_result,FBNEW, 6},{NULL,NO_PAR,NO_PAR}, // frame 10 - {l1s_read_mon_result,FBNEW, 7},{NULL,NO_PAR,NO_PAR}, // frame 11 - {l1s_read_mon_result,FBNEW, 8},{NULL,NO_PAR,NO_PAR}, // frame 12 - {l1s_read_mon_result,FBNEW, 9},{NULL,NO_PAR,NO_PAR}, // frame 13 - {l1s_read_mon_result,FBNEW,10},{NULL,NO_PAR,NO_PAR}, // frame 14 - {l1s_read_mon_result,FBNEW,11},{NULL,NO_PAR,NO_PAR}, // frame 15 - {l1s_read_mon_result,FBNEW,12},{NULL,NO_PAR,NO_PAR} // frame 16 - }; - - /*----------------------------------------------------*/ - /* TASK: SB2, New Synchro Burst search... */ - /*----------------------------------------------------*/ - /* C W R -> AGC */ - /* C W W R -> 1st SB */ - /* C W W R -> 2nd SB */ - /*----------------------------------------------------*/ - const T_FCT BLOC_SB2[] = - { - {l1s_ctrl_msagc,SB2,NO_PAR}, {NULL,NO_PAR,NO_PAR}, // frame 1 - {NULL,NO_PAR,NO_PAR}, // frame 2 - {l1s_read_msagc,SB2,NO_PAR}, {l1s_ctrl_sbgen,SB2,1}, {NULL,NO_PAR,NO_PAR}, // frame 3 - {l1s_ctrl_sbgen,SB2,2}, {NULL,NO_PAR,NO_PAR}, // frame 4 - {NULL,NO_PAR,NO_PAR}, // frame 5 - {l1s_read_mon_result,SB2,1}, {NULL,NO_PAR,NO_PAR}, // frame 6 - {l1s_read_mon_result,SB2,2}, {NULL,NO_PAR,NO_PAR} // frame 7 - }; - - /*----------------------------------------------------*/ - /* TASK: SBCONF, Synchro confirmation. */ - /*----------------------------------------------------*/ - /* C W R -> AGC */ - /* C W W R -> SBCONF */ - /*----------------------------------------------------*/ - const T_FCT BLOC_SBCONF[] = - { - {l1s_ctrl_msagc,SBCONF,1}, {NULL,NO_PAR,NO_PAR}, // frame 1 - {NULL,NO_PAR,NO_PAR}, // frame 2 - {l1s_read_msagc,SBCONF,1},{l1s_ctrl_sbgen,SBCONF,1}, {NULL,NO_PAR,NO_PAR}, // frame 3 - {NULL,NO_PAR,NO_PAR}, // frame 4 - {NULL,NO_PAR,NO_PAR}, // frame 5 - {l1s_read_mon_result,SBCONF,1},{NULL,NO_PAR,NO_PAR} // frame 6 - }; +#define BLOC_SYNCHRO_SIZE 1 // SYNC. +#define BLOC_ADC_SIZE 1 // ADC in CS_MODE0 +#define BLOC_ABORT_SIZE 3 // ABORT. +#define BLOC_RAACC_SIZE 3 // RAACC. +#define S_RECT4_SIZE 6 // All "rectangular 4" serving tasks: NP/EP/BCCHS/ALLC. +#define BLOC_TCHT_SIZE 3 // TCHTF / TCHTH / TCHD. +#define BLOC_TCHA_SIZE 3 // TCHA. +#define BLOC_SMSCB_SIZE 6 // SMSCB. +#define BLOC_FB51_SIZE 14 // FB51. +#define BLOC_SB51_SIZE 4 // SB51. +#define BLOC_SBCNF51_SIZE 4 // SBCNF51. +#define BLOC_FB26_SIZE 4 // FB26. +#define BLOC_SB26_SIZE 5 // SB26. +#define BLOC_SBCNF26_SIZE 5 // SBCNF26. +#define BLOC_HWTEST_SIZE 4 // HWTEST. +#define BLOC_DUL_ADL_MIXED_SIZED 7 +#if (L1_GPRS) + #define BLOC_BCCHN_TRAN_SIZE 7 // BCCHN_TRAN. +#endif -#if ((REL99 == 1) && (FF_BHO == 1)) + +#ifdef L1_ASYNC_C + /*----------------------------------------------------*/ + /* TASK: Frequency Burst search... */ + /*----------------------------------------------------*/ + const T_FCT BLOC_FBNEW[] = + { + {l1s_ctrl_msagc,FBNEW,NO_PAR}, {NULL,NO_PAR,NO_PAR}, // frame 1 + {NULL,NO_PAR,NO_PAR}, // frame 2 + {l1s_read_msagc,FBNEW,NO_PAR},{l1s_ctrl_fb,FBNEW,NO_PAR}, {NULL,NO_PAR,NO_PAR}, // frame 3 + {NULL,NO_PAR,NO_PAR}, // frame 4 + {l1s_read_mon_result,FBNEW, 1},{NULL,NO_PAR,NO_PAR}, // frame 5 + {l1s_read_mon_result,FBNEW, 2},{NULL,NO_PAR,NO_PAR}, // frame 6 + {l1s_read_mon_result,FBNEW, 3},{NULL,NO_PAR,NO_PAR}, // frame 7 + {l1s_read_mon_result,FBNEW, 4},{NULL,NO_PAR,NO_PAR}, // frame 8 + {l1s_read_mon_result,FBNEW, 5},{NULL,NO_PAR,NO_PAR}, // frame 9 + {l1s_read_mon_result,FBNEW, 6},{NULL,NO_PAR,NO_PAR}, // frame 10 + {l1s_read_mon_result,FBNEW, 7},{NULL,NO_PAR,NO_PAR}, // frame 11 + {l1s_read_mon_result,FBNEW, 8},{NULL,NO_PAR,NO_PAR}, // frame 12 + {l1s_read_mon_result,FBNEW, 9},{NULL,NO_PAR,NO_PAR}, // frame 13 + {l1s_read_mon_result,FBNEW,10},{NULL,NO_PAR,NO_PAR}, // frame 14 + {l1s_read_mon_result,FBNEW,11},{NULL,NO_PAR,NO_PAR}, // frame 15 + {l1s_read_mon_result,FBNEW,12},{NULL,NO_PAR,NO_PAR} // frame 16 + }; + + /*----------------------------------------------------*/ + /* TASK: SB2, New Synchro Burst search... */ + /*----------------------------------------------------*/ + /* C W R -> AGC */ + /* C W W R -> 1st SB */ + /* C W W R -> 2nd SB */ /*----------------------------------------------------*/ - /* TASK: FBSB Frequency + Synchro Bursts Search... */ + const T_FCT BLOC_SB2[] = + { + {l1s_ctrl_msagc,SB2,NO_PAR}, {NULL,NO_PAR,NO_PAR}, // frame 1 + {NULL,NO_PAR,NO_PAR}, // frame 2 + {l1s_read_msagc,SB2,NO_PAR}, {l1s_ctrl_sbgen,SB2,1}, {NULL,NO_PAR,NO_PAR}, // frame 3 + {l1s_ctrl_sbgen,SB2,2}, {NULL,NO_PAR,NO_PAR}, // frame 4 + {NULL,NO_PAR,NO_PAR}, // frame 5 + {l1s_read_mon_result,SB2,1}, {NULL,NO_PAR,NO_PAR}, // frame 6 + {l1s_read_mon_result,SB2,2}, {NULL,NO_PAR,NO_PAR} // frame 7 + }; + + /*----------------------------------------------------*/ + /* TASK: SBCONF, Synchro confirmation. */ + /*----------------------------------------------------*/ + /* C W R -> AGC */ + /* C W W R -> SBCONF */ /*----------------------------------------------------*/ - const T_FCT BLOC_FBSB[] = + const T_FCT BLOC_SBCONF[] = + { + {l1s_ctrl_msagc,SBCONF,1}, {NULL,NO_PAR,NO_PAR}, // frame 1 + {NULL,NO_PAR,NO_PAR}, // frame 2 + {l1s_read_msagc,SBCONF,1},{l1s_ctrl_sbgen,SBCONF,1}, {NULL,NO_PAR,NO_PAR}, // frame 3 + {NULL,NO_PAR,NO_PAR}, // frame 4 + {NULL,NO_PAR,NO_PAR}, // frame 5 + {l1s_read_mon_result,SBCONF,1},{NULL,NO_PAR,NO_PAR} // frame 6 + }; + + /*----------------------------------------------------*/ + /* TASK: Serving cell Normal BCCH reading. */ + /*----------------------------------------------------*/ + /* frame 1 2 3 4 5 6 */ + /* | | | | | | */ + /* C W R | | | -> burst 1 */ + /* C W R | | -> burst 2 */ + /* C W R | -> burst 3 */ + /* C W R -> burst 4 */ + /*----------------------------------------------------*/ + const T_FCT BLOC_NBCCHS[] = { - {l1s_ctrl_msagc,FBSB,NO_PAR}, {NULL,NO_PAR,NO_PAR}, // frame 1 - {NULL,NO_PAR,NO_PAR}, // frame 2 - {l1s_read_msagc,FBSB,NO_PAR},{l1s_ctrl_fbsb,FBSB,NO_PAR}, {NULL,NO_PAR,NO_PAR}, // frame 3 - {NULL,NO_PAR,NO_PAR}, // frame 4 - {l1s_read_mon_result,FBSB, 1},{NULL,NO_PAR,NO_PAR}, // frame 5 - {l1s_read_mon_result,FBSB, 2},{NULL,NO_PAR,NO_PAR}, // frame 6 - {l1s_read_mon_result,FBSB, 3},{NULL,NO_PAR,NO_PAR}, // frame 7 - {l1s_read_mon_result,FBSB, 4},{NULL,NO_PAR,NO_PAR}, // frame 8 - {l1s_read_mon_result,FBSB, 5},{NULL,NO_PAR,NO_PAR}, // frame 9 - {l1s_read_mon_result,FBSB, 6},{NULL,NO_PAR,NO_PAR}, // frame 10 - {l1s_read_mon_result,FBSB, 7},{NULL,NO_PAR,NO_PAR}, // frame 11 - {l1s_read_mon_result,FBSB, 8},{NULL,NO_PAR,NO_PAR}, // frame 12 - {l1s_read_mon_result,FBSB, 9},{NULL,NO_PAR,NO_PAR}, // frame 13 - {l1s_read_mon_result,FBSB,10},{NULL,NO_PAR,NO_PAR}, // frame 14 - {l1s_read_mon_result,FBSB,11},{NULL,NO_PAR,NO_PAR}, // frame 15 - {l1s_read_mon_result,FBSB,12},{NULL,NO_PAR,NO_PAR}, // frame 16 - {l1s_read_mon_result,FBSB,13},{NULL,NO_PAR,NO_PAR}, // frame 17 - {l1s_read_mon_result,FBSB,14},{NULL,NO_PAR,NO_PAR} // frame 18 + {l1s_ctrl_snb_dl,NBCCHS,BURST_1}, {NULL,NO_PAR,NO_PAR}, // frame 1 + {l1s_ctrl_snb_dl,NBCCHS,BURST_2}, {NULL,NO_PAR,NO_PAR}, // frame 2 + {l1s_read_snb_dl,NBCCHS,BURST_1},{l1s_ctrl_snb_dl,NBCCHS,BURST_3},{NULL,NO_PAR,NO_PAR}, // frame 3 + {l1s_read_snb_dl,NBCCHS,BURST_2},{l1s_ctrl_snb_dl,NBCCHS,BURST_4},{NULL,NO_PAR,NO_PAR}, // frame 4 + {l1s_read_snb_dl,NBCCHS,BURST_3},{NULL,NO_PAR,NO_PAR}, // frame 5 + {l1s_read_snb_dl,NBCCHS,BURST_4},{NULL,NO_PAR,NO_PAR} // frame 6 + }; + + /*----------------------------------------------------*/ + /* TASK: Serving cell Extended BCCH reading. */ + /*----------------------------------------------------*/ + /* frame 1 2 3 4 5 6 */ + /* | | | | | | */ + /* C W R | | | -> burst 1 */ + /* C W R | | -> burst 2 */ + /* C W R | -> burst 3 */ + /* C W R -> burst 4 */ + /*----------------------------------------------------*/ + const T_FCT BLOC_EBCCHS[] = + { + {l1s_ctrl_snb_dl,EBCCHS,BURST_1}, {NULL,NO_PAR,NO_PAR}, // frame 1 + {l1s_ctrl_snb_dl,EBCCHS,BURST_2}, {NULL,NO_PAR,NO_PAR}, // frame 2 + {l1s_read_snb_dl,EBCCHS,BURST_1},{l1s_ctrl_snb_dl,EBCCHS,BURST_3},{NULL,NO_PAR,NO_PAR}, // frame 3 + {l1s_read_snb_dl,EBCCHS,BURST_2},{l1s_ctrl_snb_dl,EBCCHS,BURST_4},{NULL,NO_PAR,NO_PAR}, // frame 4 + {l1s_read_snb_dl,EBCCHS,BURST_3},{NULL,NO_PAR,NO_PAR}, // frame 5 + {l1s_read_snb_dl,EBCCHS,BURST_4},{NULL,NO_PAR,NO_PAR} // frame 6 }; + + /*----------------------------------------------------*/ + /* TASK: Neighbour Cell SYStem info reading. */ + /*----------------------------------------------------*/ + /* C W R -> AGC */ + /* C W W W W W R -> all bursts */ + /*----------------------------------------------------*/ + const T_FCT BLOC_BCCHN[] = + { + {l1s_ctrl_msagc,BCCHN,NO_PAR}, {NULL,NO_PAR,NO_PAR}, // frame 1 + {NULL,NO_PAR,NO_PAR}, // frame 2 + {l1s_read_msagc,BCCHN,NO_PAR},{l1s_ctrl_nnb,BCCHN,NO_PAR},{NULL,NO_PAR,NO_PAR}, // frame 3 + {NULL,NO_PAR,NO_PAR}, // frame 4 + {NULL,NO_PAR,NO_PAR}, // frame 5 + {NULL,NO_PAR,NO_PAR}, // frame 6 + {NULL,NO_PAR,NO_PAR}, // frame 7 + {NULL,NO_PAR,NO_PAR}, // frame 8 + {l1s_read_nnb,BCCHN,NO_PAR},{NULL,NO_PAR,NO_PAR} // frame 9 + }; + + /*----------------------------------------------------*/ + /* TASK: Neighbour Cell SYStem info reading. */ + /*----------------------------------------------------*/ + /* C W R -> AGC */ + /* C W W W W W R -> all bursts */ + /*----------------------------------------------------*/ + const T_FCT BLOC_BCCHN_TOP[] = + { + {l1s_ctrl_msagc,BCCHN_TOP,NO_PAR}, {NULL,NO_PAR,NO_PAR}, // frame 1 + {NULL,NO_PAR,NO_PAR}, // frame 2 + {l1s_read_msagc,BCCHN_TOP,NO_PAR},{l1s_ctrl_nnb,BCCHN_TOP,NO_PAR},{NULL,NO_PAR,NO_PAR}, // frame 3 + {NULL,NO_PAR,NO_PAR}, // frame 4 + {NULL,NO_PAR,NO_PAR}, // frame 5 + {NULL,NO_PAR,NO_PAR}, // frame 6 + {NULL,NO_PAR,NO_PAR}, // frame 7 + {NULL,NO_PAR,NO_PAR}, // frame 8 + {l1s_read_nnb,BCCHN_TOP,NO_PAR},{NULL,NO_PAR,NO_PAR} // frame 9 + }; + + /*----------------------------------------------------*/ + /* TASK: Neighbour Cell SYStem info reading. */ + /* for packet transfer mode */ + /*----------------------------------------------------*/ + /* C W W W W W R -> all bursts */ + /*----------------------------------------------------*/ +#if (L1_GPRS) + const T_FCT BLOC_BCCHN_TRAN[] = + { + {l1s_ctrl_nnb,BCCHN_TRAN,NO_PAR},{NULL,NO_PAR,NO_PAR}, // frame 1 + {NULL,NO_PAR,NO_PAR}, // frame 2 + {NULL,NO_PAR,NO_PAR}, // frame 3 + {NULL,NO_PAR,NO_PAR}, // frame 4 + {NULL,NO_PAR,NO_PAR}, // frame 5 + {NULL,NO_PAR,NO_PAR}, // frame 6 + {l1s_read_nnb,BCCHN_TRAN,NO_PAR},{NULL,NO_PAR,NO_PAR} // frame 7 + }; #endif - /*----------------------------------------------------*/ - /* TASK: Serving cell Normal BCCH reading. */ - /*----------------------------------------------------*/ - /* frame 1 2 3 4 5 6 */ - /* | | | | | | */ - /* C W R | | | -> burst 1 */ - /* C W R | | -> burst 2 */ - /* C W R | -> burst 3 */ - /* C W R -> burst 4 */ - /*----------------------------------------------------*/ - const T_FCT BLOC_NBCCHS[] = - { - {l1s_ctrl_snb_dl,NBCCHS,BURST_1}, {NULL,NO_PAR,NO_PAR}, // frame 1 - {l1s_ctrl_snb_dl,NBCCHS,BURST_2}, {NULL,NO_PAR,NO_PAR}, // frame 2 - {l1s_read_snb_dl,NBCCHS,BURST_1},{l1s_ctrl_snb_dl,NBCCHS,BURST_3},{NULL,NO_PAR,NO_PAR}, // frame 3 - {l1s_read_snb_dl,NBCCHS,BURST_2},{l1s_ctrl_snb_dl,NBCCHS,BURST_4},{NULL,NO_PAR,NO_PAR}, // frame 4 - {l1s_read_snb_dl,NBCCHS,BURST_3},{NULL,NO_PAR,NO_PAR}, // frame 5 - {l1s_read_snb_dl,NBCCHS,BURST_4},{NULL,NO_PAR,NO_PAR} // frame 6 - }; - - /*----------------------------------------------------*/ - /* TASK: Serving cell Extended BCCH reading. */ - /*----------------------------------------------------*/ - /* frame 1 2 3 4 5 6 */ - /* | | | | | | */ - /* C W R | | | -> burst 1 */ - /* C W R | | -> burst 2 */ - /* C W R | -> burst 3 */ - /* C W R -> burst 4 */ - /*----------------------------------------------------*/ - const T_FCT BLOC_EBCCHS[] = - { - {l1s_ctrl_snb_dl,EBCCHS,BURST_1}, {NULL,NO_PAR,NO_PAR}, // frame 1 - {l1s_ctrl_snb_dl,EBCCHS,BURST_2}, {NULL,NO_PAR,NO_PAR}, // frame 2 - {l1s_read_snb_dl,EBCCHS,BURST_1},{l1s_ctrl_snb_dl,EBCCHS,BURST_3},{NULL,NO_PAR,NO_PAR}, // frame 3 - {l1s_read_snb_dl,EBCCHS,BURST_2},{l1s_ctrl_snb_dl,EBCCHS,BURST_4},{NULL,NO_PAR,NO_PAR}, // frame 4 - {l1s_read_snb_dl,EBCCHS,BURST_3},{NULL,NO_PAR,NO_PAR}, // frame 5 - {l1s_read_snb_dl,EBCCHS,BURST_4},{NULL,NO_PAR,NO_PAR} // frame 6 - }; - - /*----------------------------------------------------*/ - /* TASK: Neighbour Cell SYStem info reading. */ - /*----------------------------------------------------*/ - /* C W R -> AGC */ - /* C W W W W W R -> all bursts */ - /*----------------------------------------------------*/ - const T_FCT BLOC_BCCHN[] = - { - {l1s_ctrl_msagc,BCCHN,NO_PAR}, {NULL,NO_PAR,NO_PAR}, // frame 1 - {NULL,NO_PAR,NO_PAR}, // frame 2 - {l1s_read_msagc,BCCHN,NO_PAR},{l1s_ctrl_nnb,BCCHN,NO_PAR},{NULL,NO_PAR,NO_PAR}, // frame 3 - {NULL,NO_PAR,NO_PAR}, // frame 4 - {NULL,NO_PAR,NO_PAR}, // frame 5 - {NULL,NO_PAR,NO_PAR}, // frame 6 - {NULL,NO_PAR,NO_PAR}, // frame 7 - {NULL,NO_PAR,NO_PAR}, // frame 8 - {l1s_read_nnb,BCCHN,NO_PAR},{NULL,NO_PAR,NO_PAR} // frame 9 - }; - - /*----------------------------------------------------*/ - /* TASK: Neighbour Cell SYStem info reading. */ - /*----------------------------------------------------*/ - /* C W R -> AGC */ - /* C W W W W W R -> all bursts */ - /*----------------------------------------------------*/ - const T_FCT BLOC_BCCHN_TOP[] = - { - {l1s_ctrl_msagc,BCCHN_TOP,NO_PAR}, {NULL,NO_PAR,NO_PAR}, // frame 1 - {NULL,NO_PAR,NO_PAR}, // frame 2 - {l1s_read_msagc,BCCHN_TOP,NO_PAR},{l1s_ctrl_nnb,BCCHN_TOP,NO_PAR},{NULL,NO_PAR,NO_PAR}, // frame 3 - {NULL,NO_PAR,NO_PAR}, // frame 4 - {NULL,NO_PAR,NO_PAR}, // frame 5 - {NULL,NO_PAR,NO_PAR}, // frame 6 - {NULL,NO_PAR,NO_PAR}, // frame 7 - {NULL,NO_PAR,NO_PAR}, // frame 8 - {l1s_read_nnb,BCCHN_TOP,NO_PAR},{NULL,NO_PAR,NO_PAR} // frame 9 - }; - - /*----------------------------------------------------*/ - /* TASK: Neighbour Cell SYStem info reading. */ - /* for packet transfer mode */ - /*----------------------------------------------------*/ - /* C W W W W W R -> all bursts */ - /*----------------------------------------------------*/ - #if (L1_GPRS) - const T_FCT BLOC_BCCHN_TRAN[] = - { - {l1s_ctrl_nnb,BCCHN_TRAN,NO_PAR},{NULL,NO_PAR,NO_PAR}, // frame 1 - {NULL,NO_PAR,NO_PAR}, // frame 2 - {NULL,NO_PAR,NO_PAR}, // frame 3 - {NULL,NO_PAR,NO_PAR}, // frame 4 - {NULL,NO_PAR,NO_PAR}, // frame 5 - {NULL,NO_PAR,NO_PAR}, // frame 6 - {l1s_read_nnb,BCCHN_TRAN,NO_PAR},{NULL,NO_PAR,NO_PAR} // frame 7 - }; - #endif - - /*----------------------------------------------------*/ - /* TASK: Synchronization (camp on a new serving cell) */ - /*----------------------------------------------------*/ - const T_FCT BLOC_SYNCHRO[] = - { - {l1s_new_synchro,NO_PAR,NO_PAR},{NULL,NO_PAR,NO_PAR} // frame 1 - }; + /*----------------------------------------------------*/ + /* TASK: Synchronization (camp on a new serving cell) */ + /*----------------------------------------------------*/ + const T_FCT BLOC_SYNCHRO[] = + { + {l1s_new_synchro,NO_PAR,NO_PAR},{NULL,NO_PAR,NO_PAR} // frame 1 + }; - /*----------------------------------------------------*/ - /* TASK: ADC measurement in CS_MODE0 */ - /* C */ - /* the ADC is performed inside the frame and the */ - /* result is red in the same frame due to an */ - /* Interrupt (handle by Riviera) */ - /*----------------------------------------------------*/ - const T_FCT BLOC_ADC[] = - { - {l1s_ctrl_ADC,NO_PAR,NO_PAR},{NULL,NO_PAR,NO_PAR} // frame 1 - }; + /*----------------------------------------------------*/ + /* TASK: ADC measurement in CS_MODE0 */ + /* C */ + /* the ADC is performed inside the frame and the */ + /* result is red in the same frame due to an */ + /* Interrupt (handle by Riviera) */ + /*----------------------------------------------------*/ + const T_FCT BLOC_ADC[] = + { + {l1s_ctrl_ADC,NO_PAR,NO_PAR},{NULL,NO_PAR,NO_PAR} // frame 1 + }; - - /*----------------------------------------------------*/ - /* TASK: Short Message Service Cell Broadcast */ - /*----------------------------------------------------*/ - /* frame 1 2 3 4 5 6 */ - /* | | | | | | */ - /* C W R | | | -> hopp. + burst 1 */ - /* C W R | | -> hopp. + burst 2 */ - /* C W R | -> hopp. + burst 3 */ - /* C W R -> hopp. + burst 4 + Synch back*/ - /*----------------------------------------------------*/ - const T_FCT BLOC_SMSCB[] = - { - {l1s_hopping_algo,SMSCB,NO_PAR},{l1s_ctrl_smscb, SMSCB,BURST_1}, {NULL,NO_PAR,NO_PAR}, // frame 1 - {l1s_hopping_algo,SMSCB,NO_PAR},{l1s_ctrl_smscb, SMSCB,BURST_2}, {NULL,NO_PAR,NO_PAR}, // frame 2 - {l1s_hopping_algo,SMSCB,NO_PAR},{l1s_read_snb_dl,SMSCB,BURST_1},{l1s_ctrl_smscb, SMSCB,BURST_3},{NULL,NO_PAR,NO_PAR}, // frame 3 - {l1s_hopping_algo,SMSCB,NO_PAR},{l1s_read_snb_dl,SMSCB,BURST_2},{l1s_ctrl_smscb, SMSCB,BURST_4},{NULL,NO_PAR,NO_PAR}, // frame 4 - {l1s_read_snb_dl,SMSCB,BURST_3},{NULL,NO_PAR,NO_PAR}, // frame 5 - {l1s_read_snb_dl,SMSCB,BURST_4},{NULL,NO_PAR,NO_PAR} // frame 6 - }; - - /*----------------------------------------------------*/ - /* TASK: Normal Paging... */ - /*----------------------------------------------------*/ - /* frame 1 2 3 4 5 6 */ - /* | | | | | | */ - /* C W R | | | -> burst 1 */ - /* C W R | | -> burst 2 */ - /* C W R | -> burst 3 */ - /* C W R -> burst 4 */ - /*----------------------------------------------------*/ - const T_FCT BLOC_NP[] = - { - {l1s_ctrl_snb_dl,NP,BURST_1}, {NULL,NO_PAR,NO_PAR}, // frame 1 - {l1s_ctrl_snb_dl,NP,BURST_2}, {NULL,NO_PAR,NO_PAR}, // frame 2 - {l1s_read_snb_dl,NP,BURST_1},{l1s_ctrl_snb_dl,NP,BURST_3},{NULL,NO_PAR,NO_PAR}, // frame 3 - {l1s_read_snb_dl,NP,BURST_2},{l1s_ctrl_snb_dl,NP,BURST_4},{NULL,NO_PAR,NO_PAR}, // frame 4 - {l1s_read_snb_dl,NP,BURST_3},{NULL,NO_PAR,NO_PAR}, // frame 5 - {l1s_read_snb_dl,NP,BURST_4},{NULL,NO_PAR,NO_PAR} // frame 6 - }; - - /*----------------------------------------------------*/ - /* TASK: Extended Paging task... */ - /*----------------------------------------------------*/ - /* frame 1 2 3 4 5 6 */ - /* | | | | | | */ - /* C W R | | | -> burst 1 */ - /* C W R | | -> burst 2 */ - /* C W R | -> burst 3 */ - /* C W R -> burst 4 */ - /*----------------------------------------------------*/ - const T_FCT BLOC_EP[] = - { - {l1s_ctrl_snb_dl,EP,BURST_1}, {NULL,NO_PAR,NO_PAR}, // frame 1 - {l1s_ctrl_snb_dl,EP,BURST_2}, {NULL,NO_PAR,NO_PAR}, // frame 2 - {l1s_read_snb_dl,EP,BURST_1},{l1s_ctrl_snb_dl,EP,BURST_3},{NULL,NO_PAR,NO_PAR}, // frame 3 - {l1s_read_snb_dl,EP,BURST_2},{l1s_ctrl_snb_dl,EP,BURST_4},{NULL,NO_PAR,NO_PAR}, // frame 4 - {l1s_read_snb_dl,EP,BURST_3},{NULL,NO_PAR,NO_PAR}, // frame 5 - {l1s_read_snb_dl,EP,BURST_4},{NULL,NO_PAR,NO_PAR} // frame 6 - }; + + /*----------------------------------------------------*/ + /* TASK: Short Message Service Cell Broadcast */ + /*----------------------------------------------------*/ + /* frame 1 2 3 4 5 6 */ + /* | | | | | | */ + /* C W R | | | -> hopp. + burst 1 */ + /* C W R | | -> hopp. + burst 2 */ + /* C W R | -> hopp. + burst 3 */ + /* C W R -> hopp. + burst 4 + Synch back*/ + /*----------------------------------------------------*/ + const T_FCT BLOC_SMSCB[] = + { + {l1s_hopping_algo,SMSCB,NO_PAR},{l1s_ctrl_smscb, SMSCB,BURST_1}, {NULL,NO_PAR,NO_PAR}, // frame 1 + {l1s_hopping_algo,SMSCB,NO_PAR},{l1s_ctrl_smscb, SMSCB,BURST_2}, {NULL,NO_PAR,NO_PAR}, // frame 2 + {l1s_hopping_algo,SMSCB,NO_PAR},{l1s_read_snb_dl,SMSCB,BURST_1},{l1s_ctrl_smscb, SMSCB,BURST_3},{NULL,NO_PAR,NO_PAR}, // frame 3 + {l1s_hopping_algo,SMSCB,NO_PAR},{l1s_read_snb_dl,SMSCB,BURST_2},{l1s_ctrl_smscb, SMSCB,BURST_4},{NULL,NO_PAR,NO_PAR}, // frame 4 + {l1s_read_snb_dl,SMSCB,BURST_3},{NULL,NO_PAR,NO_PAR}, // frame 5 + {l1s_read_snb_dl,SMSCB,BURST_4},{NULL,NO_PAR,NO_PAR} // frame 6 + }; + + /*----------------------------------------------------*/ + /* TASK: Normal Paging... */ + /*----------------------------------------------------*/ + /* frame 1 2 3 4 5 6 */ + /* | | | | | | */ + /* C W R | | | -> burst 1 */ + /* C W R | | -> burst 2 */ + /* C W R | -> burst 3 */ + /* C W R -> burst 4 */ + /*----------------------------------------------------*/ + const T_FCT BLOC_NP[] = + { + {l1s_ctrl_snb_dl,NP,BURST_1}, {NULL,NO_PAR,NO_PAR}, // frame 1 + {l1s_ctrl_snb_dl,NP,BURST_2}, {NULL,NO_PAR,NO_PAR}, // frame 2 + {l1s_read_snb_dl,NP,BURST_1},{l1s_ctrl_snb_dl,NP,BURST_3},{NULL,NO_PAR,NO_PAR}, // frame 3 + {l1s_read_snb_dl,NP,BURST_2},{l1s_ctrl_snb_dl,NP,BURST_4},{NULL,NO_PAR,NO_PAR}, // frame 4 + {l1s_read_snb_dl,NP,BURST_3},{NULL,NO_PAR,NO_PAR}, // frame 5 + {l1s_read_snb_dl,NP,BURST_4},{NULL,NO_PAR,NO_PAR} // frame 6 + }; + + /*----------------------------------------------------*/ + /* TASK: Extended Paging task... */ + /*----------------------------------------------------*/ + /* frame 1 2 3 4 5 6 */ + /* | | | | | | */ + /* C W R | | | -> burst 1 */ + /* C W R | | -> burst 2 */ + /* C W R | -> burst 3 */ + /* C W R -> burst 4 */ + /*----------------------------------------------------*/ + const T_FCT BLOC_EP[] = + { + {l1s_ctrl_snb_dl,EP,BURST_1}, {NULL,NO_PAR,NO_PAR}, // frame 1 + {l1s_ctrl_snb_dl,EP,BURST_2}, {NULL,NO_PAR,NO_PAR}, // frame 2 + {l1s_read_snb_dl,EP,BURST_1},{l1s_ctrl_snb_dl,EP,BURST_3},{NULL,NO_PAR,NO_PAR}, // frame 3 + {l1s_read_snb_dl,EP,BURST_2},{l1s_ctrl_snb_dl,EP,BURST_4},{NULL,NO_PAR,NO_PAR}, // frame 4 + {l1s_read_snb_dl,EP,BURST_3},{NULL,NO_PAR,NO_PAR}, // frame 5 + {l1s_read_snb_dl,EP,BURST_4},{NULL,NO_PAR,NO_PAR} // frame 6 + }; - /*----------------------------------------------------*/ - /* TASK: All CCCH reading task... */ - /*----------------------------------------------------*/ - /* frame 1 2 3 4 5 6 */ - /* | | | | | | */ - /* C W R | | | -> burst 1 */ - /* C W R | | -> burst 2 */ - /* C W R | -> burst 3 */ - /* C W R -> burst 4 */ - /*----------------------------------------------------*/ - const T_FCT BLOC_ALLC[] = - { - {l1s_ctrl_snb_dl,ALLC,BURST_1}, {NULL,NO_PAR,NO_PAR}, // frame 1 - {l1s_ctrl_snb_dl,ALLC,BURST_2}, {NULL,NO_PAR,NO_PAR}, // frame 2 - {l1s_read_snb_dl,ALLC,BURST_1},{l1s_ctrl_snb_dl,ALLC,BURST_3},{NULL,NO_PAR,NO_PAR}, // frame 3 - {l1s_read_snb_dl,ALLC,BURST_2},{l1s_ctrl_snb_dl,ALLC,BURST_4},{NULL,NO_PAR,NO_PAR}, // frame 4 - {l1s_read_snb_dl,ALLC,BURST_3},{NULL,NO_PAR,NO_PAR}, // frame 5 - {l1s_read_snb_dl,ALLC,BURST_4},{NULL,NO_PAR,NO_PAR} // frame 6 - }; + /*----------------------------------------------------*/ + /* TASK: All CCCH reading task... */ + /*----------------------------------------------------*/ + /* frame 1 2 3 4 5 6 */ + /* | | | | | | */ + /* C W R | | | -> burst 1 */ + /* C W R | | -> burst 2 */ + /* C W R | -> burst 3 */ + /* C W R -> burst 4 */ + /*----------------------------------------------------*/ + const T_FCT BLOC_ALLC[] = + { + {l1s_ctrl_snb_dl,ALLC,BURST_1}, {NULL,NO_PAR,NO_PAR}, // frame 1 + {l1s_ctrl_snb_dl,ALLC,BURST_2}, {NULL,NO_PAR,NO_PAR}, // frame 2 + {l1s_read_snb_dl,ALLC,BURST_1},{l1s_ctrl_snb_dl,ALLC,BURST_3},{NULL,NO_PAR,NO_PAR}, // frame 3 + {l1s_read_snb_dl,ALLC,BURST_2},{l1s_ctrl_snb_dl,ALLC,BURST_4},{NULL,NO_PAR,NO_PAR}, // frame 4 + {l1s_read_snb_dl,ALLC,BURST_3},{NULL,NO_PAR,NO_PAR}, // frame 5 + {l1s_read_snb_dl,ALLC,BURST_4},{NULL,NO_PAR,NO_PAR} // frame 6 + }; - /*----------------------------------------------------*/ - /* TASK: SDCCH */ - /*----------------------------------------------------*/ - /* frame 1 2 3 4 5 6 */ - /* | | | | | | */ - /* C W R | | | -> burst 1 */ - /* C W R | | -> burst 2 */ - /* C W R | -> burst 3 */ - /* C W R -> burst 4 */ - /*----------------------------------------------------*/ - const T_FCT BLOC_DDL[] = - { - {l1s_hopping_algo,DDL,NO_PAR},{l1s_ctrl_snb_dl, DDL,BURST_1}, {NULL,NO_PAR,NO_PAR}, // frame 1 - {l1s_hopping_algo,DDL,NO_PAR},{l1s_ctrl_snb_dl, DDL,BURST_2}, {NULL,NO_PAR,NO_PAR}, // frame 2 - {l1s_hopping_algo,DDL,NO_PAR},{l1s_read_dedic_dl,DDL,BURST_1},{l1s_ctrl_snb_dl, DDL,BURST_3},{NULL,NO_PAR,NO_PAR}, // frame 3 - {l1s_hopping_algo,DDL,NO_PAR},{l1s_read_dedic_dl,DDL,BURST_2},{l1s_ctrl_snb_dl, DDL,BURST_4},{NULL,NO_PAR,NO_PAR}, // frame 4 - {l1s_read_dedic_dl,DDL,BURST_3},{NULL,NO_PAR,NO_PAR}, // frame 5 - {l1s_read_dedic_dl,DDL,BURST_4},{NULL,NO_PAR,NO_PAR} // frame 6 - }; + /*----------------------------------------------------*/ + /* TASK: SDCCH */ + /*----------------------------------------------------*/ + /* frame 1 2 3 4 5 6 */ + /* | | | | | | */ + /* C W R | | | -> burst 1 */ + /* C W R | | -> burst 2 */ + /* C W R | -> burst 3 */ + /* C W R -> burst 4 */ + /*----------------------------------------------------*/ + const T_FCT BLOC_DDL[] = + { + {l1s_hopping_algo,DDL,NO_PAR},{l1s_ctrl_snb_dl, DDL,BURST_1}, {NULL,NO_PAR,NO_PAR}, // frame 1 + {l1s_hopping_algo,DDL,NO_PAR},{l1s_ctrl_snb_dl, DDL,BURST_2}, {NULL,NO_PAR,NO_PAR}, // frame 2 + {l1s_hopping_algo,DDL,NO_PAR},{l1s_read_dedic_dl,DDL,BURST_1},{l1s_ctrl_snb_dl, DDL,BURST_3},{NULL,NO_PAR,NO_PAR}, // frame 3 + {l1s_hopping_algo,DDL,NO_PAR},{l1s_read_dedic_dl,DDL,BURST_2},{l1s_ctrl_snb_dl, DDL,BURST_4},{NULL,NO_PAR,NO_PAR}, // frame 4 + {l1s_read_dedic_dl,DDL,BURST_3},{NULL,NO_PAR,NO_PAR}, // frame 5 + {l1s_read_dedic_dl,DDL,BURST_4},{NULL,NO_PAR,NO_PAR} // frame 6 + }; - const T_FCT BLOC_DUL[] = - { - {l1s_hopping_algo,DUL,NO_PAR},{l1s_ctrl_snb_ul, DUL,BURST_1}, {NULL,NO_PAR,NO_PAR}, // frame 1 - {l1s_hopping_algo,DUL,NO_PAR},{l1s_ctrl_snb_ul, DUL,BURST_2}, {NULL,NO_PAR,NO_PAR}, // frame 2 - {l1s_hopping_algo,DUL,NO_PAR},{l1s_read_tx_result,DUL,BURST_1},{l1s_ctrl_snb_ul, DUL,BURST_3},{NULL,NO_PAR,NO_PAR}, // frame 3 - {l1s_hopping_algo,DUL,NO_PAR},{l1s_read_tx_result,DUL,BURST_2},{l1s_ctrl_snb_ul, DUL,BURST_4},{NULL,NO_PAR,NO_PAR}, // frame 4 - {l1s_read_tx_result,DUL,BURST_3},{NULL,NO_PAR,NO_PAR}, // frame 5 - {l1s_read_tx_result,DUL,BURST_4},{NULL,NO_PAR,NO_PAR} // frame 6 - }; + const T_FCT BLOC_DUL[] = + { + {l1s_hopping_algo,DUL,NO_PAR},{l1s_ctrl_snb_ul, DUL,BURST_1}, {NULL,NO_PAR,NO_PAR}, // frame 1 + {l1s_hopping_algo,DUL,NO_PAR},{l1s_ctrl_snb_ul, DUL,BURST_2}, {NULL,NO_PAR,NO_PAR}, // frame 2 + {l1s_hopping_algo,DUL,NO_PAR},{l1s_read_tx_result,DUL,BURST_1},{l1s_ctrl_snb_ul, DUL,BURST_3},{NULL,NO_PAR,NO_PAR}, // frame 3 + {l1s_hopping_algo,DUL,NO_PAR},{l1s_read_tx_result,DUL,BURST_2},{l1s_ctrl_snb_ul, DUL,BURST_4},{NULL,NO_PAR,NO_PAR}, // frame 4 + {l1s_read_tx_result,DUL,BURST_3},{NULL,NO_PAR,NO_PAR}, // frame 5 + {l1s_read_tx_result,DUL,BURST_4},{NULL,NO_PAR,NO_PAR} // frame 6 + }; - const T_FCT BLOC_ADL[] = - { - {l1s_hopping_algo,ADL,NO_PAR},{l1s_ctrl_snb_dl, ADL,BURST_1}, {NULL,NO_PAR,NO_PAR}, // frame 1 - {l1s_hopping_algo,ADL,NO_PAR},{l1s_ctrl_snb_dl, ADL,BURST_2}, {NULL,NO_PAR,NO_PAR}, // frame 2 - {l1s_hopping_algo,ADL,NO_PAR},{l1s_read_dedic_dl,ADL,BURST_1},{l1s_ctrl_snb_dl, ADL,BURST_3},{NULL,NO_PAR,NO_PAR}, // frame 3 - {l1s_hopping_algo,ADL,NO_PAR},{l1s_read_dedic_dl,ADL,BURST_2},{l1s_ctrl_snb_dl, ADL,BURST_4},{NULL,NO_PAR,NO_PAR}, // frame 4 - {l1s_read_dedic_dl,ADL,BURST_3},{NULL,NO_PAR,NO_PAR}, // frame 5 - {l1s_read_dedic_dl,ADL,BURST_4},{NULL,NO_PAR,NO_PAR} // frame 6 - }; + const T_FCT BLOC_ADL[] = + { + {l1s_hopping_algo,ADL,NO_PAR},{l1s_ctrl_snb_dl, ADL,BURST_1}, {NULL,NO_PAR,NO_PAR}, // frame 1 + {l1s_hopping_algo,ADL,NO_PAR},{l1s_ctrl_snb_dl, ADL,BURST_2}, {NULL,NO_PAR,NO_PAR}, // frame 2 + {l1s_hopping_algo,ADL,NO_PAR},{l1s_read_dedic_dl,ADL,BURST_1},{l1s_ctrl_snb_dl, ADL,BURST_3},{NULL,NO_PAR,NO_PAR}, // frame 3 + {l1s_hopping_algo,ADL,NO_PAR},{l1s_read_dedic_dl,ADL,BURST_2},{l1s_ctrl_snb_dl, ADL,BURST_4},{NULL,NO_PAR,NO_PAR}, // frame 4 + {l1s_read_dedic_dl,ADL,BURST_3},{NULL,NO_PAR,NO_PAR}, // frame 5 + {l1s_read_dedic_dl,ADL,BURST_4},{NULL,NO_PAR,NO_PAR} // frame 6 + }; - const T_FCT BLOC_AUL[] = - { - {l1s_hopping_algo,AUL,NO_PAR},{l1s_ctrl_snb_ul, AUL,BURST_1}, {NULL,NO_PAR,NO_PAR}, // frame 1 - {l1s_hopping_algo,AUL,NO_PAR},{l1s_ctrl_snb_ul, AUL,BURST_2}, {NULL,NO_PAR,NO_PAR}, // frame 2 - {l1s_hopping_algo,AUL,NO_PAR},{l1s_read_tx_result,AUL,BURST_1},{l1s_ctrl_snb_ul, AUL,BURST_3},{NULL,NO_PAR,NO_PAR}, // frame 3 - {l1s_hopping_algo,AUL,NO_PAR},{l1s_read_tx_result,AUL,BURST_2},{l1s_ctrl_snb_ul, AUL,BURST_4},{NULL,NO_PAR,NO_PAR}, // frame 4 - {l1s_read_tx_result,AUL,BURST_3},{NULL,NO_PAR,NO_PAR}, // frame 5 - {l1s_read_tx_result,AUL,BURST_4},{NULL,NO_PAR,NO_PAR} // frame 6 - }; - - /*-----------------------------------------------------------------------*/ - /* SPECIAL CASE: (ADL4,DDL4),(ADL5,DDL5),(ADL6,DDL6). */ - /*-----------------------------------------------------------------------*/ - /* frame 1 2 3 4 5 6 7 */ - /* | | | | | | | */ - /* C(DUL,1) W(DUL,1) R(DUL,1) | | | | */ - /* C(ADL,1) W(ADL,1) R(ADL,1) | | | */ - /* C(DUL,2) W(DUL,2) R(DUL,2) | | | */ - /* C(ADL,2) W(ADL,2) R(ADL,2) | | */ - /* C(DUL,3) W(DUL,3) R(DUL,3) | | */ - /* C(ADL,3) W(ADL,3) R(ADL,3) | */ - /* C(DUL,4) W(DUL,4) R(DUL,4) | */ - /* C(ADL,4) W(ADL,4) R(ADL,4) */ - /*-----------------------------------------------------------------------*/ - const T_FCT BLOC_DUL_ADL_MIXED[] = - { - {l1s_hopping_algo,AUL,NO_PAR},{l1s_ctrl_snb_ul, DUL,BURST_1}, {NULL,NO_PAR,NO_PAR}, // frame 1 - {l1s_hopping_algo,ADL,NO_PAR},{l1s_ctrl_snb_dl, ADL,BURST_1},{l1s_ctrl_snb_ul, DUL,BURST_2}, {NULL,NO_PAR,NO_PAR}, // frame 2 - {l1s_hopping_algo,ADL,NO_PAR},{l1s_read_tx_result,DUL,BURST_1},{l1s_ctrl_snb_dl, ADL,BURST_2},{l1s_ctrl_snb_ul, DUL,BURST_3}, {NULL,NO_PAR,NO_PAR}, // frame 3 - {l1s_hopping_algo,ADL,NO_PAR},{l1s_read_dedic_dl, ADL,BURST_1},{l1s_read_tx_result,DUL,BURST_2},{l1s_ctrl_snb_dl, ADL,BURST_3},{l1s_ctrl_snb_ul, DUL,BURST_4},{NULL,NO_PAR,NO_PAR}, // frame 4 - {l1s_hopping_algo,ADL,NO_PAR},{l1s_read_dedic_dl, ADL,BURST_2},{l1s_read_tx_result,DUL,BURST_3},{l1s_ctrl_snb_dl, ADL,BURST_4}, {NULL,NO_PAR,NO_PAR}, // frame 5 - {l1s_read_dedic_dl,ADL,BURST_3},{l1s_read_tx_result,DUL,BURST_4},{NULL,NO_PAR,NO_PAR}, // frame 6 - {l1s_read_dedic_dl,ADL,BURST_4}, {NULL,NO_PAR,NO_PAR} // frame 7 - }; - - /*----------------------------------------------------*/ - /* ABORT: used to abort a running task when a new */ - /* task with higher priority occurs. */ - /*----------------------------------------------------*/ - const T_FCT BLOC_ABORT[] = - { - {l1s_abort,NO_PAR,NO_PAR}, {NULL,NO_PAR,NO_PAR}, // frame 1 - {l1s_reset_tx_ptr,NO_PAR,NO_PAR}, {NULL,NO_PAR,NO_PAR}, // frame 2 - {l1s_read_dummy,NO_PAR,NO_PAR},{NULL,NO_PAR,NO_PAR} // frame 3 - }; - - /*----------------------------------------------------*/ - /* TASK: RACH in access mode... */ - /*----------------------------------------------------*/ - const T_FCT BLOC_RAACC[] = - { - {l1s_ctrl_rach,RAACC,NO_PAR}, {NULL,NO_PAR,NO_PAR}, // frame 1 - {NULL,NO_PAR,NO_PAR}, // frame 2 - {l1s_read_tx_result,RAACC,NO_PAR},{NULL,NO_PAR,NO_PAR} // frame 3 - }; + const T_FCT BLOC_AUL[] = + { + {l1s_hopping_algo,AUL,NO_PAR},{l1s_ctrl_snb_ul, AUL,BURST_1}, {NULL,NO_PAR,NO_PAR}, // frame 1 + {l1s_hopping_algo,AUL,NO_PAR},{l1s_ctrl_snb_ul, AUL,BURST_2}, {NULL,NO_PAR,NO_PAR}, // frame 2 + {l1s_hopping_algo,AUL,NO_PAR},{l1s_read_tx_result,AUL,BURST_1},{l1s_ctrl_snb_ul, AUL,BURST_3},{NULL,NO_PAR,NO_PAR}, // frame 3 + {l1s_hopping_algo,AUL,NO_PAR},{l1s_read_tx_result,AUL,BURST_2},{l1s_ctrl_snb_ul, AUL,BURST_4},{NULL,NO_PAR,NO_PAR}, // frame 4 + {l1s_read_tx_result,AUL,BURST_3},{NULL,NO_PAR,NO_PAR}, // frame 5 + {l1s_read_tx_result,AUL,BURST_4},{NULL,NO_PAR,NO_PAR} // frame 6 + }; + + /*-----------------------------------------------------------------------*/ + /* SPECIAL CASE: (ADL4,DDL4),(ADL5,DDL5),(ADL6,DDL6). */ + /*-----------------------------------------------------------------------*/ + /* frame 1 2 3 4 5 6 7 */ + /* | | | | | | | */ + /* C(DUL,1) W(DUL,1) R(DUL,1) | | | | */ + /* C(ADL,1) W(ADL,1) R(ADL,1) | | | */ + /* C(DUL,2) W(DUL,2) R(DUL,2) | | | */ + /* C(ADL,2) W(ADL,2) R(ADL,2) | | */ + /* C(DUL,3) W(DUL,3) R(DUL,3) | | */ + /* C(ADL,3) W(ADL,3) R(ADL,3) | */ + /* C(DUL,4) W(DUL,4) R(DUL,4) | */ + /* C(ADL,4) W(ADL,4) R(ADL,4) */ + /*-----------------------------------------------------------------------*/ + const T_FCT BLOC_DUL_ADL_MIXED[] = + { + {l1s_hopping_algo,AUL,NO_PAR},{l1s_ctrl_snb_ul, DUL,BURST_1}, {NULL,NO_PAR,NO_PAR}, // frame 1 + {l1s_hopping_algo,ADL,NO_PAR},{l1s_ctrl_snb_dl, ADL,BURST_1},{l1s_ctrl_snb_ul, DUL,BURST_2}, {NULL,NO_PAR,NO_PAR}, // frame 2 + {l1s_hopping_algo,ADL,NO_PAR},{l1s_read_tx_result,DUL,BURST_1},{l1s_ctrl_snb_dl, ADL,BURST_2},{l1s_ctrl_snb_ul, DUL,BURST_3}, {NULL,NO_PAR,NO_PAR}, // frame 3 + {l1s_hopping_algo,ADL,NO_PAR},{l1s_read_dedic_dl, ADL,BURST_1},{l1s_read_tx_result,DUL,BURST_2},{l1s_ctrl_snb_dl, ADL,BURST_3},{l1s_ctrl_snb_ul, DUL,BURST_4},{NULL,NO_PAR,NO_PAR}, // frame 4 + {l1s_hopping_algo,ADL,NO_PAR},{l1s_read_dedic_dl, ADL,BURST_2},{l1s_read_tx_result,DUL,BURST_3},{l1s_ctrl_snb_dl, ADL,BURST_4}, {NULL,NO_PAR,NO_PAR}, // frame 5 + {l1s_read_dedic_dl,ADL,BURST_3},{l1s_read_tx_result,DUL,BURST_4},{NULL,NO_PAR,NO_PAR}, // frame 6 + {l1s_read_dedic_dl,ADL,BURST_4}, {NULL,NO_PAR,NO_PAR} // frame 7 + }; + + /*----------------------------------------------------*/ + /* ABORT: used to abort a running task when a new */ + /* task with higher priority occurs. */ + /*----------------------------------------------------*/ + const T_FCT BLOC_ABORT[] = + { + {l1s_abort,NO_PAR,NO_PAR}, {NULL,NO_PAR,NO_PAR}, // frame 1 + {NULL,NO_PAR,NO_PAR}, // frame 2 + {l1s_read_dummy,NO_PAR,NO_PAR},{NULL,NO_PAR,NO_PAR} // frame 3 + }; + + /*----------------------------------------------------*/ + /* TASK: RACH in access mode... */ + /*----------------------------------------------------*/ + const T_FCT BLOC_RAACC[] = + { + {l1s_ctrl_rach,RAACC,NO_PAR}, {NULL,NO_PAR,NO_PAR}, // frame 1 + {NULL,NO_PAR,NO_PAR}, // frame 2 + {l1s_read_tx_result,RAACC,NO_PAR},{NULL,NO_PAR,NO_PAR} // frame 3 + }; - /*----------------------------------------------------*/ - /* TASK: TCH */ - /*----------------------------------------------------*/ - /* C W R */ - /*----------------------------------------------------*/ - const T_FCT BLOC_TCHTF[] = - { - {l1s_hopping_algo,TCHTF,NO_PAR},{l1s_ctrl_tchtf,TCHTF,NO_PAR}, {NULL,NO_PAR}, // frame 1 - {NULL,NO_PAR}, // frame 2 - {l1s_read_dedic_dl,TCHTF,NO_PAR}, {NULL,NO_PAR} // frame 3 - }; - - const T_FCT BLOC_TCHTH[] = - { - {l1s_hopping_algo,TCHTH,NO_PAR},{l1s_ctrl_tchth,TCHTH,NO_PAR}, {NULL,NO_PAR}, // frame 1 - {NULL,NO_PAR}, // frame 2 - {l1s_read_dedic_dl,TCHTH,NO_PAR}, {NULL,NO_PAR} // frame 3 - }; - - const T_FCT BLOC_TCHD[] = - { - {l1s_ctrl_tchtd,TCHD,NO_PAR}, {NULL,NO_PAR}, // frame 1 - {NULL,NO_PAR}, // frame 2 - {l1s_read_dummy,TCHD,NO_PAR}, {NULL,NO_PAR} // frame 3 - }; + /*----------------------------------------------------*/ + /* TASK: TCH */ + /*----------------------------------------------------*/ + /* C W R */ + /*----------------------------------------------------*/ + const T_FCT BLOC_TCHTF[] = + { + {l1s_hopping_algo,TCHTF,NO_PAR},{l1s_ctrl_tchtf,TCHTF,NO_PAR}, {NULL,NO_PAR}, // frame 1 + {NULL,NO_PAR}, // frame 2 + {l1s_read_dedic_dl,TCHTF,NO_PAR}, {NULL,NO_PAR} // frame 3 + }; + + const T_FCT BLOC_TCHTH[] = + { + {l1s_hopping_algo,TCHTH,NO_PAR},{l1s_ctrl_tchth,TCHTH,NO_PAR}, {NULL,NO_PAR}, // frame 1 + {NULL,NO_PAR}, // frame 2 + {l1s_read_dedic_dl,TCHTH,NO_PAR}, {NULL,NO_PAR} // frame 3 + }; + + const T_FCT BLOC_TCHD[] = + { + {l1s_ctrl_tchtd,TCHD,NO_PAR}, {NULL,NO_PAR}, // frame 1 + {NULL,NO_PAR}, // frame 2 + {l1s_read_dummy,TCHD,NO_PAR}, {NULL,NO_PAR} // frame 3 + }; - const T_FCT BLOC_TCHA[] = - { - {l1s_hopping_algo,TCHA,NO_PAR},{l1s_ctrl_tcha,TCHA,NO_PAR}, {NULL,NO_PAR}, // frame 1 - {NULL,NO_PAR}, // frame 2 - {l1s_read_dedic_dl,TCHA,NO_PAR}, {NULL,NO_PAR} // frame 3 - }; + const T_FCT BLOC_TCHA[] = + { + {l1s_hopping_algo,TCHA,NO_PAR},{l1s_ctrl_tcha,TCHA,NO_PAR}, {NULL,NO_PAR}, // frame 1 + {NULL,NO_PAR}, // frame 2 + {l1s_read_dedic_dl,TCHA,NO_PAR}, {NULL,NO_PAR} // frame 3 + }; - /*----------------------------------------------------*/ - /* TASK: Frequency Burst search in dedic/SDCCH... */ - /*----------------------------------------------------*/ - const T_FCT BLOC_FB51[] = - { - {l1s_ctrl_fb,FB51,NO_PAR}, {NULL,NO_PAR,NO_PAR}, // frame 1 - {NULL,NO_PAR,NO_PAR}, // frame 2 - {l1s_read_mon_result,FB51, 1},{NULL,NO_PAR,NO_PAR}, // frame 3 - {l1s_read_mon_result,FB51, 2},{NULL,NO_PAR,NO_PAR}, // frame 4 - {l1s_read_mon_result,FB51, 3},{NULL,NO_PAR,NO_PAR}, // frame 5 - {l1s_read_mon_result,FB51, 4},{NULL,NO_PAR,NO_PAR}, // frame 6 - {l1s_read_mon_result,FB51, 5},{NULL,NO_PAR,NO_PAR}, // frame 7 - {l1s_read_mon_result,FB51, 6},{NULL,NO_PAR,NO_PAR}, // frame 8 - {l1s_read_mon_result,FB51, 7},{NULL,NO_PAR,NO_PAR}, // frame 9 - {l1s_read_mon_result,FB51, 8},{NULL,NO_PAR,NO_PAR}, // frame 10 - {l1s_read_mon_result,FB51, 9},{NULL,NO_PAR,NO_PAR}, // frame 11 - {l1s_read_mon_result,FB51,10},{NULL,NO_PAR,NO_PAR}, // frame 12 - {l1s_read_mon_result,FB51,11},{NULL,NO_PAR,NO_PAR}, // frame 13 - {l1s_read_mon_result,FB51,12},{NULL,NO_PAR,NO_PAR} // frame 14 - }; + /*----------------------------------------------------*/ + /* TASK: Frequency Burst search in dedic/SDCCH... */ + /*----------------------------------------------------*/ + const T_FCT BLOC_FB51[] = + { + {l1s_ctrl_fb,FB51,NO_PAR}, {NULL,NO_PAR,NO_PAR}, // frame 1 + {NULL,NO_PAR,NO_PAR}, // frame 2 + {l1s_read_mon_result,FB51, 1},{NULL,NO_PAR,NO_PAR}, // frame 3 + {l1s_read_mon_result,FB51, 2},{NULL,NO_PAR,NO_PAR}, // frame 4 + {l1s_read_mon_result,FB51, 3},{NULL,NO_PAR,NO_PAR}, // frame 5 + {l1s_read_mon_result,FB51, 4},{NULL,NO_PAR,NO_PAR}, // frame 6 + {l1s_read_mon_result,FB51, 5},{NULL,NO_PAR,NO_PAR}, // frame 7 + {l1s_read_mon_result,FB51, 6},{NULL,NO_PAR,NO_PAR}, // frame 8 + {l1s_read_mon_result,FB51, 7},{NULL,NO_PAR,NO_PAR}, // frame 9 + {l1s_read_mon_result,FB51, 8},{NULL,NO_PAR,NO_PAR}, // frame 10 + {l1s_read_mon_result,FB51, 9},{NULL,NO_PAR,NO_PAR}, // frame 11 + {l1s_read_mon_result,FB51,10},{NULL,NO_PAR,NO_PAR}, // frame 12 + {l1s_read_mon_result,FB51,11},{NULL,NO_PAR,NO_PAR}, // frame 13 + {l1s_read_mon_result,FB51,12},{NULL,NO_PAR,NO_PAR} // frame 14 + }; - /*----------------------------------------------------*/ - /* TASK: SB51, Synchro Burst reading. Dedic/SDCCH. */ - /*----------------------------------------------------*/ - /* C W W R -> SB */ - /*----------------------------------------------------*/ - const T_FCT BLOC_SB51[] = - { - {l1s_ctrl_sbgen,SB51,NO_PAR}, {NULL,NO_PAR,NO_PAR}, // frame 1 - {NULL,NO_PAR,NO_PAR}, // frame 2 - {NULL,NO_PAR,NO_PAR}, // frame 3 - {l1s_read_mon_result,SB51,NO_PAR},{NULL,NO_PAR,NO_PAR} // frame 4 - }; + /*----------------------------------------------------*/ + /* TASK: SB51, Synchro Burst reading. Dedic/SDCCH. */ + /*----------------------------------------------------*/ + /* C W W R -> SB */ + /*----------------------------------------------------*/ + const T_FCT BLOC_SB51[] = + { + {l1s_ctrl_sbgen,SB51,NO_PAR}, {NULL,NO_PAR,NO_PAR}, // frame 1 + {NULL,NO_PAR,NO_PAR}, // frame 2 + {NULL,NO_PAR,NO_PAR}, // frame 3 + {l1s_read_mon_result,SB51,NO_PAR},{NULL,NO_PAR,NO_PAR} // frame 4 + }; - /*----------------------------------------------------*/ - /* TASK: SBCNF51, Synchro confirmation. Dedic/SDCCH. */ - /*----------------------------------------------------*/ - /* C W W R -> SBCONF */ - /*----------------------------------------------------*/ - const T_FCT BLOC_SBCNF51[] = - { - {l1s_ctrl_sbgen,SBCNF51,NO_PAR}, {NULL,NO_PAR,NO_PAR}, // frame 1 - {NULL,NO_PAR,NO_PAR}, // frame 2 - {NULL,NO_PAR,NO_PAR}, // frame 3 - {l1s_read_mon_result,SBCNF51,NO_PAR},{NULL,NO_PAR,NO_PAR} // frame 4 - }; + /*----------------------------------------------------*/ + /* TASK: SBCNF51, Synchro confirmation. Dedic/SDCCH. */ + /*----------------------------------------------------*/ + /* C W W R -> SBCONF */ + /*----------------------------------------------------*/ + const T_FCT BLOC_SBCNF51[] = + { + {l1s_ctrl_sbgen,SBCNF51,NO_PAR}, {NULL,NO_PAR,NO_PAR}, // frame 1 + {NULL,NO_PAR,NO_PAR}, // frame 2 + {NULL,NO_PAR,NO_PAR}, // frame 3 + {l1s_read_mon_result,SBCNF51,NO_PAR},{NULL,NO_PAR,NO_PAR} // frame 4 + }; - /*----------------------------------------------------*/ - /* TASK: FB26, Frequency Burst search in dedic/TCH... */ - /*----------------------------------------------------*/ - /* C W W R */ - /*----------------------------------------------------*/ - const T_FCT BLOC_FB26[] = - { - {l1s_ctrl_fb26,FB26,NO_PAR}, {NULL,NO_PAR,NO_PAR}, // frame 1 - {NULL,NO_PAR,NO_PAR}, // frame 2 - {NULL,NO_PAR,NO_PAR}, // frame 3 - {l1s_read_mon_result,FB26,NO_PAR},{NULL,NO_PAR,NO_PAR} // frame 4 - }; + /*----------------------------------------------------*/ + /* TASK: FB26, Frequency Burst search in dedic/TCH... */ + /*----------------------------------------------------*/ + /* C W W R */ + /*----------------------------------------------------*/ + const T_FCT BLOC_FB26[] = + { + {l1s_ctrl_fb26,FB26,NO_PAR}, {NULL,NO_PAR,NO_PAR}, // frame 1 + {NULL,NO_PAR,NO_PAR}, // frame 2 + {NULL,NO_PAR,NO_PAR}, // frame 3 + {l1s_read_mon_result,FB26,NO_PAR},{NULL,NO_PAR,NO_PAR} // frame 4 + }; - /*----------------------------------------------------*/ - /* TASK: SB26, Synchro. Burst reading in dedic/TCH... */ - /*----------------------------------------------------*/ - /* C W W W R */ - /*----------------------------------------------------*/ - const T_FCT BLOC_SB26[] = - { - {l1s_ctrl_sb26,SB26,NO_PAR}, {NULL,NO_PAR,NO_PAR}, // frame 1 - {NULL,NO_PAR,NO_PAR}, // frame 2 - {NULL,NO_PAR,NO_PAR}, // frame 3 - {NULL,NO_PAR,NO_PAR}, // frame 4 - {l1s_read_mon_result,SB26,NO_PAR},{NULL,NO_PAR,NO_PAR} // frame 5 - }; + /*----------------------------------------------------*/ + /* TASK: SB26, Synchro. Burst reading in dedic/TCH... */ + /*----------------------------------------------------*/ + /* C W W W R */ + /*----------------------------------------------------*/ + const T_FCT BLOC_SB26[] = + { + {l1s_ctrl_sb26,SB26,NO_PAR}, {NULL,NO_PAR,NO_PAR}, // frame 1 + {NULL,NO_PAR,NO_PAR}, // frame 2 + {NULL,NO_PAR,NO_PAR}, // frame 3 + {NULL,NO_PAR,NO_PAR}, // frame 4 + {l1s_read_mon_result,SB26,NO_PAR},{NULL,NO_PAR,NO_PAR} // frame 5 + }; - /*----------------------------------------------------*/ - /* TASK: SBCNF26, Synchro. Burst reading in dedic/TCH.*/ - /*----------------------------------------------------*/ - /* C W W W R */ - /*----------------------------------------------------*/ - const T_FCT BLOC_SBCNF26[] = - { - {l1s_ctrl_sb26,SBCNF26,NO_PAR}, {NULL,NO_PAR,NO_PAR}, // frame 1 - {NULL,NO_PAR,NO_PAR}, // frame 2 - {NULL,NO_PAR,NO_PAR}, // frame 3 - {NULL,NO_PAR,NO_PAR}, // frame 4 - {l1s_read_mon_result,SBCNF26,NO_PAR},{NULL,NO_PAR,NO_PAR} // frame 5 - }; + /*----------------------------------------------------*/ + /* TASK: SBCNF26, Synchro. Burst reading in dedic/TCH.*/ + /*----------------------------------------------------*/ + /* C W W W R */ + /*----------------------------------------------------*/ + const T_FCT BLOC_SBCNF26[] = + { + {l1s_ctrl_sb26,SBCNF26,NO_PAR}, {NULL,NO_PAR,NO_PAR}, // frame 1 + {NULL,NO_PAR,NO_PAR}, // frame 2 + {NULL,NO_PAR,NO_PAR}, // frame 3 + {NULL,NO_PAR,NO_PAR}, // frame 4 + {l1s_read_mon_result,SBCNF26,NO_PAR},{NULL,NO_PAR,NO_PAR} // frame 5 + }; - /*----------------------------------------------------*/ - /* TASK: HWTEST after power-on... */ - /*----------------------------------------------------*/ - const T_FCT BLOC_HWTEST[] = - { - {l1s_ctrl_hwtest,HWTEST,NO_PAR}, {NULL,NO_PAR,NO_PAR}, // frame 1 - {NULL,NO_PAR,NO_PAR}, // frame 2 - {NULL,NO_PAR,NO_PAR}, // frame 3 - {l1s_read_hwtest,HWTEST,NO_PAR}, {NULL,NO_PAR,NO_PAR} // frame 4 - }; + /*----------------------------------------------------*/ + /* TASK: HWTEST after power-on... */ + /*----------------------------------------------------*/ + const T_FCT BLOC_HWTEST[] = + { + {l1s_ctrl_hwtest,HWTEST,NO_PAR}, {NULL,NO_PAR,NO_PAR}, // frame 1 + {NULL,NO_PAR,NO_PAR}, // frame 2 + {NULL,NO_PAR,NO_PAR}, // frame 3 + {l1s_read_hwtest,HWTEST,NO_PAR}, {NULL,NO_PAR,NO_PAR} // frame 4 + }; - #else - extern T_FCT BLOC_FB[]; - extern T_FCT BLOC_SB[]; - extern T_FCT BLOC_BCCHS[]; - extern T_FCT BLOC_BCCHN[]; - extern T_FCT BLOC_BCCHN_TOP[]; - extern T_FCT BLOC_EP[]; - extern T_FCT BLOC_SYNCHRO[]; - extern T_FCT BLOC_ADC[]; - extern T_FCT BLOC_SMSCB[]; - extern T_FCT BLOC_NP[]; - extern T_FCT BLOC_ALLC[]; - extern T_FCT BLOC_DDL[]; - extern T_FCT BLOC_DUL[]; - extern T_FCT BLOC_ADL[]; - extern T_FCT BLOC_AUL[]; - extern T_FCT BLOC_DUL_ADL_MIXED[]; - extern T_FCT BLOC_ABORT[]; - extern T_FCT BLOC_RAACC[]; - extern T_FCT BLOC_TCHTF[]; - extern T_FCT BLOC_TCHTH[]; - extern T_FCT BLOC_TCHTD[]; - extern T_FCT BLOC_TCHA[]; - extern T_FCT BLOC_FB51[]; - extern T_FCT BLOC_SB51[]; - extern T_FCT BLOC_SBCNF51[]; - extern T_FCT BLOC_FB26[]; - extern T_FCT BLOC_SB26[]; - extern T_FCT BLOC_SBCNF26[]; - extern T_FCT BLOC_HWTEST[]; -#if ((REL99 == 1) && (FF_BHO == 1)) - extern T_FCT BLOC_FBSB[]; -#endif - #if (L1_GPRS) - extern T_FCT BLOC_BCCHN_TRAN[]; - #endif +#else + extern T_FCT BLOC_FB[]; + extern T_FCT BLOC_SB[]; + extern T_FCT BLOC_BCCHS[]; + extern T_FCT BLOC_BCCHN[]; + extern T_FCT BLOC_BCCHN_TOP[]; + extern T_FCT BLOC_EP[]; + extern T_FCT BLOC_SYNCHRO[]; + extern T_FCT BLOC_ADC[]; + extern T_FCT BLOC_SMSCB[]; + extern T_FCT BLOC_NP[]; + extern T_FCT BLOC_ALLC[]; + extern T_FCT BLOC_DDL[]; + extern T_FCT BLOC_DUL[]; + extern T_FCT BLOC_ADL[]; + extern T_FCT BLOC_AUL[]; + extern T_FCT BLOC_DUL_ADL_MIXED[]; + extern T_FCT BLOC_ABORT[]; + extern T_FCT BLOC_RAACC[]; + extern T_FCT BLOC_TCHTF[]; + extern T_FCT BLOC_TCHTH[]; + extern T_FCT BLOC_TCHTD[]; + extern T_FCT BLOC_TCHA[]; + extern T_FCT BLOC_FB51[]; + extern T_FCT BLOC_SB51[]; + extern T_FCT BLOC_SBCNF51[]; + extern T_FCT BLOC_FB26[]; + extern T_FCT BLOC_SB26[]; + extern T_FCT BLOC_SBCNF26[]; + extern T_FCT BLOC_HWTEST[]; + #if (L1_GPRS) + extern T_FCT BLOC_BCCHN_TRAN[]; #endif -#endif //ndef L1_MFTAB_H + +#endif +
--- a/L1/include/l1_msgty.h Thu Jun 09 00:19:28 2016 +0000 +++ b/L1/include/l1_msgty.h Thu Jun 09 00:45:00 2016 +0000 @@ -1,9 +1,9 @@ /************* Revision Controle System Header ************* - * GSM Layer 1 software + * GSM Layer 1 software * L1_MSGTY.H * * Filename l1_msgty.h - * Copyright 2003 (C) Texas Instruments + * Copyright 2003 (C) Texas Instruments * ************* Revision Controle System Header *************/ @@ -27,9 +27,9 @@ /* TCH/4.8 -> 15 bytes */ /* TCH/2.4 -> 9 bytes */ /****************************************************************/ -typedef struct +typedef struct { - UWORD8 A[30]; + UWORD8 A[30]; } T_DATA_FRAME; @@ -37,7 +37,7 @@ /* Structure definition for L1A <-> MMI messages */ /****************************************************************/ -typedef struct +typedef struct { UWORD8 tx_flag; UWORD8 traffic_period; @@ -64,14 +64,6 @@ T_TST_HW_CONFIG_REQ; #endif // OP_L1_STANDALONE -/* Message used for software dynamic configuration */ -typedef struct -{ - UWORD8 ids_enable; // activation of IDS module - T_FACCH_TEST_PARAMS facch_test; -} -T_TST_SW_CONFIG_REQ; - typedef struct { UWORD32 mf51_fn; @@ -84,11 +76,6 @@ UWORD8 nbr_of_carriers; WORD8 s_rxlev; UWORD8 ba_id; - //added for Enhanced RSSI - UWORD16 qual_acc_idle; // accumulated rxqual meas. on different channels in Idle mode.= error bits - UWORD32 qual_nbr_meas_idle; // accumulated rxqual meas. on different channels in Idle mode.= total number of bits decoded - - } T_MPHC_RXLEV_PERIODIC_IND; @@ -123,7 +110,7 @@ } T_MPHC_NCELL_BCCH_READ; -typedef struct +typedef struct { UWORD32 fn; UWORD8 channel_request; @@ -145,24 +132,24 @@ } T_MPHC_IMMED_ASSIGN_REQ; -typedef struct +typedef struct { - T_CHANNEL_DESCRIPTION channel_desc_1; - UWORD8 channel_mode_1; - UWORD8 txpwr; - T_MOBILE_ALLOCATION frequency_list; - T_STARTING_TIME starting_time; - T_CHANNEL_DESCRIPTION channel_desc_2; - UWORD8 channel_mode_2; - T_MOBILE_ALLOCATION frequency_list_bef_sti; - T_CHANNEL_DESCRIPTION channel_desc_1_bef_sti; - T_CHANNEL_DESCRIPTION channel_desc_2_bef_sti; - UWORD8 cipher_mode; - UWORD8 a5_algorithm; - T_ENCRYPTION_KEY cipher_key; - BOOL dtx_allowed; + T_CHANNEL_DESCRIPTION channel_desc_1; + UWORD8 channel_mode_1; + UWORD8 txpwr; + T_MOBILE_ALLOCATION frequency_list; + T_STARTING_TIME starting_time; + T_CHANNEL_DESCRIPTION channel_desc_2; + UWORD8 channel_mode_2; + T_MOBILE_ALLOCATION frequency_list_bef_sti; + T_CHANNEL_DESCRIPTION channel_desc_1_bef_sti; + T_CHANNEL_DESCRIPTION channel_desc_2_bef_sti; + UWORD8 cipher_mode; + UWORD8 a5_algorithm; + T_ENCRYPTION_KEY cipher_key; + BOOL dtx_allowed; #if (AMR == 1) - T_AMR_CONFIGURATION amr_configuration; + T_AMR_CONFIGURATION amr_configuration; #endif } T_MPHC_CHANNEL_ASSIGN_REQ; @@ -170,95 +157,63 @@ typedef struct { - UWORD8 cipher_mode; - UWORD8 a5_algorithm; - T_ENCRYPTION_KEY new_ciph_param; -} -T_MPHC_SET_CIPHERING_REQ; - - -typedef struct -{ - T_CHANNEL_DESCRIPTION channel_desc; - T_MOBILE_ALLOCATION frequency_list; - T_STARTING_TIME starting_time; -} -T_MPHC_CHANGE_FREQUENCY; - - -typedef struct -{ UWORD8 txpwr; UWORD8 rand; UWORD8 channel_request; -#if (L1_FF_MULTIBAND == 0) UWORD8 powerclass_band1; UWORD8 powerclass_band2; -#endif } T_MPHC_RA_REQ; -typedef struct +typedef struct { - T_HO_PARAMS handover_command; - UWORD32 fn_offset; - UWORD32 time_alignmt; - T_ENCRYPTION_KEY cipher_key; - #if (AMR == 1) - T_AMR_CONFIGURATION amr_configuration; - #endif // (AMR == 1) - #if ((REL99 == 1) && (FF_BHO == 1)) - BOOL handover_type; + T_HO_PARAMS handover_command; + UWORD32 fn_offset; + UWORD32 time_alignmt; + T_ENCRYPTION_KEY cipher_key; + #if (AMR == 1) + T_AMR_CONFIGURATION amr_configuration; #endif } T_MPHC_ASYNC_HO_REQ; -typedef struct +typedef struct { - T_HO_PARAMS handover_command; - UWORD32 fn_offset; - UWORD32 time_alignmt; - T_ENCRYPTION_KEY cipher_key; - BOOL nci; - BOOL timing_advance_valid; - UWORD8 timing_advance; - #if (AMR == 1) - T_AMR_CONFIGURATION amr_configuration; - #endif - #if ((REL99 == 1) && (FF_BHO == 1)) - BOOL handover_type; + T_HO_PARAMS handover_command; + UWORD32 fn_offset; + UWORD32 time_alignmt; + T_ENCRYPTION_KEY cipher_key; + BOOL nci; + BOOL timing_advance_valid; + UWORD8 timing_advance; + #if (AMR == 1) + T_AMR_CONFIGURATION amr_configuration; #endif } T_MPHC_PRE_SYNC_HO_REQ; -typedef struct +typedef struct { - T_HO_PARAMS handover_command; - UWORD32 fn_offset; - UWORD32 time_alignmt; - T_ENCRYPTION_KEY cipher_key; - BOOL nci; - UWORD8 real_time_difference; -#if ((REL99 == 1) && (FF_BHO == 1)) - BOOL handover_type; -#endif // #if ((REL99 == 1) && (FF_BHO == 1)) -} + T_HO_PARAMS handover_command; + UWORD32 fn_offset; + UWORD32 time_alignmt; + T_ENCRYPTION_KEY cipher_key; + BOOL nci; + UWORD8 real_time_difference; +} T_MPHC_PSEUDO_SYNC_HO_REQ; typedef struct { - T_HO_PARAMS handover_command; - UWORD32 fn_offset; - UWORD32 time_alignmt; - T_ENCRYPTION_KEY cipher_key; - BOOL nci; - #if (AMR == 1) - T_AMR_CONFIGURATION amr_configuration; - #endif - #if ((REL99 == 1) && (FF_BHO == 1)) - BOOL handover_type; + T_HO_PARAMS handover_command; + UWORD32 fn_offset; + UWORD32 time_alignmt; + T_ENCRYPTION_KEY cipher_key; + BOOL nci; + #if (AMR == 1) + T_AMR_CONFIGURATION amr_configuration; #endif } T_MPHC_SYNC_HO_REQ; @@ -266,14 +221,10 @@ typedef struct { UWORD8 cause; - #if ((REL99 == 1) && (FF_BHO == 1)) - UWORD32 fn_offset; - UWORD32 time_alignment; - #endif } T_MPHC_HANDOVER_FINISHED; -typedef struct +typedef struct { BOOL dtx_used; BOOL meas_valid; @@ -290,32 +241,17 @@ UWORD8 ba_id; UWORD8 timing_advance; UWORD8 txpwr_used; -#if (REL99 == 1) -#if FF_EMR - WORD16 rxlev_val_acc; - UWORD8 rxlev_val_nbr_meas; - UWORD32 mean_bep_block_acc; - UWORD16 cv_bep_block_acc; - UWORD8 mean_bep_block_num; - UWORD8 cv_bep_block_num; - UWORD8 nbr_rcvd_blocks; -#endif -#endif // RESERVED: for trace/debug only UWORD8 facch_dl_count; UWORD8 facch_ul_count; - #if (FF_REPEATED_DL_FACCH == 1) - UWORD8 facch_dl_combined_good_count; /* No of good decoded blocks after combining */ - UWORD8 facch_dl_repetition_block_count; /* Total of Dl block count */ - #endif } T_MPHC_MEAS_REPORT; typedef T_NEW_BA_LIST T_MPHC_UPDATE_BA_LIST; -typedef struct +typedef struct { UWORD8 bs_pa_mfrms; UWORD8 bs_ag_blks_res; @@ -341,23 +277,13 @@ typedef T_FULL_LIST_MEAS T_L1C_VALID_MEAS_INFO; typedef T_MPHC_RXLEV_PERIODIC_IND T_L1C_RXLEV_PERIODIC_DONE; -#if (L1_FF_MULTIBAND == 0) - typedef struct - { - UWORD8 radio_band_config; // frequency band configuration: E-GSM, DCS, GSM/DCS, PCS - } - T_MPHC_INIT_L1_REQ; -#else // For Multiband the Init request is just a dummy and init confirm contains info - - typedef struct - { - T_L1_MULTIBAND_POWER_CLASS multiband_power_class[NB_MAX_GSM_BANDS]; - } - T_MPHC_INIT_L1_CON; - -#endif // L1_FF_MULTIBAND == 0 +typedef struct +{ + UWORD8 radio_band_config; // frequency band configuration: E-GSM, DCS, GSM/DCS, PCS +} +T_MPHC_INIT_L1_REQ; /****************************************************************/ /* Structure definition for Test <-> L1A messages */ @@ -365,7 +291,7 @@ typedef struct { - UWORD16 dsp_code_version; + UWORD16 dsp_code_version; UWORD16 dsp_checksum; UWORD16 dsp_patch_version; UWORD16 mcu_tcs_program_release; @@ -651,22 +577,6 @@ } T_L1C_FB_INFO; -#if ((REL99 == 1) && (FF_BHO == 1)) -typedef struct -{ - BOOL fb_flag; - BOOL sb_flag; - UWORD8 bsic; - UWORD32 fn_offset; - UWORD32 time_alignmt; - UWORD32 pm; - UWORD32 toa; - UWORD32 angle; - UWORD32 snr; -} -T_L1C_FBSB_INFO; -#endif - typedef struct { WORD8 radio_freq_array_size; @@ -734,10 +644,6 @@ UWORD8 swap_iq_band2; UWORD8 pwr_mngt; UWORD8 tx_pwr_code; - #if IDS - UWORD8 ids_enable; - #endif - T_FACCH_TEST_PARAMS facch_test; UWORD16 dwnld; UWORD8 pwr_mngt_mode_authorized; UWORD32 pwr_mngt_clocks;
--- a/L1/include/l1_proto.h Thu Jun 09 00:19:28 2016 +0000 +++ b/L1/include/l1_proto.h Thu Jun 09 00:45:00 2016 +0000 @@ -14,9 +14,6 @@ void frit_task (UWORD32 argc, void *argv); void l1s_task (UWORD32 argc, void *argv); -#if FF_L1_IT_DSP_USF -void usf_task (UWORD32 argc, void *argv); -#endif void l1s_synch (void); void l1s_task_scheduler_process (void); @@ -27,24 +24,22 @@ void l1s_merge_manager (WORD32 dl_pending_task); void l1s_dedicated_mode_manager (void); -void l1s_keep_mftab_hist (void); /**************************************/ /* prototypes of L1_PWMGR.C functions */ /**************************************/ -void l1s_sleep_manager (void); -void l1s_wakeup (void); -void l1s_wakeup_adjust (void); -void GAUGING_Handler (void); -UWORD8 l1s_recover_Os (void); -UWORD8 l1s_check_System (void); -void l1s_recover_Frame (void); -void l1s_recover_HWTimers (void); -BOOL l1s_compute_wakeup_ticks (void); -void l1s_gauging_task (void); -void l1s_gauging_task_end (void); -UWORD32 l1s_get_next_gauging_in_Packet_Idle(void); -void l1s_adapt_traffic_controller (void); +void l1s_sleep_manager (void); +void l1s_gauging_task (void); +void l1s_gauging_task_end (void); +WORD32 l1s_get_next_gauging_in_Packet_Idle(void); +void l1s_wakeup (void); +void l1s_wakeup_adjust (void); +void GAUGING_Handler (void); +UWORD8 l1s_recover_Os (void); +UWORD8 l1s_check_System (void); +void l1s_recover_Frame (void); +void l1s_recover_HWTimers (void); +BOOL l1s_compute_wakeup_ticks (void); /**************************************/ /* prototypes of L1_MFMGR.C functions */ @@ -68,9 +63,7 @@ void l1s_ctrl_fb26 (UWORD8 task, UWORD8 param2); void l1s_ctrl_sbgen (UWORD8 task, UWORD8 attempt); void l1s_ctrl_sb26 (UWORD8 task, UWORD8 param2); -#if ((REL99 == 1) && (FF_BHO == 1)) -void l1s_ctrl_fbsb (UWORD8 task , UWORD8 param2); -#endif + void l1s_ctrl_smscb (UWORD8 task, UWORD8 burst_id); void l1s_ctrl_snb_dl (UWORD8 task, UWORD8 param2); @@ -98,26 +91,16 @@ void l1s_read_dedic_dl (UWORD8 task, UWORD8 burst_id); void l1s_read_tx_result (UWORD8 param1, UWORD8 param2); - -#if FF_EMR - void l1s_read_dedic_scell_meas (UWORD8 meas, UWORD8 sub_flag, T_EMR_PARAMS *emr_params); -#else //FF_EMR void l1s_read_dedic_scell_meas (UWORD8 meas, UWORD8 sub_flag); -#endif //FF_EMR void l1s_dedic_reporting (void); void l1s_read_fb (UWORD8 task, UWORD32 fb_flag, UWORD32 toa, UWORD32 attempt, UWORD32 pm, UWORD32 angle, UWORD32 snr); void l1s_read_sb (UWORD8 task,UWORD32 flag, API *data, UWORD32 toa, UWORD8 attempt, UWORD32 pm, UWORD32 angle, UWORD32 snr); -#if ((REL99 == 1) && (FF_BHO == 1)) -void l1s_read_fbsb (UWORD8 task, UWORD8 attempt, BOOL fb_flag, BOOL sb_flag, API *data, - UWORD32 toa, UWORD32 pm, UWORD32 angle, UWORD32 snr); -#endif void l1s_read_sacch_dl (API *info_address, UWORD32 task_rx); void l1s_read_dcch_dl (API *info_address, UWORD32 task_rx); void l1s_read_l3frm (UWORD8 pwr_level, API *info_address, UWORD32 task_rx); -void l1s_reset_tx_ptr(UWORD8 param1, UWORD8 param2); /**************************************/ @@ -139,24 +122,24 @@ UWORD8 l1a_encode_rxqual (UWORD32 inlevel); void l1a_report_failling_ncell_sync (UWORD32 SignalCode, UWORD8 neigh_id); UWORD8 l1a_clip_txpwr (UWORD8 supplied_txpwr, UWORD16 radio_freq); -void l1a_add_time_delta (UWORD32 *time_alignmt, UWORD32 *fn_offset, WORD32 delta); -void l1a_compensate_sync_ind (T_MPHC_NCELL_SYNC_IND * msg); -void l1a_compute_Eotd_data (UWORD8 *first_scell, UWORD8 neigh_id, UWORD32 SignalCode, xSignalHeaderRec *msg); -void l1a_correct_timing (UWORD8 neigh_id,UWORD32 time_alignmt,UWORD32 fn_offset); +void l1a_correct_timing (UWORD8 neigh_id,UWORD32 time_alignmt,UWORD32 fn_offset); +void l1a_add_time_delta (UWORD32 *time_alignmt, UWORD32 *fn_offset, WORD32 delta); +void l1a_compensate_sync_ind (T_MPHC_NCELL_SYNC_IND * msg); +void l1a_compute_Eotd_data (UWORD8 *first_scell, UWORD8 neigh_id, UWORD32 SignalCode, xSignalHeaderRec *msg); +#if (L1_MPHC_RXLEV_IND_REPORT_SORT==1) +void l1a_sort_freq_reported_in_rxlev_ind(T_POWER_ARRAY *data_tab,UWORD16 data_tab_size,UWORD16 *index_tab,UWORD16 index_tab_size); +#endif /**************************************/ /* prototypes of L1_FUNC functions */ /**************************************/ void dsp_power_on (void); -#if ((ANALOG == 1) || (ANALOG == 2) || (ANALOG == 3) || (ANALOG == 11)) +#if ((ANALOG == 1) || (ANALOG == 2) || (ANALOG == 3)) void l1_abb_power_on (void); #endif void tpu_init (void); void l1s_reset_db_mcu_to_dsp (T_DB_MCU_TO_DSP *page_ptr); -#if (DSP == 38) || (DSP == 39) -void l1s_reset_db_common_mcu_to_dsp (T_DB_COMMON_MCU_TO_DSP *page_ptr); -#endif void l1s_reset_db_dsp_to_mcu (T_DB_DSP_TO_MCU *page_ptr); void initialize_l1var (void); void l1_initialize (T_MMI_L1_CONFIG *mmi_l1_config); @@ -174,7 +157,6 @@ UWORD8 l1s_amr_get_ratscch_type (API *a_ratscch_dl); void l1s_amr_update_from_ratscch (API *a_ratscch_dl); #endif -void l1_memcpy_16bit(void *dst,void* src,unsigned int len); /**************************************/ @@ -182,10 +164,6 @@ /**************************************/ // MCU-DSP interface drivers. //--------------------------- - -#if (FF_L1_FAST_DECODING == 1) -void l1ddsp_load_fast_dec_task(API task, UWORD8 burst_id); -#endif void l1ddsp_load_info (UWORD32 task, API *info_ptr, UWORD8 *data); @@ -203,21 +181,6 @@ void l1ddsp_load_txpwr (UWORD8 txpwr, UWORD16 radio_freq); - -// SAIC low level driver function -#if (L1_SAIC != 0) -void l1ddsp_load_swh_flag (UWORD16 SWH_flag, UWORD16 SAIC_flag); -#endif - -void l1ddsp_read_iq_dump(UWORD8 task); -void l1ddsp_apc_load_apcctrl2(UWORD16 apcctrl2); -void l1ddsp_apc_set_manual_mode(void); -void l1ddsp_apc_set_automatic_mode(void); - -#ifdef TESTMODE - void l1ddsp_apc_load_apclev(UWORD16 apclev); -#endif - #if (AMR == 1) #if (FF_L1_TCH_VOCODER_CONTROL == 1) // Add the AMR synchro bit in the driver's paramters @@ -229,25 +192,15 @@ UWORD8 sync_tch, UWORD8 sync_amr, UWORD8 reset_sacch, - #if !FF_L1_IT_DSP_DTX UWORD8 vocoder_on); #else - UWORD8 vocoder_on, - BOOL dtx_dsp_interrupt); - #endif - #else void l1ddsp_load_tch_param (T_TIME_INFO *next_time, UWORD8 chan_mode, UWORD8 chan_type, UWORD8 subchannel, UWORD8 tch_loop, UWORD8 sync_tch, - #if !FF_L1_IT_DSP_DTX UWORD8 sync_amr); - #else - UWORD8 sync_amr, - BOOL dtx_dsp_interrupt); - #endif #endif #else #if (FF_L1_TCH_VOCODER_CONTROL == 1) @@ -258,41 +211,31 @@ UWORD8 tch_loop, UWORD8 sync_tch, UWORD8 reset_sacch, - #if !FF_L1_IT_DSP_DTX UWORD8 vocoder_on); #else - UWORD8 vocoder_on, - BOOL dtx_dsp_interrupt); - #endif - #else void l1ddsp_load_tch_param (T_TIME_INFO *next_time, UWORD8 chan_mode, UWORD8 chan_type, UWORD8 subchannel, UWORD8 tch_loop, - #if !FF_L1_IT_DSP_DTX UWORD8 sync_tch); - #else - UWORD8 sync_tch, - BOOL dtx_dsp_interrupt); - #endif #endif #endif -#if (L1_VOCODER_IF_CHANGE == 0) -BOOL enable_tch_vocoder (BOOL vocoder_on); -#endif // L1_VOCODER_IF_CHANGE == 0 +BOOL enable_tch_vocoder (BOOL vocoder_on); + BOOL l1_select_mcsi_port (UWORD8 port); -void l1ddsp_load_ciph_param (UWORD8 a5mode, - T_ENCRYPTION_KEY *ciph_key); -void l1ddsp_load_tch_mode (UWORD8 dai_mode, - BOOL dtx_allowed); +void l1ddsp_load_ciph_param (UWORD8 a5mode, + T_ENCRYPTION_KEY *ciph_key); +void l1ddsp_load_tch_mode (UWORD8 dai_mode, + BOOL dtx_allowed); #if (AMR == 1) - void l1ddsp_load_amr_param (T_AMR_CONFIGURATION amr_param, UWORD8 cmip); +void l1ddsp_load_amr_param (T_AMR_CONFIGURATION amr_param, UWORD8 cmip); #endif -void l1ddsp_stop_tch (void); -void l1ddsp_load_afc (API afc); + +void l1ddsp_stop_tch (void); + // MCU-TPU interface drivers. //--------------------------- @@ -301,12 +244,7 @@ UWORD8 lna_off, UWORD16 win_id, UWORD16 tpu_synchro, - UWORD8 adc_active -#if(RF_FAM == 61) - ,UWORD8 afc_mode - ,UWORD8 if_ctl -#endif - ); + UWORD8 adc_active); void l1dtpu_neig_fb (UWORD16 radio_freq, WORD8 agc, UWORD8 lna_off); @@ -320,36 +258,20 @@ UWORD32 time_alignmt, UWORD32 offset_serv, UWORD8 reload_flag, - UWORD8 attempt -#if(RF_FAM == 61) - ,UWORD8 if_ctl -#endif - ); + UWORD8 attempt); void l1dtpu_neig_sb26 (UWORD16 radio_freq, WORD8 agc, UWORD8 lna_off, UWORD32 time_alignmt, UWORD32 fn_offset, - UWORD32 offset_serv -#if(RF_FAM == 61) - ,UWORD8 if_ctl -#endif - ); + UWORD32 offset_serv); void l1dtpu_serv_rx_nb (UWORD16 radio_freq, WORD8 agc, UWORD8 lna_off, UWORD32 synchro_serv, UWORD32 new_offset, BOOL change_offset, - UWORD8 adc_active -#if(RF_FAM == 61) - ,UWORD8 csf_filter_choice - ,UWORD8 if_ctl -#endif -#if (NEW_SNR_THRESHOLD == 1) - ,UWORD8 saic_flag -#endif /* NEW_SNR_THRESHOLD*/ - ); + UWORD8 adc_active); void l1dtpu_serv_tx_nb (UWORD16 radio_freq, UWORD8 timing_advance, UWORD32 offset_serv, @@ -361,15 +283,7 @@ UWORD32 time_alignmt, UWORD32 offset_serv, UWORD8 reload_flag, - UWORD8 nop -#if(RF_FAM == 61) - ,UWORD8 if_ctl -#endif -#if (NEW_SNR_THRESHOLD == 1) - ,UWORD8 saic_flag -#endif /* NEW_SNR_THRESHOLD*/ - ); - + UWORD8 nop); void l1dtpu_serv_tx_ra (UWORD16 radio_freq, UWORD32 offset_serv, UWORD8 txpwr, @@ -427,11 +341,7 @@ void l1a_idle_full_list_meas_process (xSignalHeaderRec *msg); void l1a_test_process (xSignalHeaderRec *msg); void l1a_freq_band_configuration (xSignalHeaderRec *msg); -void l1a_at_power_process (xSignalHeaderRec *msg); -#if(L1_CHECK_COMPATIBLE == 1) -void l1a_checkmsg_compatibility (xSignalHeaderRec *msg); -#endif #if (OP_L1_STANDALONE == 1) // Dynamic configuration process for L1 standalone only void l1a_test_config_process (xSignalHeaderRec *msg); @@ -458,8 +368,9 @@ /**************************************/ /* Prototypes for Nu_main. */ /**************************************/ +UWORD32 get_arm_version (void); +void usart_hisr (void); void Adc_timer (UWORD32 id); - /**************************************/ /* Prototypes for l2 task */ /**************************************/ @@ -478,26 +389,13 @@ UWORD8 *tx_tch_data (void); #if (SEND_FN_TO_L2_IN_DCCH==1) -#if (L1_SAGEM_INTERFACE == 1) -void dll_dcch_downlink (API *info_address, - UWORD8 valid_flag, - UWORD32 frame_number, - UWORD8 channel_type); -#else void dll_dcch_downlink (API *info_address, UWORD8 valid_flag, UWORD32 frame_number); -#endif -#else -#if (L1_SAGEM_INTERFACE == 1) -void dll_dcch_downlink (API *info_address, - UWORD8 valid_flag, - UWORD8 channel_type); #else void dll_dcch_downlink (API *info_address, UWORD8 valid_flag); #endif -#endif /***************************************/ /* Prototypes of L1_TRACE.c functions */ @@ -505,6 +403,7 @@ void l1_trace_message (xSignalHeaderRec *msg); void send_debug_sig (UWORD8 debug_code, UWORD8 task); void l1_trace_cpu_load (UWORD8 cpu_load); +void l1_trace_ratscch(UWORD16 fn, UWORD16 amr_change_bitmap); #if (TRACE_TYPE==7) // CPU_LOAD void l1_cpu_load_start (void); @@ -516,6 +415,7 @@ /***************************************/ /* Prototypes of HW_DEBUG.c functions */ /***************************************/ +void get_usart_characters (void); // HISR for Rx characters void wait_for_next_message (CHAR *); /***************************************/ @@ -535,7 +435,7 @@ void trace_msg (CHAR *msg_name, CHAR *queue_name); void log_msg (CHAR *msg_name, CHAR *queue_name); void trace_dedic (void); -void trace_fct_simu (CHAR *fct_name, UWORD32 radio_freq); +void trace_fct_simu (CHAR *fct_name, WORD32 radio_freq); void trace_flowchart_msg (CHAR *msg_name, CHAR *dest_queue_name); void trace_flowchart_l1tsk (UWORD32 bit_register, UWORD32 *src_register_set); void trace_flowchart_dedic (WORD32 SignalCode); @@ -546,14 +446,6 @@ void trace_flowchart_dsptx (CHAR *task_name); void trace_flowchart_header (void); void trace_sim_freq_band_configuration (UWORD8 freq_band_config); -#if (TOA_ALGO == 2) - void trace_toa_sim_ctrl (UWORD16 SNR_val, UWORD16 TOA_val, UWORD32 l1_mode, - UWORD32 frames_counter, UWORD32 cumul_counter,WORD16 cumul); - void trace_toa_sim_update (WORD16 toa_shift, UWORD32 tpu_offset); -#endif -#if (L1_SAIC != 0) - void trace_saic_sim (UWORD32 Il_for_rxlev, UWORD32 l1_mode, UWORD32 SWH_flag); -#endif /**************************************/ /* prototypes of control functions */ @@ -572,36 +464,12 @@ UWORD16 radio_freq, UWORD32 l1_mode); #endif - -#if (TOA_ALGO == 2) -WORD16 l1ctl_toa (UWORD8 phase, - UWORD32 l1_mode, - UWORD16 SNR_val, - UWORD16 TOA_val); -#else WORD16 l1ctl_toa (UWORD8 phase, UWORD32 l1_mode, UWORD16 SNR_val, UWORD16 TOA_val, BOOL *toa_update, - UWORD16 *toa_period_count -#if (FF_L1_FAST_DECODING == 1) - ,UWORD8 skipped_values -#endif /* FF_L1_FAST_DECODING */ - ); -#endif - -// SAIC Control Function -#if (L1_SAIC != 0) -UWORD8 l1ctl_saic (UWORD8 IL_for_rxlev, - UWORD32 l1_mode -#if (NEW_SNR_THRESHOLD == 1) - ,UWORD8 task, - UWORD8 * saic_flag -#endif /* NEW_SNR_THRESHOLD*/ -); -#endif - + UWORD16 *toa_period_count); UWORD8 l1ctl_txpwr (UWORD8 target_txpwr, UWORD8 current_txpwr); @@ -612,7 +480,6 @@ UWORD16 radio_freq); UWORD8 l1ctl_find_max (UWORD8 *buff, UWORD8 buffer_len); - // Automatic Gain Control Algorithms void l1ctl_pgc2 (UWORD8 pm_high_agc, UWORD8 pm_low_agc, @@ -641,62 +508,18 @@ UWORD16 l1ctl_get_g_magic (UWORD16 radio_freq); UWORD16 l1ctl_get_lna_att (UWORD16 radio_freq); -UWORD16 l1ctl_update_TPU_with_toa(void); - -#if (FF_L1_FAST_DECODING == 1) -void l1ctl_pagc_missing_bursts (UWORD8 skipped_values); -#endif +void l1ctl_update_TPU_with_toa(void); //functions for customization void Cust_init_std (void); void Cust_init_params (void); -WORD8 Cust_get_agc_from_IL (UWORD16 radio_freq, UWORD16 agc_index, UWORD8 table_id,UWORD8 lna_off_val); +WORD8 Cust_get_agc_from_IL (UWORD16 radio_freq, UWORD16 agc_index, UWORD8 table_id); WORD8 l1ctl_encode_delta1 (UWORD16 radio_freq); WORD8 l1ctl_encode_delta2 (UWORD16 radio_freq); void Cust_get_ramp_tab (API *a_ramp, UWORD8 txpwr_ramp_up, UWORD8 txpwr_ramp_down, UWORD16 radio_freq); -#if ((ANALOG == 1) || (ANALOG == 2) || (ANALOG == 3) || (RF_FAM == 61)) - UWORD16 Cust_get_pwr_data(UWORD8 txpwr, UWORD16 radio_freq - #if(REL99 && FF_PRF) - ,UWORD8 number_uplink_timeslot - #endif - ); -#endif - -#if (RF_FAM == 61) -void l1_drp_wrapper_init (void); -void l1_drp_init (void); -void l1dapc_init_ramp_tables(void ); -void cust_get_if_dco_ctl_algo (UWORD16* dco_algo_ctl, UWORD8* if_ctl, - UWORD8 input_level_flag, UWORD8 input_level, UWORD16 radio_freq, UWORD8 if_threshold); +#if ((ANALOG == 1) || (ANALOG == 2) || (ANALOG == 3)) + UWORD16 Cust_get_pwr_data(UWORD8 txpwr, UWORD16 radio_freq); #endif -void l1s_restore_synchro(void); - -#if (FF_L1_FAST_DECODING == 1) -BOOL l1s_check_deferred_control(UWORD8 task, UWORD8 burst_id); -BOOL l1s_check_fast_decoding_authorized(UWORD8 task); -#endif /* FF_L1_FAST_DECODING */ - -#if (DRP_FW_EXT == 1) -void l1_get_boot_result_and_version(T_L1_BOOT_VERSION_CODE * p_version); -#endif /* DRP_FW_EXT */ - -/*-----------------------------------------------------------------*/ -/* Prototypes of MULTIBAND related functions */ -/*-----------------------------------------------------------------*/ -#if (L1_FF_MULTIBAND == 1) -#if 0 -UWORD16 l1_multiband_radio_freq_convert_into_operative_radio_freq(UWORD16 radio_freq); -UWORD8 l1_multiband_radio_freq_convert_into_physical_band_id(UWORD16 radio_freq); -UWORD8 l1_multiband_radio_freq_convert_into_effective_band_id(UWORD16 radio_freq); -void l1_multiband_fill_power_meas_array(UWORD16 power_array_size, T_FULL_LIST_MEAS *full_list); -UWORD8 l1_multiband_map_radio_freq_into_tpu_table(UWORD16 radio_freq); -void l1_multiband_increment_effective_band_id(UWORD8 *effective_band_id); -void l1_multiband_trace_params(UWORD8 multiband_table_id, UWORD8 multiband_trace_id) ; -void l1_multiband_tpu_get_power_classes(T_L1_MULTIBAND_POWER_CLASS multiband_power_class[]); -void l1_multiband_error_handler(UWORD16 radio_freq); -#endif // if 0 - -#endif /*if(L1_FF_MULTIBAND == 1)*/
--- a/L1/include/l1_rtt_macro.h Thu Jun 09 00:19:28 2016 +0000 +++ b/L1/include/l1_rtt_macro.h Thu Jun 09 00:45:00 2016 +0000 @@ -38,14 +38,12 @@ #define RTTL1_FILL_FN(param1) \ if(SELECTED_BITMAP(RTTL1_ENABLE_FN)) \ { \ - T_RTT_PTR *ptr; \ - T_RTTL1_FN *ptr2; \ + T_RTT_PTR ptr; \ \ - ptr = (T_RTT_PTR *) &ptr2; \ - if ((*ptr = trace_info.l1s_rtt_func.rtt_get_fill_ptr(trace_info.l1s_trace_user_id, sizeof(T_RTTL1_FN))) != NULL) \ + if ((ptr = trace_info.l1s_rtt_func.rtt_get_fill_ptr(trace_info.l1s_trace_user_id, sizeof(T_RTTL1_FN))) != NULL) \ { \ - ptr2->fn = param1; \ - ptr2->cell_id = RTTL1_ENABLE_FN; \ + ((T_RTTL1_FN *)ptr)->fn = param1; \ + ((T_RTTL1_FN *)ptr)->cell_id = RTTL1_ENABLE_FN; \ } \ } @@ -55,20 +53,18 @@ #define RTTL1_FILL_DL_BURST(param1,param2,param3,param4,param5,param6,param7) \ if(SELECTED_BITMAP(RTTL1_ENABLE_DL_BURST)) \ { \ - T_RTT_PTR *ptr; \ - T_RTTL1_DL_BURST *ptr2; \ + T_RTT_PTR ptr; \ \ - ptr = (T_RTT_PTR *) &ptr2; \ - if ((*ptr = trace_info.l1s_rtt_func.rtt_get_fill_ptr(trace_info.l1s_trace_user_id, sizeof(T_RTTL1_DL_BURST))) != NULL) \ + if ((ptr = trace_info.l1s_rtt_func.rtt_get_fill_ptr(trace_info.l1s_trace_user_id, sizeof(T_RTTL1_DL_BURST))) != NULL) \ { \ - ptr2->angle = param1; \ - ptr2->snr = param2; \ - ptr2->afc = param3; \ - ptr2->task = param4; \ - ptr2->pm = param5; \ - ptr2->toa = param6; \ - ptr2->input_level = param7; \ - ptr2->cell_id = RTTL1_ENABLE_DL_BURST; \ + ((T_RTTL1_DL_BURST *)ptr)->angle = param1; \ + ((T_RTTL1_DL_BURST *)ptr)->snr = param2; \ + ((T_RTTL1_DL_BURST *)ptr)->afc = param3; \ + ((T_RTTL1_DL_BURST *)ptr)->task = param4; \ + ((T_RTTL1_DL_BURST *)ptr)->pm = param5; \ + ((T_RTTL1_DL_BURST *)ptr)->toa = param6; \ + ((T_RTTL1_DL_BURST *)ptr)->input_level = param7; \ + ((T_RTTL1_DL_BURST *)ptr)->cell_id = RTTL1_ENABLE_DL_BURST; \ } \ } @@ -78,16 +74,14 @@ #define RTTL1_FILL_UL_NB(param1, param2, param3) \ if(SELECTED_BITMAP(RTTL1_ENABLE_UL_NB)) \ { \ - T_RTT_PTR *ptr; \ - T_RTTL1_UL_NB *ptr2; \ + T_RTT_PTR ptr; \ \ - ptr = (T_RTT_PTR *) &ptr2; \ - if ((*ptr = trace_info.l1s_rtt_func.rtt_get_fill_ptr(trace_info.l1s_trace_user_id, sizeof(T_RTTL1_UL_NB))) != NULL) \ + if ((ptr = trace_info.l1s_rtt_func.rtt_get_fill_ptr(trace_info.l1s_trace_user_id, sizeof(T_RTTL1_UL_NB))) != NULL) \ { \ - ptr2->task = param1; \ - ptr2->ta = param2; \ - ptr2->txpwr = param3; \ - ptr2->cell_id = RTTL1_ENABLE_UL_NB; \ + ((T_RTTL1_UL_NB *)ptr)->task = param1; \ + ((T_RTTL1_UL_NB *)ptr)->ta = param2; \ + ((T_RTTL1_UL_NB *)ptr)->txpwr = param3; \ + ((T_RTTL1_UL_NB *)ptr)->cell_id = RTTL1_ENABLE_UL_NB; \ } \ } @@ -97,15 +91,13 @@ #define RTTL1_FILL_UL_AB(param1, param2) \ if(SELECTED_BITMAP(RTTL1_ENABLE_UL_AB)) \ { \ - T_RTT_PTR *ptr; \ - T_RTTL1_UL_AB *ptr2; \ + T_RTT_PTR ptr; \ \ - ptr = (T_RTT_PTR *) &ptr2; \ - if ((*ptr = trace_info.l1s_rtt_func.rtt_get_fill_ptr(trace_info.l1s_trace_user_id, sizeof(T_RTTL1_UL_AB))) != NULL) \ + if ((ptr = trace_info.l1s_rtt_func.rtt_get_fill_ptr(trace_info.l1s_trace_user_id, sizeof(T_RTTL1_UL_AB))) != NULL) \ { \ - ptr2->task = param1; \ - ptr2->txpwr = param2; \ - ptr2->cell_id = RTTL1_ENABLE_UL_AB; \ + ((T_RTTL1_UL_AB *)ptr)->task = param1; \ + ((T_RTTL1_UL_AB *)ptr)->txpwr = param2; \ + ((T_RTTL1_UL_AB *)ptr)->cell_id = RTTL1_ENABLE_UL_AB; \ } \ } @@ -115,17 +107,15 @@ #define RTTL1_FILL_FULL_LIST_MEAS(param1, param2, param3, param4) \ if(SELECTED_BITMAP(RTTL1_ENABLE_FULL_LIST_MEAS)) \ { \ - T_RTT_PTR *ptr; \ - T_RTTL1_FULL_LIST_MEAS *ptr2; \ + T_RTT_PTR ptr; \ \ - ptr = (T_RTT_PTR *) &ptr2; \ - if ((*ptr = trace_info.l1s_rtt_func.rtt_get_fill_ptr(trace_info.l1s_trace_user_id, sizeof(T_RTTL1_FULL_LIST_MEAS))) != NULL) \ + if ((ptr = trace_info.l1s_rtt_func.rtt_get_fill_ptr(trace_info.l1s_trace_user_id, sizeof(T_RTTL1_FULL_LIST_MEAS))) != NULL) \ { \ - ptr2->pm = param1; \ - ptr2->input_level = param2; \ - ptr2->task = param3; \ - ptr2->radio_freq = param4; \ - ptr2->cell_id = RTTL1_ENABLE_FULL_LIST_MEAS; \ + ((T_RTTL1_FULL_LIST_MEAS *)ptr)->pm = param1; \ + ((T_RTTL1_FULL_LIST_MEAS *)ptr)->input_level = param2; \ + ((T_RTTL1_FULL_LIST_MEAS *)ptr)->task = param3; \ + ((T_RTTL1_FULL_LIST_MEAS *)ptr)->radio_freq = param4; \ + ((T_RTTL1_FULL_LIST_MEAS *)ptr)->cell_id = RTTL1_ENABLE_FULL_LIST_MEAS; \ } \ } @@ -135,17 +125,15 @@ #define RTTL1_FILL_MON_MEAS(param1, param2, param3, param4) \ if(SELECTED_BITMAP(RTTL1_ENABLE_MON_MEAS)) \ { \ - T_RTT_PTR *ptr; \ - T_RTTL1_MON_MEAS *ptr2; \ + T_RTT_PTR ptr; \ \ - ptr = (T_RTT_PTR *) &ptr2; \ - if ((*ptr = trace_info.l1s_rtt_func.rtt_get_fill_ptr(trace_info.l1s_trace_user_id, sizeof(T_RTTL1_MON_MEAS))) != NULL) \ + if ((ptr = trace_info.l1s_rtt_func.rtt_get_fill_ptr(trace_info.l1s_trace_user_id, sizeof(T_RTTL1_MON_MEAS))) != NULL) \ { \ - ptr2->pm = param1; \ - ptr2->input_level = param2; \ - ptr2->task = param3; \ - ptr2->radio_freq = param4; \ - ptr2->cell_id = RTTL1_ENABLE_MON_MEAS; \ + ((T_RTTL1_MON_MEAS *)ptr)->pm = param1; \ + ((T_RTTL1_MON_MEAS *)ptr)->input_level = param2; \ + ((T_RTTL1_MON_MEAS *)ptr)->task = param3; \ + ((T_RTTL1_MON_MEAS *)ptr)->radio_freq = param4; \ + ((T_RTTL1_MON_MEAS *)ptr)->cell_id = RTTL1_ENABLE_MON_MEAS; \ } \ } @@ -155,15 +143,13 @@ #define RTTL1_FILL_DL_DCCH(param1, param2) \ if(SELECTED_BITMAP(RTTL1_ENABLE_DL_DCCH)) \ { \ - T_RTT_PTR *ptr; \ - T_RTTL1_DL_DCCH *ptr2; \ + T_RTT_PTR ptr; \ \ - ptr = (T_RTT_PTR *) &ptr2; \ - if ((*ptr = trace_info.l1s_rtt_func.rtt_get_fill_ptr(trace_info.l1s_trace_user_id, sizeof(T_RTTL1_DL_DCCH))) != NULL) \ + if ((ptr = trace_info.l1s_rtt_func.rtt_get_fill_ptr(trace_info.l1s_trace_user_id, sizeof(T_RTTL1_DL_DCCH))) != NULL) \ { \ - ptr2->valid_flag = param1; \ - ptr2->physical_info = param2; \ - ptr2->cell_id = RTTL1_ENABLE_DL_DCCH; \ + ((T_RTTL1_DL_DCCH *)ptr)->valid_flag = param1; \ + ((T_RTTL1_DL_DCCH *)ptr)->physical_info = param2; \ + ((T_RTTL1_DL_DCCH *)ptr)->cell_id = RTTL1_ENABLE_DL_DCCH; \ } \ } @@ -173,15 +159,13 @@ #define RTTL1_FILL_DL_PTCCH(param1, param2) \ if(SELECTED_BITMAP(RTTL1_ENABLE_DL_PTCCH)) \ { \ - T_RTT_PTR *ptr; \ - T_RTTL1_DL_PTCCH *ptr2; \ + T_RTT_PTR ptr; \ \ - ptr = (T_RTT_PTR *) &ptr2; \ - if ((*ptr = trace_info.l1s_rtt_func.rtt_get_fill_ptr(trace_info.l1s_trace_user_id, sizeof(T_RTTL1_DL_PTCCH))) != NULL) \ + if ((ptr = trace_info.l1s_rtt_func.rtt_get_fill_ptr(trace_info.l1s_trace_user_id, sizeof(T_RTTL1_DL_PTCCH))) != NULL) \ { \ - ptr2->crc = param1; \ - ptr2->ordered_ta = param2; \ - ptr2->cell_id = RTTL1_ENABLE_DL_PTCCH; \ + ((T_RTTL1_DL_PTCCH *)ptr)->crc = param1; \ + ((T_RTTL1_DL_PTCCH *)ptr)->ordered_ta = param2; \ + ((T_RTTL1_DL_PTCCH *)ptr)->cell_id = RTTL1_ENABLE_DL_PTCCH; \ } \ } @@ -191,13 +175,11 @@ #define RTTL1_FILL_UL_DCCH \ if(SELECTED_BITMAP(RTTL1_ENABLE_UL_DCCH)) \ { \ - T_RTT_PTR *ptr; \ - T_RTTL1_UL_DCCH *ptr2; \ + T_RTT_PTR ptr; \ \ - ptr = (T_RTT_PTR *) &ptr2; \ - if ((*ptr = trace_info.l1s_rtt_func.rtt_get_fill_ptr(trace_info.l1s_trace_user_id, sizeof(T_RTTL1_UL_DCCH))) != NULL) \ + if ((ptr = trace_info.l1s_rtt_func.rtt_get_fill_ptr(trace_info.l1s_trace_user_id, sizeof(T_RTTL1_UL_DCCH))) != NULL) \ { \ - ptr2->cell_id = RTTL1_ENABLE_UL_DCCH; \ + ((T_RTTL1_UL_DCCH *)ptr)->cell_id = RTTL1_ENABLE_UL_DCCH; \ } \ } @@ -207,16 +189,14 @@ #define RTTL1_FILL_UL_SACCH(param1, param2, param3) \ if(SELECTED_BITMAP(RTTL1_ENABLE_UL_SACCH)) \ { \ - T_RTT_PTR *ptr; \ - T_RTTL1_UL_SACCH *ptr2; \ + T_RTT_PTR ptr; \ \ - ptr = (T_RTT_PTR *) &ptr2; \ - if ((*ptr = trace_info.l1s_rtt_func.rtt_get_fill_ptr(trace_info.l1s_trace_user_id, sizeof(T_RTTL1_UL_SACCH))) != NULL) \ + if ((ptr = trace_info.l1s_rtt_func.rtt_get_fill_ptr(trace_info.l1s_trace_user_id, sizeof(T_RTTL1_UL_SACCH))) != NULL) \ { \ - ptr2->data_present = param1; \ - ptr2->reported_ta = param2; \ - ptr2->reported_txpwr = param3; \ - ptr2->cell_id = RTTL1_ENABLE_UL_SACCH; \ + ((T_RTTL1_UL_SACCH *)ptr)->data_present = param1; \ + ((T_RTTL1_UL_SACCH *)ptr)->reported_ta = param2; \ + ((T_RTTL1_UL_SACCH *)ptr)->reported_txpwr = param3; \ + ((T_RTTL1_UL_SACCH *)ptr)->cell_id = RTTL1_ENABLE_UL_SACCH; \ } \ } @@ -226,18 +206,16 @@ #define RTTL1_FILL_DL_PDTCH(param1, param2, param3, param4, param5) \ if(SELECTED_BITMAP(RTTL1_ENABLE_DL_PDTCH)) \ { \ - T_RTT_PTR *ptr; \ - T_RTTL1_DL_PDTCH *ptr2; \ + T_RTT_PTR ptr; \ \ - ptr = (T_RTT_PTR *) &ptr2; \ - if ((*ptr = trace_info.l1s_rtt_func.rtt_get_fill_ptr(trace_info.l1s_trace_user_id, sizeof(T_RTTL1_DL_PDTCH))) != NULL) \ + if ((ptr = trace_info.l1s_rtt_func.rtt_get_fill_ptr(trace_info.l1s_trace_user_id, sizeof(T_RTTL1_DL_PDTCH))) != NULL) \ { \ - ptr2->mac_header = param1; \ - ptr2->tfi_result = param2; \ - ptr2->crc = param3; \ - ptr2->cs_type = param4; \ - ptr2->timeslot = param5; \ - ptr2->cell_id = RTTL1_ENABLE_DL_PDTCH; \ + ((T_RTTL1_DL_PDTCH *)ptr)->mac_header = param1; \ + ((T_RTTL1_DL_PDTCH *)ptr)->tfi_result = param2; \ + ((T_RTTL1_DL_PDTCH *)ptr)->crc = param3; \ + ((T_RTTL1_DL_PDTCH *)ptr)->cs_type = param4; \ + ((T_RTTL1_DL_PDTCH *)ptr)->timeslot = param5; \ + ((T_RTTL1_DL_PDTCH *)ptr)->cell_id = RTTL1_ENABLE_DL_PDTCH; \ } \ } @@ -247,16 +225,14 @@ #define RTTL1_FILL_UL_PDTCH(param1, param2, param3) \ if(SELECTED_BITMAP(RTTL1_ENABLE_UL_PDTCH)) \ { \ - T_RTT_PTR *ptr; \ - T_RTTL1_UL_PDTCH *ptr2; \ + T_RTT_PTR ptr; \ \ - ptr = (T_RTT_PTR *) &ptr2; \ - if ((*ptr = trace_info.l1s_rtt_func.rtt_get_fill_ptr(trace_info.l1s_trace_user_id, sizeof(T_RTTL1_UL_PDTCH))) != NULL) \ + if ((ptr = trace_info.l1s_rtt_func.rtt_get_fill_ptr(trace_info.l1s_trace_user_id, sizeof(T_RTTL1_UL_PDTCH))) != NULL) \ { \ - ptr2->cs_type = param1; \ - ptr2->data_allowed = param2; \ - ptr2->timeslot = param3; \ - ptr2->cell_id = RTTL1_ENABLE_UL_PDTCH; \ + ((T_RTTL1_UL_PDTCH *)ptr)->cs_type = param1; \ + ((T_RTTL1_UL_PDTCH *)ptr)->data_allowed = param2; \ + ((T_RTTL1_UL_PDTCH *)ptr)->timeslot = param3; \ + ((T_RTTL1_UL_PDTCH *)ptr)->cell_id = RTTL1_ENABLE_UL_PDTCH; \ } \ } @@ -266,15 +242,13 @@ #define RTTL1_FILL_MACS_STATUS(param1, param2) \ if(SELECTED_BITMAP(RTTL1_ENABLE_MACS_STATUS)) \ { \ - T_RTT_PTR *ptr; \ - T_RTTL1_MACS_STATUS *ptr2; \ + T_RTT_PTR ptr; \ \ - ptr = (T_RTT_PTR *) &ptr2; \ - if ((*ptr = trace_info.l1s_rtt_func.rtt_get_fill_ptr(trace_info.l1s_trace_user_id, sizeof(T_RTTL1_MACS_STATUS))) != NULL) \ + if ((ptr = trace_info.l1s_rtt_func.rtt_get_fill_ptr(trace_info.l1s_trace_user_id, sizeof(T_RTTL1_MACS_STATUS))) != NULL) \ { \ - ptr2->status = param1; \ - ptr2->timeslot = param2; \ - ptr2->cell_id = RTTL1_ENABLE_MACS_STATUS; \ + ((T_RTTL1_MACS_STATUS *)ptr)->status = param1; \ + ((T_RTTL1_MACS_STATUS *)ptr)->timeslot = param2; \ + ((T_RTTL1_MACS_STATUS *)ptr)->cell_id = RTTL1_ENABLE_MACS_STATUS; \ } \ } @@ -284,15 +258,13 @@ #define RTTL1_FILL_L1S_TASK_ENABLE(param1, param2) \ if(SELECTED_BITMAP(RTTL1_ENABLE_L1S_TASK_ENABLE)) \ { \ - T_RTT_PTR *ptr; \ - T_RTTL1_L1S_TASK_ENABLE *ptr2; \ + T_RTT_PTR ptr; \ \ - ptr = (T_RTT_PTR *) &ptr2; \ - if ((*ptr = trace_info.l1s_rtt_func.rtt_get_fill_ptr(trace_info.l1s_trace_user_id, sizeof(T_RTTL1_L1S_TASK_ENABLE))) != NULL) \ + if ((ptr = trace_info.l1s_rtt_func.rtt_get_fill_ptr(trace_info.l1s_trace_user_id, sizeof(T_RTTL1_L1S_TASK_ENABLE))) != NULL) \ { \ - ptr2->bitmap1 = param1; \ - ptr2->bitmap2 = param2; \ - ptr2->cell_id = RTTL1_ENABLE_L1S_TASK_ENABLE; \ + ((T_RTTL1_L1S_TASK_ENABLE *)ptr)->bitmap1 = param1; \ + ((T_RTTL1_L1S_TASK_ENABLE *)ptr)->bitmap2 = param2; \ + ((T_RTTL1_L1S_TASK_ENABLE *)ptr)->cell_id = RTTL1_ENABLE_L1S_TASK_ENABLE; \ } \ } @@ -302,14 +274,12 @@ #define RTTL1_FILL_MFTAB(param1) \ if(SELECTED_BITMAP(RTTL1_ENABLE_MFTAB)) \ { \ - T_RTT_PTR *ptr; \ - T_RTTL1_MFTAB *ptr2; \ + T_RTT_PTR ptr; \ \ - ptr = (T_RTT_PTR *) &ptr2; \ - if ((*ptr = trace_info.l1s_rtt_func.rtt_get_fill_ptr(trace_info.l1s_trace_user_id, sizeof(T_RTTL1_MFTAB))) != NULL) \ + if ((ptr = trace_info.l1s_rtt_func.rtt_get_fill_ptr(trace_info.l1s_trace_user_id, sizeof(T_RTTL1_MFTAB))) != NULL) \ { \ - ptr2->func = param1; \ - ptr2->cell_id = RTTL1_ENABLE_MFTAB; \ + ((T_RTTL1_MFTAB *)ptr)->func = param1; \ + ((T_RTTL1_MFTAB *)ptr)->cell_id = RTTL1_ENABLE_MFTAB; \ } \ }
--- a/L1/include/l1_signa.h Thu Jun 09 00:19:28 2016 +0000 +++ b/L1/include/l1_signa.h Thu Jun 09 00:45:00 2016 +0000 @@ -1,102 +1,91 @@ /************* Revision Controle System Header ************* - * GSM Layer 1 software + * GSM Layer 1 software * L1_SIGNA.H * * Filename l1_signa.h - * Copyright 2003 (C) Texas Instruments + * Copyright 2003 (C) Texas Instruments * ************* Revision Controle System Header *************/ #define P_L1C 0 #define P_DLL ( P_L1C + 1 ) -#if ((REL99 == 1) && (FF_BHO == 1)) - #define P_MSB P_L1C - #define P_SHIFT1 8 - #define P_SHIFT2 0 - #define P_MPHC_UL 0 - #define P_MPHC_DL 0 -#endif - // Messages Test/PWRMNGT <-> L1A -/* Message used for software dynamic configuration */ -#define TST_SW_CONFIG_REQ ( ( P_L1C << 8 ) | 117) - #if (OP_L1_STANDALONE == 1) /* Message used for hardware dynamic configuration */ #define TST_HW_CONFIG_REQ ( ( P_L1C << 8 ) | 116) #endif -#define TST_TEST_HW_REQ ( ( P_L1C << 8 ) | 1 ) // build: trigger +#define TST_TEST_HW_REQ ( ( P_L1C << 8 ) | 1 ) #define TST_TEST_HW_CON ( ( P_L1C << 8 ) | 2 ) -#define TST_TIMESTAMP_MSG ( ( P_L1C << 8 ) | 3 ) // build: trigger -#define TST_SLEEP_REQ ( ( P_L1C << 8 ) | 4 ) // build: T_TST_SLEEP_REQ +#define TST_TIMESTAMP_MSG ( ( P_L1C << 8 ) | 3 ) +#define TST_SLEEP_REQ ( ( P_L1C << 8 ) | 4 ) // Messages L3 <-> L1A -#define MPHC_RXLEV_REQ ( ( P_L1C << 8 ) | 11 ) // build: T_FULL_LIST_MEAS +#define MPHC_RXLEV_REQ ( ( P_L1C << 8 ) | 11 ) #define MPHC_RXLEV_IND ( ( P_L1C << 8 ) | 12 ) -#define MPHC_STOP_RXLEV_REQ ( ( P_L1C << 8 ) | 13 ) // build: trigger +#define MPHC_STOP_RXLEV_REQ ( ( P_L1C << 8 ) | 13 ) #define MPHC_STOP_RXLEV_CON ( ( P_L1C << 8 ) | 14 ) -#define MPHC_NETWORK_SYNC_REQ ( ( P_L1C << 8 ) | 15 ) // build: T_MPHC_NETWORK_SYNC_REQ +#define MPHC_NETWORK_SYNC_REQ ( ( P_L1C << 8 ) | 15 ) #define MPHC_NETWORK_SYNC_IND ( ( P_L1C << 8 ) | 16 ) -#define MPHC_STOP_NETWORK_SYNC_REQ ( ( P_L1C << 8 ) | 17 ) // build: trigger +#define MPHC_STOP_NETWORK_SYNC_REQ ( ( P_L1C << 8 ) | 17 ) #define MPHC_STOP_NETWORK_SYNC_CON ( ( P_L1C << 8 ) | 18 ) -#define MPHC_NEW_SCELL_REQ ( ( P_L1C << 8 ) | 19 ) // build: T_MPHC_NEW_SCELL_REQ +#define MPHC_NEW_SCELL_REQ ( ( P_L1C << 8 ) | 19 ) #define MPHC_NEW_SCELL_CON ( ( P_L1C << 8 ) | 20 ) -#define MPHC_START_CCCH_REQ ( ( P_L1C << 8 ) | 21 ) // build: T_MPHC_START_CCCH_REQ -#define MPHC_STOP_CCCH_REQ ( ( P_L1C << 8 ) | 22 ) // build: trigger +#define MPHC_START_CCCH_REQ ( ( P_L1C << 8 ) | 21 ) +#define MPHC_STOP_CCCH_REQ ( ( P_L1C << 8 ) | 22 ) #define MPHC_STOP_CCCH_CON ( ( P_L1C << 8 ) | 23 ) -#define MPHC_SCELL_NBCCH_REQ ( ( P_L1C << 8 ) | 24 ) // build: T_MPHC_SCELL_NBCCH_REQ -#define MPHC_SCELL_EBCCH_REQ ( ( P_L1C << 8 ) | 25 ) // build: T_MPHC_SCELL_EBCCH_REQ -#define MPHC_STOP_SCELL_BCCH_REQ ( ( P_L1C << 8 ) | 26 ) // build: trigger +#define MPHC_SCELL_NBCCH_REQ ( ( P_L1C << 8 ) | 24 ) +#define MPHC_SCELL_EBCCH_REQ ( ( P_L1C << 8 ) | 25 ) +#define MPHC_STOP_SCELL_BCCH_REQ ( ( P_L1C << 8 ) | 26 ) #define MPHC_STOP_SCELL_BCCH_CON ( ( P_L1C << 8 ) | 27 ) -#define MPHC_NCELL_BCCH_REQ ( ( P_L1C << 8 ) | 28 ) // build: T_MPHC_NCELL_BCCH_REQ +#define MPHC_NCELL_BCCH_REQ ( ( P_L1C << 8 ) | 28 ) #define MPHC_NCELL_BCCH_IND ( ( P_L1C << 8 ) | 29 ) -#define MPHC_STOP_NCELL_BCCH_REQ ( ( P_L1C << 8 ) | 30 ) // build: T_MPHC_STOP_NCELL_BCCH_REQ +#define MPHC_STOP_NCELL_BCCH_REQ ( ( P_L1C << 8 ) | 30 ) #define MPHC_STOP_NCELL_BCCH_CON ( ( P_L1C << 8 ) | 31 ) -#define MPHC_NCELL_SYNC_REQ ( ( P_L1C << 8 ) | 32 ) // build: T_MPHC_NCELL_SYNC_REQ +#define MPHC_NCELL_SYNC_REQ ( ( P_L1C << 8 ) | 32 ) #define MPHC_NCELL_SYNC_IND ( ( P_L1C << 8 ) | 33 ) -#define MPHC_STOP_NCELL_SYNC_REQ ( ( P_L1C << 8 ) | 34 ) // build: T_MPHC_STOP_NCELL_SYNC_REQ +#define MPHC_STOP_NCELL_SYNC_REQ ( ( P_L1C << 8 ) | 34 ) #define MPHC_STOP_NCELL_SYNC_CON ( ( P_L1C << 8 ) | 35 ) -#define MPHC_RXLEV_PERIODIC_REQ ( ( P_L1C << 8 ) | 36 ) // build: T_MPHC_RXLEV_PERIODIC_REQ +#define MPHC_RXLEV_PERIODIC_REQ ( ( P_L1C << 8 ) | 36 ) #define MPHC_RXLEV_PERIODIC_IND ( ( P_L1C << 8 ) | 37 ) -#define MPHC_STOP_RXLEV_PERIODIC_REQ ( ( P_L1C << 8 ) | 38 ) // build: trigger +#define MPHC_STOP_RXLEV_PERIODIC_REQ ( ( P_L1C << 8 ) | 38 ) #define MPHC_STOP_RXLEV_PERIODIC_CON ( ( P_L1C << 8 ) | 39 ) -#define MPHC_CONFIG_CBCH_REQ ( ( P_L1C << 8 ) | 40 ) // build: T_MPHC_CONFIG_CBCH_REQ -#define MPHC_CBCH_SCHEDULE_REQ ( ( P_L1C << 8 ) | 41 ) // build: T_MPHC_CBCH_SCHEDULE_REQ -#define MPHC_CBCH_UPDATE_REQ ( ( P_L1C << 8 ) | 42 ) // build: T_MPHC_CBCH_UPDATE_REQ -#define MPHC_CBCH_INFO_REQ ( ( P_L1C << 8 ) | 43 ) // build: T_MPHC_CBCH_INFO_REQ -#define MPHC_STOP_CBCH_REQ ( ( P_L1C << 8 ) | 44 ) // build: T_MPHC_STOP_CBCH_REQ +#define MPHC_CONFIG_CBCH_REQ ( ( P_L1C << 8 ) | 40 ) +#define MPHC_CBCH_SCHEDULE_REQ ( ( P_L1C << 8 ) | 41 ) +#define MPHC_CBCH_UPDATE_REQ ( ( P_L1C << 8 ) | 42 ) +#define MPHC_CBCH_INFO_REQ ( ( P_L1C << 8 ) | 43 ) +#define MPHC_STOP_CBCH_REQ ( ( P_L1C << 8 ) | 44 ) #define MPHC_STOP_CBCH_CON ( ( P_L1C << 8 ) | 45 ) -#define MPHC_RA_REQ ( ( P_L1C << 8 ) | 46 ) // build: T_MPHC_RA_REQ +#define MPHC_RA_REQ ( ( P_L1C << 8 ) | 46 ) #define MPHC_RA_CON ( ( P_L1C << 8 ) | 47 ) -#define MPHC_STOP_RA_REQ ( ( P_L1C << 8 ) | 48 ) // build: trigger +#define MPHC_STOP_RA_REQ ( ( P_L1C << 8 ) | 48 ) #define MPHC_STOP_RA_CON ( ( P_L1C << 8 ) | 49 ) #define MPHC_DATA_IND ( ( P_L1C << 8 ) | 50 ) -#define MPHC_IMMED_ASSIGN_REQ ( ( P_L1C << 8 ) | 51 ) // build: T_MPHC_IMMED_ASSIGN_REQ -#define MPHC_CHANNEL_ASSIGN_REQ ( ( P_L1C << 8 ) | 52 ) // build: T_MPHC_CHANNEL_ASSIGN_REQ -#define MPHC_ASYNC_HO_REQ ( ( P_L1C << 8 ) | 53 ) // build: T_MPHC_ASYNC_HO_REQ -#define MPHC_SYNC_HO_REQ ( ( P_L1C << 8 ) | 54 ) // build: T_MPHC_SYNC_HO_REQ -#define MPHC_PRE_SYNC_HO_REQ ( ( P_L1C << 8 ) | 55 ) // build: T_MPHC_PRE_SYNC_HO_REQ -#define MPHC_PSEUDO_SYNC_HO_REQ ( ( P_L1C << 8 ) | 56 ) // build: T_MPHC_PSEUDO_SYNC_HO_REQ -#define MPHC_STOP_DEDICATED_REQ ( ( P_L1C << 8 ) | 57 ) // build: trigger -#define MPHC_STOP_DEDICATED_CON ( ( P_L1C << 8 ) | 128 ) // build: trigger +#define MPHC_IMMED_ASSIGN_REQ ( ( P_L1C << 8 ) | 51 ) +#define MPHC_CHANNEL_ASSIGN_REQ ( ( P_L1C << 8 ) | 52 ) +#define MPHC_ASYNC_HO_REQ ( ( P_L1C << 8 ) | 53 ) +#define MPHC_SYNC_HO_REQ ( ( P_L1C << 8 ) | 54 ) +#define MPHC_PRE_SYNC_HO_REQ ( ( P_L1C << 8 ) | 55 ) +#define MPHC_PSEUDO_SYNC_HO_REQ ( ( P_L1C << 8 ) | 56 ) +#define MPHC_STOP_DEDICATED_REQ ( ( P_L1C << 8 ) | 57 ) +#define MPHC_STOP_DEDICATED_CON ( ( P_L1C << 8 ) | 128 ) #define MPHC_CHANGE_FREQUENCY_CON ( ( P_L1C << 8 ) | 58 ) #define MPHC_ASYNC_HO_CON ( ( P_L1C << 8 ) | 59 ) @@ -111,25 +100,24 @@ #define MPHC_HANDOVER_FINISHED ( ( P_L1C << 8 ) | 68 ) -#define MPHC_CHANGE_FREQUENCY ( ( P_L1C << 8 ) | 69 ) // build: T_MPHC_CHANGE_FREQUENCY -#define MPHC_CHANNEL_MODE_MODIFY_REQ ( ( P_L1C << 8 ) | 70 ) // build: T_MPHC_CHANNEL_MODE_MODIFY_REQ -#define MPHC_HANDOVER_FAIL_REQ ( ( P_L1C << 8 ) | 71 ) // build: trigger -#define MPHC_SET_CIPHERING_REQ ( ( P_L1C << 8 ) | 72 ) // build: T_MPHC_SET_CIPHERING_REQ +#define MPHC_CHANGE_FREQUENCY ( ( P_L1C << 8 ) | 69 ) +#define MPHC_CHANNEL_MODE_MODIFY_REQ ( ( P_L1C << 8 ) | 70 ) +#define MPHC_HANDOVER_FAIL_REQ ( ( P_L1C << 8 ) | 71 ) +#define MPHC_SET_CIPHERING_REQ ( ( P_L1C << 8 ) | 72 ) -#define MPHC_MEAS_REPORT ( ( P_L1C << 8 ) | 73 ) // build: T_MPHC_MEAS_REPORT -#define MPHC_UPDATE_BA_LIST ( ( P_L1C << 8 ) | 74 ) // build: T_NEW_BA_LIST +#define MPHC_MEAS_REPORT ( ( P_L1C << 8 ) | 73 ) +#define MPHC_UPDATE_BA_LIST ( ( P_L1C << 8 ) | 74 ) -#define MPHC_NCELL_FB_SB_READ ( ( P_L1C << 8 ) | 75 ) // build: T_MPHC_NCELL_FB_SB_READ -#define MPHC_NCELL_SB_READ ( ( P_L1C << 8 ) | 76 ) // build: T_MPHC_NCELL_SB_READ -#define MPHC_NCELL_BCCH_READ ( ( P_L1C << 8 ) | 77 ) // build: T_MPHC_NCELL_BCCH_READ +#define MPHC_NCELL_FB_SB_READ ( ( P_L1C << 8 ) | 75 ) +#define MPHC_NCELL_SB_READ ( ( P_L1C << 8 ) | 76 ) +#define MPHC_NCELL_BCCH_READ ( ( P_L1C << 8 ) | 77 ) + + // Messages L1S -> L1A #define L1C_VALID_MEAS_INFO ( ( P_L1C << 8 ) | 80 ) #define L1C_FB_INFO ( ( P_L1C << 8 ) | 81 ) #define L1C_SB_INFO ( ( P_L1C << 8 ) | 82 ) -#if ((REL99 == 1) && (FF_BHO == 1)) -#define L1C_FBSB_INFO ( ( ( ( P_MSB << P_SHIFT1 ) | 118 ) << P_SHIFT2 ) | P_MPHC_DL ) -#endif #define L1C_SBCONF_INFO ( ( P_L1C << 8 ) | 83 ) #define L1C_BCCHS_INFO ( ( P_L1C << 8 ) | 84 ) #define L1C_BCCHN_INFO ( ( P_L1C << 8 ) | 85 ) @@ -147,10 +135,10 @@ #define L1C_STOP_DEDICATED_DONE ( ( P_L1C << 8 ) | 129 ) // Messages O&M <-> L1A -#define OML1_CLOSE_TCH_LOOP_REQ ( ( P_L1C << 8 ) | 97 ) // build: T_OML1_CLOSE_TCH_LOOP_REQ -#define OML1_OPEN_TCH_LOOP_REQ ( ( P_L1C << 8 ) | 98 ) // build: trigger -#define OML1_START_DAI_TEST_REQ ( ( P_L1C << 8 ) | 99 ) // build: T_OML1_START_DAI_TEST_REQ -#define OML1_STOP_DAI_TEST_REQ ( ( P_L1C << 8 ) | 100 ) // build: trigger +#define OML1_CLOSE_TCH_LOOP_REQ ( ( P_L1C << 8 ) | 97 ) +#define OML1_OPEN_TCH_LOOP_REQ ( ( P_L1C << 8 ) | 98 ) +#define OML1_START_DAI_TEST_REQ ( ( P_L1C << 8 ) | 99 ) +#define OML1_STOP_DAI_TEST_REQ ( ( P_L1C << 8 ) | 100 ) #define OML1_CLOSE_TCH_LOOP_CON ( ( P_L1C << 8 ) | 101 ) #define OML1_OPEN_TCH_LOOP_CON ( ( P_L1C << 8 ) | 102 ) @@ -163,8 +151,8 @@ // Messages for trace -#define L1_STATS_REQ ( ( P_L1C << 8 ) | 107 ) // build: T_L1_STATS_REQ -#define L1_DUMMY_FOR_SIM ( ( P_L1C << 8 ) | 108 ) // build: trigger +#define L1_STATS_REQ ( ( P_L1C << 8 ) | 107 ) +#define L1_DUMMY_FOR_SIM ( ( P_L1C << 8 ) | 108 ) #define TRACE_DSP_DEBUG ( ( P_L1C << 8 ) | 106 ) #define TRACE_CONFIG ( ( P_L1C << 8 ) | 123 ) @@ -173,24 +161,24 @@ #define QUICK_TRACE ( ( P_L1C << 8 ) | 126 ) #define TRACE_DSP_AMR_DEBUG ( ( P_L1C << 8 ) | 127 ) -#define MPHC_NETWORK_LOST_IND ( ( P_L1C << 8 ) | 110 ) // build: trigger +#define MPHC_NETWORK_LOST_IND ( ( P_L1C << 8 ) | 110 ) // Messages MMI <-> L1A -#define MMI_ADC_REQ ( ( P_L1C << 8 ) | 111 ) // build: T_MMI_ADC_REQ -#define MMI_STOP_ADC_REQ ( ( P_L1C << 8 ) | 112 ) // build: trigger +#define MMI_ADC_REQ ( ( P_L1C << 8 ) | 111 ) +#define MMI_STOP_ADC_REQ ( ( P_L1C << 8 ) | 112 ) #define MMI_STOP_ADC_CON ( ( P_L1C << 8 ) | 113 ) #define L1_TEST_HW_INFO ( ( P_L1C << 8 ) | 119 ) // Multi-band selection E-GSM900/DCS1800/PCS1900/GSM850 - #define MPHC_INIT_L1_REQ ( ( P_L1C << 8 ) | 114 ) // build: T_MPHC_INIT_L1_REQ - #define MPHC_INIT_L1_CON ( ( P_L1C << 8 ) | 115 ) + #define MPHC_INIT_L1_REQ ( ( P_L1C << 8 ) | 114 ) + #define MPHC_INIT_L1_CON ( ( P_L1C << 8 ) | 115 ) -// Message RR -> L1A for Enhanced meas. +// MEssage RR -> L1A for Enhanced meas. #if (L1_12NEIGH ==1) -#define MPHC_NCELL_LIST_SYNC_REQ ( ( P_L1C << 8 ) | 122 ) // build: T_MPHC_NCELL_LIST_SYNC_REQ +#define MPHC_NCELL_LIST_SYNC_REQ ( ( P_L1C << 8 ) | 122 ) #endif // Messages L2 <-> L1A -#define PH_DATA_IND ( ( P_DLL << 8 ) | 109 ) +#define PH_DATA_IND ( ( P_DLL << 8 ) | 109 )
--- a/L1/include/l1_tabs.h Thu Jun 09 00:19:28 2016 +0000 +++ b/L1/include/l1_tabs.h Thu Jun 09 00:45:00 2016 +0000 @@ -11,563 +11,547 @@ * This file contains the miscelaneous ROM tables. ***********************************************************/ -#ifndef L1_TABS_H -#define L1_TABS_H +#ifdef L1_ASYNC_C + /*-----------------------------------------------------------------*/ + /* Idle Tasks info. (Paging position, extended Paging position...) */ + /*-----------------------------------------------------------------*/ + /* REM: */ + /* The "working area" field gives the starting position of an area */ + /* it will be used for neighbour: - FB search, */ + /* - SB reading, */ + /* The value given for each parameter set takes into account the */ + /* size of the "FB search" task and the CBCH task. */ + /*-----------------------------------------------------------------*/ + // NP or EP task size: 1 + 4 + 1 = 6. + // BCCHS task size: 1 + 4 + 1 = 6. + // FB task size: 1 + 12 + 1 = 14. --+-- FB + SB task take 15 TDMA (pipeline overlay). + // SB task size: 1 + 2 + 1 = 4. --+ + // CNF, SB task size: 1 + 2 + 1 = 4. + // BC (Broad. Channel): 1 + 4 + 1 = 6 + + const T_IDLE_TASK_INFO IDLE_INFO_NCOMB[(MAX_AG_BLKS_RES_NCOMB+1) * (MAX_PG_BLOC_INDEX_NCOMB+1)] = + // BS_CCCH_SDCCH_COMB = False, BCCH not combined. + { + // BS_AG_BLKS_RES = 0. + // ------------------- + // Paging, Ext Paging + { CCCH_0, CCCH_2 }, // Paging Block Index = 0. + { CCCH_1, CCCH_3 }, // Paging Block Index = 1. + { CCCH_2, CCCH_4 }, // Paging Block Index = 2. + { CCCH_3, CCCH_5 }, // Paging Block Index = 3. + { CCCH_4, CCCH_6 }, // Paging Block Index = 4. + { CCCH_5, CCCH_7 }, // Paging Block Index = 5. + { CCCH_6, CCCH_8 }, // Paging Block Index = 6. + { CCCH_7, CCCH_0 }, // Paging Block Index = 7. + { CCCH_8, CCCH_1 }, // Paging Block Index = 8. - #ifdef L1_ASYNC_C - /*-----------------------------------------------------------------*/ - /* Idle Tasks info. (Paging position, extended Paging position...) */ - /*-----------------------------------------------------------------*/ - /* REM: */ - /* The "working area" field gives the starting position of an area */ - /* it will be used for neighbour: - FB search, */ - /* - SB reading, */ - /* The value given for each parameter set takes into account the */ - /* size of the "FB search" task and the CBCH task. */ - /*-----------------------------------------------------------------*/ - // NP or EP task size: 1 + 4 + 1 = 6. - // BCCHS task size: 1 + 4 + 1 = 6. - // FB task size: 1 + 12 + 1 = 14. --+-- FB + SB task take 15 TDMA (pipeline overlay). - // SB task size: 1 + 2 + 1 = 4. --+ - // CNF, SB task size: 1 + 2 + 1 = 4. - // BC (Broad. Channel): 1 + 4 + 1 = 6 - - const T_IDLE_TASK_INFO IDLE_INFO_NCOMB[(MAX_AG_BLKS_RES_NCOMB+1) * (MAX_PG_BLOC_INDEX_NCOMB+1)] = - // BS_CCCH_SDCCH_COMB = False, BCCH not combined. - { - // BS_AG_BLKS_RES = 0. - // ------------------- - // Paging, Ext Paging - { CCCH_0, CCCH_2 }, // Paging Block Index = 0. - { CCCH_1, CCCH_3 }, // Paging Block Index = 1. - { CCCH_2, CCCH_4 }, // Paging Block Index = 2. - { CCCH_3, CCCH_5 }, // Paging Block Index = 3. - { CCCH_4, CCCH_6 }, // Paging Block Index = 4. - { CCCH_5, CCCH_7 }, // Paging Block Index = 5. - { CCCH_6, CCCH_8 }, // Paging Block Index = 6. - { CCCH_7, CCCH_0 }, // Paging Block Index = 7. - { CCCH_8, CCCH_1 }, // Paging Block Index = 8. - - // BS_AG_BLKS_RES = 1. - // ------------------- - // Paging, Ext Paging - { CCCH_1, CCCH_3 }, // Paging Block Index = 0. - { CCCH_2, CCCH_4 }, // Paging Block Index = 1. - { CCCH_3, CCCH_5 }, // Paging Block Index = 2. - { CCCH_4, CCCH_6 }, // Paging Block Index = 3. - { CCCH_5, CCCH_7 }, // Paging Block Index = 4. - { CCCH_6, CCCH_8 }, // Paging Block Index = 5. - { CCCH_7, CCCH_1 }, // Paging Block Index = 6. - { CCCH_8, CCCH_2 }, // Paging Block Index = 7. - { NULL, NULL }, // Paging Block Index = 8. + // BS_AG_BLKS_RES = 1. + // ------------------- + // Paging, Ext Paging + { CCCH_1, CCCH_3 }, // Paging Block Index = 0. + { CCCH_2, CCCH_4 }, // Paging Block Index = 1. + { CCCH_3, CCCH_5 }, // Paging Block Index = 2. + { CCCH_4, CCCH_6 }, // Paging Block Index = 3. + { CCCH_5, CCCH_7 }, // Paging Block Index = 4. + { CCCH_6, CCCH_8 }, // Paging Block Index = 5. + { CCCH_7, CCCH_1 }, // Paging Block Index = 6. + { CCCH_8, CCCH_2 }, // Paging Block Index = 7. + { NULL, NULL }, // Paging Block Index = 8. - // BS_AG_BLKS_RES = 2. - // ------------------- - // Paging, Ext Paging - { CCCH_2, CCCH_4 }, // Paging Block Index = 0. - { CCCH_3, CCCH_5 }, // Paging Block Index = 1. - { CCCH_4, CCCH_6 }, // Paging Block Index = 2. - { CCCH_5, CCCH_7 }, // Paging Block Index = 3. - { CCCH_6, CCCH_8 }, // Paging Block Index = 4. - { CCCH_7, CCCH_2 }, // Paging Block Index = 5. - { CCCH_8, CCCH_3 }, // Paging Block Index = 6. - { NULL, NULL }, // Paging Block Index = 7. - { NULL, NULL }, // Paging Block Index = 8. + // BS_AG_BLKS_RES = 2. + // ------------------- + // Paging, Ext Paging + { CCCH_2, CCCH_4 }, // Paging Block Index = 0. + { CCCH_3, CCCH_5 }, // Paging Block Index = 1. + { CCCH_4, CCCH_6 }, // Paging Block Index = 2. + { CCCH_5, CCCH_7 }, // Paging Block Index = 3. + { CCCH_6, CCCH_8 }, // Paging Block Index = 4. + { CCCH_7, CCCH_2 }, // Paging Block Index = 5. + { CCCH_8, CCCH_3 }, // Paging Block Index = 6. + { NULL, NULL }, // Paging Block Index = 7. + { NULL, NULL }, // Paging Block Index = 8. - // BS_AG_BLKS_RES = 3. - // ------------------- - // Paging, Ext Paging, - { CCCH_3, CCCH_5 }, // Paging Block Index = 0. - { CCCH_4, CCCH_6 }, // Paging Block Index = 1. - { CCCH_5, CCCH_7 }, // Paging Block Index = 2. - { CCCH_6, CCCH_8 }, // Paging Block Index = 3. - { CCCH_7, CCCH_3 }, // Paging Block Index = 4. - { CCCH_8, CCCH_4 }, // Paging Block Index = 5. - { NULL, NULL }, // Paging Block Index = 6. - { NULL, NULL }, // Paging Block Index = 7. - { NULL, NULL }, // Paging Block Index = 8. + // BS_AG_BLKS_RES = 3. + // ------------------- + // Paging, Ext Paging, + { CCCH_3, CCCH_5 }, // Paging Block Index = 0. + { CCCH_4, CCCH_6 }, // Paging Block Index = 1. + { CCCH_5, CCCH_7 }, // Paging Block Index = 2. + { CCCH_6, CCCH_8 }, // Paging Block Index = 3. + { CCCH_7, CCCH_3 }, // Paging Block Index = 4. + { CCCH_8, CCCH_4 }, // Paging Block Index = 5. + { NULL, NULL }, // Paging Block Index = 6. + { NULL, NULL }, // Paging Block Index = 7. + { NULL, NULL }, // Paging Block Index = 8. - // BS_AG_BLKS_RES = 4. - // ------------------- - // Paging, Ext Paging - { CCCH_4, CCCH_6 }, // Paging Block Index = 0. - { CCCH_5, CCCH_7 }, // Paging Block Index = 1. - { CCCH_6, CCCH_8 }, // Paging Block Index = 2. - { CCCH_7, CCCH_4 }, // Paging Block Index = 3. - { CCCH_8, CCCH_5 }, // Paging Block Index = 4. - { NULL, NULL }, // Paging Block Index = 5. - { NULL, NULL }, // Paging Block Index = 6. - { NULL, NULL }, // Paging Block Index = 7. - { NULL, NULL }, // Paging Block Index = 8. + // BS_AG_BLKS_RES = 4. + // ------------------- + // Paging, Ext Paging + { CCCH_4, CCCH_6 }, // Paging Block Index = 0. + { CCCH_5, CCCH_7 }, // Paging Block Index = 1. + { CCCH_6, CCCH_8 }, // Paging Block Index = 2. + { CCCH_7, CCCH_4 }, // Paging Block Index = 3. + { CCCH_8, CCCH_5 }, // Paging Block Index = 4. + { NULL, NULL }, // Paging Block Index = 5. + { NULL, NULL }, // Paging Block Index = 6. + { NULL, NULL }, // Paging Block Index = 7. + { NULL, NULL }, // Paging Block Index = 8. - // BS_AG_BLKS_RES = 5. - // ------------------- - // Paging, Ext Paging - { CCCH_5, CCCH_7 }, // Paging Block Index = 0. - { CCCH_6, CCCH_8 }, // Paging Block Index = 1. - { CCCH_7, CCCH_5 }, // Paging Block Index = 2. - { CCCH_8, CCCH_6 }, // Paging Block Index = 3. - { NULL, NULL }, // Paging Block Index = 4. - { NULL, NULL }, // Paging Block Index = 5. - { NULL, NULL }, // Paging Block Index = 6. - { NULL, NULL }, // Paging Block Index = 7. - { NULL, NULL }, // Paging Block Index = 8. + // BS_AG_BLKS_RES = 5. + // ------------------- + // Paging, Ext Paging + { CCCH_5, CCCH_7 }, // Paging Block Index = 0. + { CCCH_6, CCCH_8 }, // Paging Block Index = 1. + { CCCH_7, CCCH_5 }, // Paging Block Index = 2. + { CCCH_8, CCCH_6 }, // Paging Block Index = 3. + { NULL, NULL }, // Paging Block Index = 4. + { NULL, NULL }, // Paging Block Index = 5. + { NULL, NULL }, // Paging Block Index = 6. + { NULL, NULL }, // Paging Block Index = 7. + { NULL, NULL }, // Paging Block Index = 8. - // BS_AG_BLKS_RES = 6. - // ------------------- - // Paging, Ext Paging, - { CCCH_6, CCCH_8 }, // Paging Block Index = 0. - { CCCH_7, CCCH_6 }, // Paging Block Index = 1. - { CCCH_8, CCCH_7 }, // Paging Block Index = 2. - { NULL, NULL }, // Paging Block Index = 3. - { NULL, NULL }, // Paging Block Index = 4. - { NULL, NULL }, // Paging Block Index = 5. - { NULL, NULL }, // Paging Block Index = 6. - { NULL, NULL }, // Paging Block Index = 7. - { NULL, NULL }, // Paging Block Index = 8. + // BS_AG_BLKS_RES = 6. + // ------------------- + // Paging, Ext Paging, + { CCCH_6, CCCH_8 }, // Paging Block Index = 0. + { CCCH_7, CCCH_6 }, // Paging Block Index = 1. + { CCCH_8, CCCH_7 }, // Paging Block Index = 2. + { NULL, NULL }, // Paging Block Index = 3. + { NULL, NULL }, // Paging Block Index = 4. + { NULL, NULL }, // Paging Block Index = 5. + { NULL, NULL }, // Paging Block Index = 6. + { NULL, NULL }, // Paging Block Index = 7. + { NULL, NULL }, // Paging Block Index = 8. - // BS_AG_BLKS_RES = 7. - // ------------------- - // Paging, Ext Paging - { CCCH_7, CCCH_7 }, // Paging Block Index = 0. - { CCCH_8, CCCH_8 }, // Paging Block Index = 1. - { NULL, NULL }, // Paging Block Index = 2. - { NULL, NULL }, // Paging Block Index = 3. - { NULL, NULL }, // Paging Block Index = 4. - { NULL, NULL }, // Paging Block Index = 5. - { NULL, NULL }, // Paging Block Index = 6. - { NULL, NULL }, // Paging Block Index = 7. - { NULL, NULL } // Paging Block Index = 8. - }; + // BS_AG_BLKS_RES = 7. + // ------------------- + // Paging, Ext Paging + { CCCH_7, CCCH_7 }, // Paging Block Index = 0. + { CCCH_8, CCCH_8 }, // Paging Block Index = 1. + { NULL, NULL }, // Paging Block Index = 2. + { NULL, NULL }, // Paging Block Index = 3. + { NULL, NULL }, // Paging Block Index = 4. + { NULL, NULL }, // Paging Block Index = 5. + { NULL, NULL }, // Paging Block Index = 6. + { NULL, NULL }, // Paging Block Index = 7. + { NULL, NULL } // Paging Block Index = 8. + }; - const T_IDLE_TASK_INFO IDLE_INFO_COMB[(MAX_AG_BLKS_RES_COMB+1) * (MAX_PG_BLOC_INDEX_COMB+1)] = - // BS_CCCH_SDCCH_COMB = TRUE, BCCH combined. - { - // BS_AG_BLKS_RES = 0. - // ------------------- - // Paging, Ext Paging, offset, working_area - { CCCH_0, CCCH_2 }, // Paging Block Index = 0. - { CCCH_1, CCCH_0 }, // Paging Block Index = 1. - { CCCH_2, CCCH_1 }, // Paging Block Index = 2. + const T_IDLE_TASK_INFO IDLE_INFO_COMB[(MAX_AG_BLKS_RES_COMB+1) * (MAX_PG_BLOC_INDEX_COMB+1)] = + // BS_CCCH_SDCCH_COMB = TRUE, BCCH combined. + { + // BS_AG_BLKS_RES = 0. + // ------------------- + // Paging, Ext Paging, offset, working_area + { CCCH_0, CCCH_2 }, // Paging Block Index = 0. + { CCCH_1, CCCH_0 }, // Paging Block Index = 1. + { CCCH_2, CCCH_1 }, // Paging Block Index = 2. - // BS_AG_BLKS_RES = 1. - // ------------------- - // Paging, Ext Paging, offset, working_area - { CCCH_1, CCCH_1 }, // Paging Block Index = 0. - { CCCH_2, CCCH_2 }, // Paging Block Index = 1. - { NULL, NULL }, // Paging Block Index = 2. + // BS_AG_BLKS_RES = 1. + // ------------------- + // Paging, Ext Paging, offset, working_area + { CCCH_1, CCCH_1 }, // Paging Block Index = 0. + { CCCH_2, CCCH_2 }, // Paging Block Index = 1. + { NULL, NULL }, // Paging Block Index = 2. - // BS_AG_BLKS_RES = 2. - // ------------------- - // Paging, Ext Paging, offset, working_area - { CCCH_2, CCCH_2 }, // Paging Block Index = 0. - { NULL, NULL }, // Paging Block Index = 1. - { NULL, NULL } // Paging Block Index = 2. - }; + // BS_AG_BLKS_RES = 2. + // ------------------- + // Paging, Ext Paging, offset, working_area + { CCCH_2, CCCH_2 }, // Paging Block Index = 0. + { NULL, NULL }, // Paging Block Index = 1. + { NULL, NULL } // Paging Block Index = 2. + }; - - /*-------------------------------------*/ - /* Table giving the number of Paging */ - /* blocks in a MF51. */ - /* (called "N div BS_PA_MFRMS" in */ - /* GSM05.02, Page 21). */ - /*-------------------------------------*/ + + /*-------------------------------------*/ + /* Table giving the number of Paging */ + /* blocks in a MF51. */ + /* (called "N div BS_PA_MFRMS" in */ + /* GSM05.02, Page 21). */ + /*-------------------------------------*/ - // BS_CCCH_SDCCH_COMB = False, BCCH not combined. - const UWORD8 NBPCH_IN_MF51_NCOMB[(MAX_AG_BLKS_RES_NCOMB+1)] = - { - 9, // BS_AG_BLKS_RES = 0. - 8, // BS_AG_BLKS_RES = 1. - 7, // BS_AG_BLKS_RES = 2. - 6, // BS_AG_BLKS_RES = 3. - 5, // BS_AG_BLKS_RES = 4. - 4, // BS_AG_BLKS_RES = 5. - 3, // BS_AG_BLKS_RES = 6. - 2 // BS_AG_BLKS_RES = 7. - }; + // BS_CCCH_SDCCH_COMB = False, BCCH not combined. + const UWORD8 NBPCH_IN_MF51_NCOMB[(MAX_AG_BLKS_RES_NCOMB+1)] = + { + 9, // BS_AG_BLKS_RES = 0. + 8, // BS_AG_BLKS_RES = 1. + 7, // BS_AG_BLKS_RES = 2. + 6, // BS_AG_BLKS_RES = 3. + 5, // BS_AG_BLKS_RES = 4. + 4, // BS_AG_BLKS_RES = 5. + 3, // BS_AG_BLKS_RES = 6. + 2 // BS_AG_BLKS_RES = 7. + }; - // BS_CCCH_SDCCH_COMB = True, BCCH combined. - const UWORD8 NBPCH_IN_MF51_COMB[(MAX_AG_BLKS_RES_COMB+1)] = - { - 3, // BS_AG_BLKS_RES = 0. - 2, // BS_AG_BLKS_RES = 1. - 1 // BS_AG_BLKS_RES = 2. - }; + // BS_CCCH_SDCCH_COMB = True, BCCH combined. + const UWORD8 NBPCH_IN_MF51_COMB[(MAX_AG_BLKS_RES_COMB+1)] = + { + 3, // BS_AG_BLKS_RES = 0. + 2, // BS_AG_BLKS_RES = 1. + 1 // BS_AG_BLKS_RES = 2. + }; - // Initial value for Downlink Signalling failure Counter (DSC). - const UWORD8 DSC_INIT_VALUE[MAX_BS_PA_MFRMS-1] = - { - 45, // BS_PA_MFRMS = 2. - 30, // BS_PA_MFRMS = 3. - 23, // BS_PA_MFRMS = 4. - 18, // BS_PA_MFRMS = 5. - 15, // BS_PA_MFRMS = 6. - 13, // BS_PA_MFRMS = 7. - 11, // BS_PA_MFRMS = 8. - 10 // BS_PA_MFRMS = 9. - }; + // Initial value for Downlink Signalling failure Counter (DSC). + const UWORD8 DSC_INIT_VALUE[MAX_BS_PA_MFRMS-1] = + { + 45, // BS_PA_MFRMS = 2. + 30, // BS_PA_MFRMS = 3. + 23, // BS_PA_MFRMS = 4. + 18, // BS_PA_MFRMS = 5. + 15, // BS_PA_MFRMS = 6. + 13, // BS_PA_MFRMS = 7. + 11, // BS_PA_MFRMS = 8. + 10 // BS_PA_MFRMS = 9. + }; - // REM: 2nd block of SDCCH is always at the same position as the first block - // but 1 mf51 later. - // REM: monitoring during SDCCH used a fixe area (FB51/SB51/SBCNF51 tasks). - // Here is given the area starting position. This position is chosen - // to allow the equations for SBCNF51 occurence as it is in the l1s - // scheduler (the area do not overlap the end of 102 multiframe - // structure). - // Table for SDCCH description, Down Link & Up link, Not combined case. - const T_SDCCH_DESC SDCCH_DESC_NCOMB[8] = - { - // "dl_D" , "dl_A" , "ul_D" , "ul_A". , "monit. area" - { 51 - 12 , 32 - 12 , 15 - 12 , 47 - 12 , 70 - 12 }, // SDCCH, D0 - { 55 - 12 , 36 - 12 , 19 - 12 , 51 - 12 , 74 - 12 }, // SDCCH, D1 - { 59 - 12 , 40 - 12 , 23 - 12 , 55 - 12 , 78 - 12 }, // SDCCH, D2 - { 12 - 12 , 44 - 12 , 27 - 12 , 59 - 12 , 82 - 12 }, // SDCCH, D3 - { 16 - 12 , 83 - 12 , 31 - 12 , 98 - 12 , 35 - 12 }, // SDCCH, D4 - { 20 - 12 , 87 - 12 , 35 - 12 , 102 - 12 , 39 - 12 }, // SDCCH, D5 - { 24 - 12 , 91 - 12 , 39 - 12 , 4 - 12 + 102 , 43 - 12 }, // SDCCH, D6 - { 28 - 12 , 95 - 12 , 43 - 12 , 8 - 12 + 102 , 47 - 12 } // SDCCH, D7 - }; + // REM: 2nd block of SDCCH is always at the same position as the first block + // but 1 mf51 later. + // REM: monitoring during SDCCH used a fixe area (FB51/SB51/SBCNF51 tasks). + // Here is given the area starting position. This position is chosen + // to allow the equations for SBCNF51 occurence as it is in the l1s + // scheduler (the area do not overlap the end of 102 multiframe + // structure). + // Table for SDCCH description, Down Link & Up link, Not combined case. + const T_SDCCH_DESC SDCCH_DESC_NCOMB[8] = + { + // "dl_D" , "dl_A" , "ul_D" , "ul_A". , "monit. area" + { 51 - 12 , 32 - 12 , 15 - 12 , 47 - 12 , 70 - 12 }, // SDCCH, D0 + { 55 - 12 , 36 - 12 , 19 - 12 , 51 - 12 , 74 - 12 }, // SDCCH, D1 + { 59 - 12 , 40 - 12 , 23 - 12 , 55 - 12 , 78 - 12 }, // SDCCH, D2 + { 12 - 12 , 44 - 12 , 27 - 12 , 59 - 12 , 82 - 12 }, // SDCCH, D3 + { 16 - 12 , 83 - 12 , 31 - 12 , 98 - 12 , 35 - 12 }, // SDCCH, D4 + { 20 - 12 , 87 - 12 , 35 - 12 , 102 - 12 , 39 - 12 }, // SDCCH, D5 + { 24 - 12 , 91 - 12 , 39 - 12 , 4 - 12 + 102 , 43 - 12 }, // SDCCH, D6 + { 28 - 12 , 95 - 12 , 43 - 12 , 8 - 12 + 102 , 47 - 12 } // SDCCH, D7 + }; - // REM: monitoring during SDCCH used a fixe area (FB51/SB51/SBCNF51 tasks). - // Here is given the area starting position. This position is chosen - // to allow the equations for SBCNF51 occurence as it is in the l1s - // scheduler (the area do not overlap the end of 102 multiframe - // structure). - // Table for SDCCH description, Down Link & Up link, Combined case. - const T_SDCCH_DESC SDCCH_DESC_COMB[4] = - { - // "dl_D" , "dl_A" , "ul_D" , "ul_A". , "monit. area" - { 73 - 37 , 42 - 37 , 37 - 37 , 57 - 37 , 92 - 37 }, // SDCCH, D0 - { 77 - 37 , 46 - 37 , 41 - 37 , 61 - 37 , 96 - 37 }, // SDCCH, D1 - { 83 - 37 , 93 - 37 , 47 - 37 , 6 - 37 + 102 , 51 - 37 }, // SDCCH, D2 - { 87 - 37 , 97 - 37 , 51 - 37 , 10 - 37 + 102 , 55 - 37 } // SDCCH, D3 - }; + // REM: monitoring during SDCCH used a fixe area (FB51/SB51/SBCNF51 tasks). + // Here is given the area starting position. This position is chosen + // to allow the equations for SBCNF51 occurence as it is in the l1s + // scheduler (the area do not overlap the end of 102 multiframe + // structure). + // Table for SDCCH description, Down Link & Up link, Combined case. + const T_SDCCH_DESC SDCCH_DESC_COMB[4] = + { + // "dl_D" , "dl_A" , "ul_D" , "ul_A". , "monit. area" + { 73 - 37 , 42 - 37 , 37 - 37 , 57 - 37 , 92 - 37 }, // SDCCH, D0 + { 77 - 37 , 46 - 37 , 41 - 37 , 61 - 37 , 96 - 37 }, // SDCCH, D1 + { 83 - 37 , 93 - 37 , 47 - 37 , 6 - 37 + 102 , 51 - 37 }, // SDCCH, D2 + { 87 - 37 , 97 - 37 , 51 - 37 , 10 - 37 + 102 , 55 - 37 } // SDCCH, D3 + }; - // Table for HOPPING SEQUENCE GENERATION ALGORITHM. - const UWORD8 RNTABLE[114] = - { - 48, 98, 63, 1, 36, 95, 78, 102, 94, 73, - 0, 64, 25, 81, 76, 59, 124, 23, 104, 100, - 101, 47, 118, 85, 18, 56, 96, 86, 54, 2, - 80, 34, 127, 13, 6, 89, 57, 103, 12, 74, - 55, 111, 75, 38, 109, 71, 112, 29, 11, 88, - 87, 19, 3, 68, 110, 26, 33, 31, 8, 45, - 82, 58, 40, 107, 32, 5, 106, 92, 62, 67, - 77, 108, 122, 37, 60, 66, 121, 42, 51, 126, - 117, 114, 4, 90, 43, 52, 53, 113, 120, 72, - 16, 49, 7, 79, 119, 61, 22, 84, 9, 97, - 91, 15, 21, 24, 46, 39, 93, 105, 65, 70, - 125, 99, 17, 123 - }; + // Table for HOPPING SEQUENCE GENERATION ALGORITHM. + const UWORD8 RNTABLE[114] = + { + 48, 98, 63, 1, 36, 95, 78, 102, 94, 73, + 0, 64, 25, 81, 76, 59, 124, 23, 104, 100, + 101, 47, 118, 85, 18, 56, 96, 86, 54, 2, + 80, 34, 127, 13, 6, 89, 57, 103, 12, 74, + 55, 111, 75, 38, 109, 71, 112, 29, 11, 88, + 87, 19, 3, 68, 110, 26, 33, 31, 8, 45, + 82, 58, 40, 107, 32, 5, 106, 92, 62, 67, + 77, 108, 122, 37, 60, 66, 121, 42, 51, 126, + 117, 114, 4, 90, 43, 52, 53, 113, 120, 72, + 16, 49, 7, 79, 119, 61, 22, 84, 9, 97, + 91, 15, 21, 24, 46, 39, 93, 105, 65, 70, + 125, 99, 17, 123 + }; - // Table giving the RACH slot positions when COMBINED. - // Rem: all is shifted left by 1 to map the position of the possible "contoles". - const UWORD8 COMBINED_RA_DISTRIB[51] = - { - 0, 0, 0, - 1, 1, - 0, 0, 0, 0, 0, 0, 0, 0, - 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, - 0, 0, 0, 0, 0, 0, 0, 0, - 1, 1, - 0, 0, 0, 0, 0 + // Table giving the RACH slot positions when COMBINED. + // Rem: all is shifted left by 1 to map the position of the possible "contoles". + const UWORD8 COMBINED_RA_DISTRIB[51] = + { + 0, 0, 0, + 1, 1, + 0, 0, 0, 0, 0, 0, 0, 0, + 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, + 0, 0, 0, 0, 0, 0, 0, 0, + 1, 1, + 0, 0, 0, 0, 0 + }; + +#if !L1_GPRS + const T_TASK_MFTAB TASK_ROM_MFTAB[NBR_DL_L1S_TASKS] = + { + { BLOC_HWTEST, BLOC_HWTEST_SIZE }, // HWTEST + { BLOC_ADC , BLOC_ADC_SIZE }, // ADC in CS_MODE0 + { NULL, 0 }, // DEDIC (not meaningfull) + { BLOC_RAACC, BLOC_RAACC_SIZE }, // RAACC + { NULL, 0 }, // RAHO (not meaningfull) + { NULL, 0 }, // NSYNC (not meaningfull) + { BLOC_FBNEW, BLOC_FBNEW_SIZE }, // FBNEW + { BLOC_SBCONF, BLOC_SBCONF_SIZE }, // SBCONF + { BLOC_SB2, BLOC_SB2_SIZE }, // SB2 + { BLOC_FB26, BLOC_FB26_SIZE }, // FB26 + { BLOC_SB26, BLOC_SB26_SIZE }, // SB26 + { BLOC_SBCNF26, BLOC_SBCNF26_SIZE }, // SBCNF26 + { BLOC_FB51, BLOC_FB51_SIZE }, // FB51 + { BLOC_SB51, BLOC_SB51_SIZE }, // SB51 + { BLOC_SBCNF51, BLOC_SBCNF51_SIZE }, // SBCNF51 + { BLOC_BCCHN, BLOC_BCCHN_SIZE }, // BCCHN + { BLOC_ALLC, S_RECT4_SIZE }, // ALLC + { BLOC_EBCCHS, S_RECT4_SIZE }, // EBCCHS + { BLOC_NBCCHS, S_RECT4_SIZE }, // NBCCHS + { BLOC_SMSCB, BLOC_SMSCB_SIZE }, // SMSCB + { BLOC_NP, S_RECT4_SIZE }, // NP + { BLOC_EP, S_RECT4_SIZE }, // EP + { BLOC_ADL, S_RECT4_SIZE }, // ADL + { BLOC_AUL, S_RECT4_SIZE }, // AUL + { BLOC_DDL, S_RECT4_SIZE }, // DDL + { BLOC_DUL, S_RECT4_SIZE }, // DUL + { BLOC_TCHD, BLOC_TCHT_SIZE }, // TCHD + { BLOC_TCHA, BLOC_TCHA_SIZE }, // TCHA + { BLOC_TCHTF, BLOC_TCHT_SIZE }, // TCHTF + { BLOC_TCHTH, BLOC_TCHT_SIZE }, // TCHTH + { BLOC_BCCHN_TOP,BLOC_BCCHN_TOP_SIZE}, // BCCHN_TOP + { BLOC_SYNCHRO, BLOC_SYNCHRO_SIZE } // SYNCHRO + }; + + const UWORD8 DSP_TASK_CODE[NBR_DL_L1S_TASKS] = + { + CHECKSUM_DSP_TASK,// HWTEST + 0, // DEDIC (not meaningfull) + 0, // ADC (not meaningfull) + RACH_DSP_TASK, // RAACC + RACH_DSP_TASK, // RAHO + 0, // NSYNC (not meaningfull) + FB_DSP_TASK, // FBNEW + SB_DSP_TASK, // SBCONF + SB_DSP_TASK, // SB2 + TCH_FB_DSP_TASK, // FB26 + TCH_SB_DSP_TASK, // SB26 + TCH_SB_DSP_TASK, // SBCNF26 + FB_DSP_TASK, // FB51 + SB_DSP_TASK, // SB51 + SB_DSP_TASK, // SBCNF51 + NBN_DSP_TASK, // BCCHN + ALLC_DSP_TASK, // ALLC + NBS_DSP_TASK, // EBCCHS + NBS_DSP_TASK, // NBCCHS + DDL_DSP_TASK, // Temporary (BUG IN SIMULATOR) CB_DSP_TASK, // SMSCB + NP_DSP_TASK, // NP + EP_DSP_TASK, // EP + ADL_DSP_TASK, // ADL + AUL_DSP_TASK, // AUL + DDL_DSP_TASK, // DDL + DUL_DSP_TASK, // DUL + TCHD_DSP_TASK, // TCHD + TCHA_DSP_TASK, // TCHA + TCHT_DSP_TASK, // TCHTF + TCHT_DSP_TASK, // TCHTH + NBN_DSP_TASK, // BCCHN_TOP == BCCHN + 0, // SYNCHRO (not meaningfull) + }; +#else + const T_TASK_MFTAB TASK_ROM_MFTAB[NBR_DL_L1S_TASKS] = + { + { BLOC_HWTEST, BLOC_HWTEST_SIZE }, // HWTEST + { BLOC_ADC, BLOC_ADC_SIZE }, // ADC in CS_MODE0 + { NULL, 0 }, // DEDIC (not meaningfull) + { BLOC_RAACC, BLOC_RAACC_SIZE }, // RAACC + { NULL, 0 }, // RAHO (not meaningfull) + { NULL, 0 }, // NSYNC (not meaningfull) + { BLOC_POLL , BLOC_POLL_SIZE }, // POLL + { BLOC_PRACH, BLOC_PRACH_SIZE }, // PRACH + { BLOC_ITMEAS, BLOC_ITMEAS_SIZE }, // ITMEAS + { BLOC_FBNEW, BLOC_FBNEW_SIZE }, // FBNEW + { BLOC_SBCONF, BLOC_SBCONF_SIZE }, // SBCONF + { BLOC_SB2, BLOC_SB2_SIZE }, // SB2 + { BLOC_PTCCH, BLOC_PTCCH_SIZE }, // PTCCH + { BLOC_FB26, BLOC_FB26_SIZE }, // FB26 + { BLOC_SB26, BLOC_SB26_SIZE }, // SB26 + { BLOC_SBCNF26, BLOC_SBCNF26_SIZE }, // SBCNF26 + { BLOC_FB51, BLOC_FB51_SIZE }, // FB51 + { BLOC_SB51, BLOC_SB51_SIZE }, // SB51 + { BLOC_SBCNF51, BLOC_SBCNF51_SIZE }, // SBCNF51 + { BLOC_PDTCH, BLOC_PDTCH_SIZE }, // PDTCH + { BLOC_BCCHN, BLOC_BCCHN_SIZE }, // BCCHN + { BLOC_ALLC, S_RECT4_SIZE }, // ALLC + { BLOC_EBCCHS, S_RECT4_SIZE }, // EBCCHS + { BLOC_NBCCHS, S_RECT4_SIZE }, // NBCCHS + { BLOC_ADL, S_RECT4_SIZE }, // ADL + { BLOC_AUL, S_RECT4_SIZE }, // AUL + { BLOC_DDL, S_RECT4_SIZE }, // DDL + { BLOC_DUL, S_RECT4_SIZE }, // DUL + { BLOC_TCHD, BLOC_TCHT_SIZE }, // TCHD + { BLOC_TCHA, BLOC_TCHA_SIZE }, // TCHA + { BLOC_TCHTF, BLOC_TCHT_SIZE }, // TCHTF + { BLOC_TCHTH, BLOC_TCHT_SIZE }, // TCHTH + { BLOC_PALLC, BLOC_PCCCH_SIZE }, // PALLC + { BLOC_SMSCB, BLOC_SMSCB_SIZE }, // SMSCB + { BLOC_PBCCHS, BLOC_PBCCHS_SIZE }, // PBCCHS + { BLOC_PNP, BLOC_PCCCH_SIZE }, // PNP + { BLOC_PEP, BLOC_PCCCH_SIZE }, // PEP + { BLOC_SINGLE, BLOC_SINGLE_SIZE }, // SINGLE + { BLOC_PBCCHN_TRAN, BLOC_PBCCHN_TRAN_SIZE }, // PBCCHN_TRAN + { BLOC_PBCCHN_IDLE, BLOC_PBCCHN_IDLE_SIZE }, // PBCCHN_IDLE + { BLOC_BCCHN_TRAN, BLOC_BCCHN_TRAN_SIZE }, // BCCHN_TRAN + { BLOC_NP, S_RECT4_SIZE }, // NP + { BLOC_EP, S_RECT4_SIZE }, // EP + { BLOC_BCCHN_TOP, BLOC_BCCHN_TOP_SIZE}, // BCCHN_TOP + { BLOC_SYNCHRO, BLOC_SYNCHRO_SIZE } // SYNCHRO + }; + + const UWORD8 DSP_TASK_CODE[NBR_DL_L1S_TASKS] = + { + CHECKSUM_DSP_TASK,// HWTEST + 0, // ADC (not meaningfull) + 0, // DEDIC (not meaningfull) + RACH_DSP_TASK, // RAACC + RACH_DSP_TASK, // RAHO + 0, // NSYNC (not meaningfull) + 0, // POLL (not meaningfull) + 0, // PRACH (not meaningfull) + 0, // ITMEAS + FB_DSP_TASK, // FBNEW + SB_DSP_TASK, // SBCONF + SB_DSP_TASK, // SB2 + PTCCHU_DSP_TASK, // PTCCH + TCH_FB_DSP_TASK, // FB26 + TCH_SB_DSP_TASK, // SB26 + TCH_SB_DSP_TASK, // SBCNF26 + FB_DSP_TASK, // FB51 + SB_DSP_TASK, // SB51 + SB_DSP_TASK, // SBCNF51 + 0, // PDTCH (not meaningfull) + NBN_DSP_TASK, // BCCHN + ALLC_DSP_TASK, // ALLC + NBS_DSP_TASK, // EBCCHS + NBS_DSP_TASK, // NBCCHS + ADL_DSP_TASK, // ADL + AUL_DSP_TASK, // AUL + DDL_DSP_TASK, // DDL + DUL_DSP_TASK, // DUL + TCHD_DSP_TASK, // TCHD + TCHA_DSP_TASK, // TCHA + TCHT_DSP_TASK, // TCHTF + TCHT_DSP_TASK, // TCHTH + 0, // PALLC (not meaningfull) + DDL_DSP_TASK, // Temporary (BUG IN SIMULATOR) CB_DSP_TASK, // SMSCB + DDL_DSP_TASK, // PBCCHS (In order to allow PBCCHS running in CS or Idle mode, we have to specify a valid DSP task in order to request a PBCCHS with the GSM scheduler) + 0, // PNP (not meaningfull) + 0, // PEP (not meaningfull) + 0, // SINGLE (not meaningfull) + 0, // PBCCHN_TRAN (not meaningfull) + DDL_DSP_TASK, // PBCCHN_IDLE (only for GSM scheduler the task used is the same as SMSCB task) + NBN_DSP_TASK, // BCCHN_TRAN == BCCHN + NP_DSP_TASK, // NP + EP_DSP_TASK, // EP + NBN_DSP_TASK, // BCCHN_TOP == BCCHN + 0 // SYNCHRO (not meaningfull) + }; + +#endif + + const UWORD8 REPORTING_PERIOD[] = + { + 255, // INVALID_CHANNEL -> invalid reporting period + 104, // TCH_F + 104, // TCH_H + 102, // SDCCH_4 + 102 // SDCCH_8 + }; + + const UWORD8 TOA_PERIOD_LEN[] = + { + 0, // CS_MODE0 not used for histogram filling + 12, // CS_MODE histogram length + 12, // I_MODE histogram length + 12, // CON_EST_MODE1 histogram length + 144, // CON_EST_MODE2 histogram length + 36, // DEDIC_MODE (Full rate) histogram length + 42 // DEDIC_MODE (Half rate) histogram length + #if L1_GPRS + ,16 // PACKET TRANSFER MODE histogram length + #endif + }; + + // #if (STD == GSM) + const UWORD8 MIN_TXPWR_GSM[] = + { + 0, // unused. + 0, // Power class = 1, unused for GSM900 + 2, // Power class = 2. + 3, // Power class = 3. + 5, // Power class = 4. + 7 // Power class = 5. + }; + // #elif (STD == PCS1900) + const UWORD8 MIN_TXPWR_PCS[] = + { + 0, // unused. + 0, // Power class = 1. + 3, // Power class = 2. + 30 // Power class = 3. + }; + // #elif (STD == DCS1800) + const UWORD8 MIN_TXPWR_DCS[] = + { + 0, // unused. + 0, // Power class = 1. + 3, // Power class = 2. + 29 // Power class = 3. }; - #if !L1_GPRS - const T_TASK_MFTAB TASK_ROM_MFTAB[NBR_DL_L1S_TASKS] = - { - { BLOC_HWTEST, BLOC_HWTEST_SIZE }, // HWTEST - { BLOC_ADC , BLOC_ADC_SIZE }, // ADC in CS_MODE0 - { NULL, 0 }, // DEDIC (not meaningfull) - { BLOC_RAACC, BLOC_RAACC_SIZE }, // RAACC - { NULL, 0 }, // RAHO (not meaningfull) - { NULL, 0 }, // NSYNC (not meaningfull) - { BLOC_FBNEW, BLOC_FBNEW_SIZE }, // FBNEW - { BLOC_SBCONF, BLOC_SBCONF_SIZE }, // SBCONF - { BLOC_SB2, BLOC_SB2_SIZE }, // SB2 - { BLOC_FB26, BLOC_FB26_SIZE }, // FB26 - { BLOC_SB26, BLOC_SB26_SIZE }, // SB26 - { BLOC_SBCNF26, BLOC_SBCNF26_SIZE }, // SBCNF26 - { BLOC_FB51, BLOC_FB51_SIZE }, // FB51 - { BLOC_SB51, BLOC_SB51_SIZE }, // SB51 - { BLOC_SBCNF51, BLOC_SBCNF51_SIZE }, // SBCNF51 - { BLOC_BCCHN, BLOC_BCCHN_SIZE }, // BCCHN - { BLOC_ALLC, S_RECT4_SIZE }, // ALLC - { BLOC_EBCCHS, S_RECT4_SIZE }, // EBCCHS - { BLOC_NBCCHS, S_RECT4_SIZE }, // NBCCHS - { BLOC_SMSCB, BLOC_SMSCB_SIZE }, // SMSCB - { BLOC_NP, S_RECT4_SIZE }, // NP - { BLOC_EP, S_RECT4_SIZE }, // EP - { BLOC_ADL, S_RECT4_SIZE }, // ADL - { BLOC_AUL, S_RECT4_SIZE }, // AUL - { BLOC_DDL, S_RECT4_SIZE }, // DDL - { BLOC_DUL, S_RECT4_SIZE }, // DUL - { BLOC_TCHD, BLOC_TCHT_SIZE }, // TCHD - { BLOC_TCHA, BLOC_TCHA_SIZE }, // TCHA - { BLOC_TCHTF, BLOC_TCHT_SIZE }, // TCHTF - { BLOC_TCHTH, BLOC_TCHT_SIZE }, // TCHTH - { BLOC_BCCHN_TOP,BLOC_BCCHN_TOP_SIZE}, // BCCHN_TOP -#if ((REL99 == 1) && (FF_BHO == 1)) - { BLOC_FBSB, BLOC_FBSB_SIZE }, // FBSB -#endif - { BLOC_SYNCHRO, BLOC_SYNCHRO_SIZE } // SYNCHRO - }; - - const UWORD8 DSP_TASK_CODE[NBR_DL_L1S_TASKS] = + const UWORD8 MIN_TXPWR_GSM850[] = { - CHECKSUM_DSP_TASK,// HWTEST - 0, // DEDIC (not meaningfull) - 0, // ADC (not meaningfull) - RACH_DSP_TASK, // RAACC - RACH_DSP_TASK, // RAHO - 0, // NSYNC (not meaningfull) - FB_DSP_TASK, // FBNEW - SB_DSP_TASK, // SBCONF - SB_DSP_TASK, // SB2 - TCH_FB_DSP_TASK, // FB26 - TCH_SB_DSP_TASK, // SB26 - TCH_SB_DSP_TASK, // SBCNF26 - FB_DSP_TASK, // FB51 - SB_DSP_TASK, // SB51 - SB_DSP_TASK, // SBCNF51 - NBN_DSP_TASK, // BCCHN - ALLC_DSP_TASK, // ALLC - NBS_DSP_TASK, // EBCCHS - NBS_DSP_TASK, // NBCCHS - DDL_DSP_TASK, // Temporary (BUG IN SIMULATOR) CB_DSP_TASK, // SMSCB - NP_DSP_TASK, // NP - EP_DSP_TASK, // EP - ADL_DSP_TASK, // ADL - AUL_DSP_TASK, // AUL - DDL_DSP_TASK, // DDL - DUL_DSP_TASK, // DUL - TCHD_DSP_TASK, // TCHD - TCHA_DSP_TASK, // TCHA - TCHT_DSP_TASK, // TCHTF - TCHT_DSP_TASK, // TCHTH - NBN_DSP_TASK, // BCCHN_TOP == BCCHN -#if ((REL99 == 1) && (FF_BHO == 1)) - FBSB_DSP_TASK, // FBSB -#endif - 0, // SYNCHRO (not meaningfull) - }; - #else - const T_TASK_MFTAB TASK_ROM_MFTAB[NBR_DL_L1S_TASKS] = - { - { BLOC_HWTEST, BLOC_HWTEST_SIZE }, // HWTEST - { BLOC_ADC, BLOC_ADC_SIZE }, // ADC in CS_MODE0 - { NULL, 0 }, // DEDIC (not meaningfull) - { BLOC_RAACC, BLOC_RAACC_SIZE }, // RAACC - { NULL, 0 }, // RAHO (not meaningfull) - { NULL, 0 }, // NSYNC (not meaningfull) - { BLOC_POLL , BLOC_POLL_SIZE }, // POLL - { BLOC_PRACH, BLOC_PRACH_SIZE }, // PRACH - { BLOC_ITMEAS, BLOC_ITMEAS_SIZE }, // ITMEAS - { BLOC_FBNEW, BLOC_FBNEW_SIZE }, // FBNEW - { BLOC_SBCONF, BLOC_SBCONF_SIZE }, // SBCONF - { BLOC_SB2, BLOC_SB2_SIZE }, // SB2 - { BLOC_PTCCH, BLOC_PTCCH_SIZE }, // PTCCH - { BLOC_FB26, BLOC_FB26_SIZE }, // FB26 - { BLOC_SB26, BLOC_SB26_SIZE }, // SB26 - { BLOC_SBCNF26, BLOC_SBCNF26_SIZE }, // SBCNF26 - { BLOC_FB51, BLOC_FB51_SIZE }, // FB51 - { BLOC_SB51, BLOC_SB51_SIZE }, // SB51 - { BLOC_SBCNF51, BLOC_SBCNF51_SIZE }, // SBCNF51 - { BLOC_PDTCH, BLOC_PDTCH_SIZE }, // PDTCH - { BLOC_BCCHN, BLOC_BCCHN_SIZE }, // BCCHN - { BLOC_ALLC, S_RECT4_SIZE }, // ALLC - { BLOC_EBCCHS, S_RECT4_SIZE }, // EBCCHS - { BLOC_NBCCHS, S_RECT4_SIZE }, // NBCCHS - { BLOC_ADL, S_RECT4_SIZE }, // ADL - { BLOC_AUL, S_RECT4_SIZE }, // AUL - { BLOC_DDL, S_RECT4_SIZE }, // DDL - { BLOC_DUL, S_RECT4_SIZE }, // DUL - { BLOC_TCHD, BLOC_TCHT_SIZE }, // TCHD - { BLOC_TCHA, BLOC_TCHA_SIZE }, // TCHA - { BLOC_TCHTF, BLOC_TCHT_SIZE }, // TCHTF - { BLOC_TCHTH, BLOC_TCHT_SIZE }, // TCHTH - { BLOC_PALLC, BLOC_PCCCH_SIZE }, // PALLC - { BLOC_SMSCB, BLOC_SMSCB_SIZE }, // SMSCB - { BLOC_PBCCHS, BLOC_PBCCHS_SIZE }, // PBCCHS - { BLOC_PNP, BLOC_PCCCH_SIZE }, // PNP - { BLOC_PEP, BLOC_PCCCH_SIZE }, // PEP - { BLOC_SINGLE, BLOC_SINGLE_SIZE }, // SINGLE - { BLOC_PBCCHN_TRAN, BLOC_PBCCHN_TRAN_SIZE }, // PBCCHN_TRAN - { BLOC_PBCCHN_IDLE, BLOC_PBCCHN_IDLE_SIZE }, // PBCCHN_IDLE - { BLOC_BCCHN_TRAN, BLOC_BCCHN_TRAN_SIZE }, // BCCHN_TRAN - { BLOC_NP, S_RECT4_SIZE }, // NP - { BLOC_EP, S_RECT4_SIZE }, // EP - { BLOC_BCCHN_TOP, BLOC_BCCHN_TOP_SIZE}, // BCCHN_TOP -#if ((REL99 == 1) && (FF_BHO == 1)) - { BLOC_FBSB, BLOC_FBSB_SIZE }, // FBSB -#endif - { BLOC_SYNCHRO, BLOC_SYNCHRO_SIZE } // SYNCHRO + 0, // unused. + 0, // Power class = 1, unused for GSM900 + 2, // Power class = 2. + 3, // Power class = 3. + 5, // Power class = 4. + 7 // Power class = 5. }; - const UWORD8 DSP_TASK_CODE[NBR_DL_L1S_TASKS] = - { - CHECKSUM_DSP_TASK,// HWTEST - 0, // ADC (not meaningfull) - 0, // DEDIC (not meaningfull) - RACH_DSP_TASK, // RAACC - RACH_DSP_TASK, // RAHO - 0, // NSYNC (not meaningfull) - 0, // POLL (not meaningfull) - 0, // PRACH (not meaningfull) - 0, // ITMEAS - FB_DSP_TASK, // FBNEW - SB_DSP_TASK, // SBCONF - SB_DSP_TASK, // SB2 - PTCCHU_DSP_TASK, // PTCCH - TCH_FB_DSP_TASK, // FB26 - TCH_SB_DSP_TASK, // SB26 - TCH_SB_DSP_TASK, // SBCNF26 - FB_DSP_TASK, // FB51 - SB_DSP_TASK, // SB51 - SB_DSP_TASK, // SBCNF51 - 0, // PDTCH (not meaningfull) - NBN_DSP_TASK, // BCCHN - ALLC_DSP_TASK, // ALLC - NBS_DSP_TASK, // EBCCHS - NBS_DSP_TASK, // NBCCHS - ADL_DSP_TASK, // ADL - AUL_DSP_TASK, // AUL - DDL_DSP_TASK, // DDL - DUL_DSP_TASK, // DUL - TCHD_DSP_TASK, // TCHD - TCHA_DSP_TASK, // TCHA - TCHT_DSP_TASK, // TCHTF - TCHT_DSP_TASK, // TCHTH - 0, // PALLC (not meaningfull) - DDL_DSP_TASK, // Temporary (BUG IN SIMULATOR) CB_DSP_TASK, // SMSCB - DDL_DSP_TASK, // PBCCHS (In order to allow PBCCHS running in CS or Idle mode, we have to specify a valid DSP task in order to request a PBCCHS with the GSM scheduler) - 0, // PNP (not meaningfull) - 0, // PEP (not meaningfull) - 0, // SINGLE (not meaningfull) - 0, // PBCCHN_TRAN (not meaningfull) - DDL_DSP_TASK, // PBCCHN_IDLE (only for GSM scheduler the task used is the same as SMSCB task) - NBN_DSP_TASK, // BCCHN_TRAN == BCCHN - NP_DSP_TASK, // NP - EP_DSP_TASK, // EP - NBN_DSP_TASK, // BCCHN_TOP == BCCHN -#if ((REL99 == 1) && (FF_BHO == 1)) - FBSB_DSP_TASK, // FBSB -#endif - 0 // SYNCHRO (not meaningfull) - }; - - #endif +// #elif (STD == DUAL) + // const UWORD8 MIN_TXPWR_GSM[] = + // { + // 0, // unused. + // 0, // Power class = 1, unused for GSM900 + // 2, // Power class = 2. + // 3, // Power class = 3. + // 5, // Power class = 4. + // 7 // Power class = 5. + // }; + // const UWORD8 MIN_TXPWR_DCS[] = + // { + // 0, // unused. + // 0, // Power class = 1. + // 3, // Power class = 2. + // 29 // Power class = 3. + // }; +// #endif - const UWORD8 REPORTING_PERIOD[] = - { - 255, // INVALID_CHANNEL -> invalid reporting period - 104, // TCH_F - 104, // TCH_H - 102, // SDCCH_4 - 102 // SDCCH_8 - }; - - const UWORD8 TOA_PERIOD_LEN[] = - { - 0, // CS_MODE0 not used for histogram filling - 12, // CS_MODE histogram length - 12, // I_MODE histogram length - 12, // CON_EST_MODE1 histogram length - 144, // CON_EST_MODE2 histogram length - 36, // DEDIC_MODE (Full rate) histogram length - 42, // DEDIC_MODE (Half rate) histogram length - #if L1_GPRS - 16, // PACKET TRANSFER MODE histogram length - #endif - }; - - // #if (STD == GSM) - const UWORD8 MIN_TXPWR_GSM[] = - { - 0, // unused. - 0, // Power class = 1, unused for GSM900 - 2, // Power class = 2. - 3, // Power class = 3. - 5, // Power class = 4. - 7 // Power class = 5. - }; - // #elif (STD == PCS1900) - const UWORD8 MIN_TXPWR_PCS[] = - { - 0, // unused. - 0, // Power class = 1. - 3, // Power class = 2. - 30 // Power class = 3. - }; - // #elif (STD == DCS1800) - const UWORD8 MIN_TXPWR_DCS[] = - { - 0, // unused. - 0, // Power class = 1. - 3, // Power class = 2. - 29 // Power class = 3. - }; - - const UWORD8 MIN_TXPWR_GSM850[] = - { - 0, // unused. - 0, // Power class = 1, unused for GSM900 - 2, // Power class = 2. - 3, // Power class = 3. - 5, // Power class = 4. - 7 // Power class = 5. - }; - - // #elif (STD == DUAL) - // const UWORD8 MIN_TXPWR_GSM[] = - // { - // 0, // unused. - // 0, // Power class = 1, unused for GSM900 - // 2, // Power class = 2. - // 3, // Power class = 3. - // 5, // Power class = 4. - // 7 // Power class = 5. - // }; - // const UWORD8 MIN_TXPWR_DCS[] = - // { - // 0, // unused. - // 0, // Power class = 1. - // 3, // Power class = 2. - // 29 // Power class = 3. - // }; - // #endif - - const UWORD8 GAUG_VS_PAGING_RATE[] = - { - 4, // bs_pa_mfrms = 2, 1 gauging every 4 Paging blocs - 3, // bs_pa_mfrms = 3, 1 gauging every 3 Paging blocs - 2, // bs_pa_mfrms = 4, 1 gauging every 2 Paging blocs - 1, // bs_pa_mfrms = 5, 1 gauging every 1 Paging bloc - 1, // bs_pa_mfrms = 6, 1 gauging every 1 Paging bloc - 1, // bs_pa_mfrms = 7, 1 gauging every 1 Paging bloc - 1, // bs_pa_mfrms = 8, 1 gauging every 1 Paging bloc - 1 // bs_pa_mfrms = 9, 1 gauging every 1 Paging bloc - }; - - #else - extern T_IDLE_TASK_INFO IDLE_INFO_COMB[(MAX_AG_BLKS_RES_COMB+1) * (MAX_PG_BLOC_INDEX_COMB+1)]; - extern T_IDLE_TASK_INFO IDLE_INFO_NCOMB[(MAX_AG_BLKS_RES_NCOMB+1) * (MAX_PG_BLOC_INDEX_NCOMB+1)]; - extern UWORD8 NBPCH_IN_MF51_NCOMB[(MAX_AG_BLKS_RES_NCOMB+1)]; - extern UWORD8 NBPCH_IN_MF51_COMB[(MAX_AG_BLKS_RES_COMB+1)]; - extern UWORD8 DSC_INIT_VALUE[MAX_BS_PA_MFRMS-2]; - extern T_SDCCH_DESC SDCCH_DESC_NCOMB[]; - extern T_SDCCH_DESC SDCCH_DESC_COMB[]; - extern UWORD8 RNTABLE[114]; - extern UWORD8 COMBINED_RA_DISTRIB[51]; - extern T_TASK_MFTAB TASK_ROM_MFTAB[NBR_DL_L1S_TASKS]; - extern UWORD8 DSP_TASK_CODE[NBR_DL_L1S_TASKS]; - extern UWORD8 REPORTING_PERIOD[]; - extern UWORD8 TOA_PERIOD_LEN[]; - extern UWORD8 MIN_TXPWR_GSM[]; - extern UWORD8 MIN_TXPWR_DCS[]; - extern UWORD8 MIN_TXPWR_PCS[]; - extern UWORD8 MIN_TXPWR_GSM850[]; - extern UWORD8 GAUG_VS_PAGING_RATE[]; - #endif -#endif //L1_TABS_H +const UWORD8 GAUG_VS_PAGING_RATE[] = +{ + 4, // bs_pa_mfrms = 2, 1 gauging every 4 Paging blocs + 3, // bs_pa_mfrms = 3, 1 gauging every 3 Paging blocs + 2, // bs_pa_mfrms = 4, 1 gauging every 2 Paging blocs + 1, // bs_pa_mfrms = 5, 1 gauging every 1 Paging bloc + 1, // bs_pa_mfrms = 6, 1 gauging every 1 Paging bloc + 1, // bs_pa_mfrms = 7, 1 gauging every 1 Paging bloc + 1, // bs_pa_mfrms = 8, 1 gauging every 1 Paging bloc + 1 // bs_pa_mfrms = 9, 1 gauging every 1 Paging bloc +}; + +#else + extern T_IDLE_TASK_INFO IDLE_INFO_COMB[(MAX_AG_BLKS_RES_COMB+1) * (MAX_PG_BLOC_INDEX_COMB+1)]; + extern T_IDLE_TASK_INFO IDLE_INFO_NCOMB[(MAX_AG_BLKS_RES_NCOMB+1) * (MAX_PG_BLOC_INDEX_NCOMB+1)]; + extern UWORD8 NBPCH_IN_MF51_NCOMB[(MAX_AG_BLKS_RES_NCOMB+1)]; + extern UWORD8 NBPCH_IN_MF51_COMB[(MAX_AG_BLKS_RES_COMB+1)]; + extern UWORD8 DSC_INIT_VALUE[MAX_BS_PA_MFRMS-2]; + extern T_SDCCH_DESC SDCCH_DESC_NCOMB[]; + extern T_SDCCH_DESC SDCCH_DESC_COMB[]; + extern UWORD8 RNTABLE[114]; + extern UWORD8 COMBINED_RA_DISTRIB[51]; + extern T_TASK_MFTAB TASK_ROM_MFTAB[NBR_DL_L1S_TASKS]; + extern UWORD8 DSP_TASK_CODE[NBR_DL_L1S_TASKS]; + extern UWORD8 REPORTING_PERIOD[]; + extern UWORD8 TOA_PERIOD_LEN[]; + extern UWORD8 MIN_TXPWR_GSM[]; + extern UWORD8 MIN_TXPWR_DCS[]; + extern UWORD8 MIN_TXPWR_PCS[]; + extern UWORD8 MIN_TXPWR_GSM850[]; + extern UWORD8 GAUG_VS_PAGING_RATE[]; +#endif
--- a/L1/include/l1_time.h Thu Jun 09 00:19:28 2016 +0000 +++ b/L1/include/l1_time.h Thu Jun 09 00:45:00 2016 +0000 @@ -91,16 +91,8 @@ #define D_NSUBB_IDLE 296L // Nb of 48 samples window for FBNEW task. #if (CODE_VERSION==SIMULATION) #define D_NSUBB_DEDIC 31L // Nb of 48 samples window for FB26 task. - //To simulate the handling of the worst case (FB/SB task with class 12 allocation), - //this parameter used in the computation of FB26_ACQUIS_DURATION has to fit with the - //value used outside the PC simulation (D_NSUBB_DEDIC) - //This value will only be used for mac_mode = Extended Dynamic Allocation to minimize the - //impact on reference simulation files for other allocation modes - #if L1_EDA - #define D_NSUBB_DEDIC_EDA 30L // Nb of 48 samples window for FB26 task. - #endif #else - #if (DSP >= 32) + #if (DSP == 33) || (DSP == 34) || (DSP == 35) || (DSP == 32) || (DSP == 36) #define D_NSUBB_DEDIC 30L // Nb of 48 samples window for FB26 task. #else #define D_NSUBB_DEDIC 31L // Nb of 48 samples window for FB26 task. @@ -117,37 +109,15 @@ #define SWITCH_TIME ( TPU_CLOCK_RANGE - EPSILON_SYNC ) // = 4990, time for offset change. #define PROVISION_TIME ( 66L ) - -#ifndef EPSILON_SYNC - #define EPSILON_SYNC ( 10L ) // synchro change: max TOA shift=8qbits, 2qbits TPU scenario exec. -#endif - -#ifndef EPSILON_OFFS - #define EPSILON_OFFS ( 2L ) // offset change: 2qbits for TPU scenario exec. -#endif - -#ifndef EPSILON_MEAS - #define EPSILON_MEAS ( 20L ) // margin kept between RX and PW meas or between PW meas -#endif - -#ifndef SERV_OFFS_REST_LOAD - #define SERV_OFFS_REST_LOAD ( 1L ) // 1qbit TPU scen exec. for serv. cell offset restore -#endif - +#define EPSILON_SYNC ( 10L ) // synchro change: max TOA shift=8qbits, 2qbits TPU scenario exec. +#define EPSILON_OFFS ( 2L ) // offset change: 2qbits for TPU scenario exec. +#define EPSILON_MEAS ( 20L ) // margin kept between RX and PW meas or between PW meas +#define SERV_OFFS_REST_LOAD ( 1L ) // 1qbit TPU scen exec. for serv. cell offset restore #define TPU_SLEEP_LOAD ( 2L ) // 2qbit TPU scen exec. for TPU sleep #if (CODE_VERSION==SIMULATION) - #define DL_ABB_DELAY ( 32L ) // RX ABB filter delay + #define DL_ABB_DELAY ( 32L ) // RX ABB filter delay #else - #if (RF_FAM != 61) - #ifndef DL_ABB_DELAY //Flexi ABB Delays defines it in tpudrvXX.c - #define DL_ABB_DELAY ( 32L + 4L) // RX ABB filter delay - #endif - #endif - #if (RF_FAM == 61) - #ifndef DL_ABB_DELAY //Flexi ABB Delays defines it in tpudrvXX.c - #define DL_ABB_DELAY ( 41L + 4L) // RX DRP filter delay - #endif - #endif + #define DL_ABB_DELAY ( 32L + 4L) // RX ABB filter delay #endif // DMA threshold used for sample acquisition by the DSP @@ -170,7 +140,7 @@ #if (CODE_VERSION==SIMULATION) #define TULSET_DURATION ( 16L ) // Uplink power on setup time #define BULRUDEL_DURATION ( 2L ) - #if ((ANALOG == 1) || (ANALOG == 2) || (ANALOG == 3) || (ANALOG == 11)) + #if ((ANALOG == 1) || (ANALOG == 2) || (ANALOG == 3)) // 16 qbits are added because the Calibration time is reduced of 4 GSM bit // due to a slow APC ramp of OMEGA (Cf. START_TX_NB) #define UL_VEGA_DELAY ( TULSET_DURATION + BULRUDEL_DURATION +16L ) // = 18qbits, TX Vega delay @@ -179,10 +149,7 @@ #define SB_MARGIN ( 23L * 4L ) // = 92 #define NB_MARGIN ( 3L * 4L ) // = 12 - -#ifndef TA_MAX //flexi Abb Delays defined in tpudrvXX.h - #define TA_MAX ( 63L * 4L ) // = 252 -#endif +#define TA_MAX ( 63L * 4L ) // = 252 #define SB_BURST_DURATION ( TAIL_WIDTH + ( 142L * 4L) ) // = 580, required for Demodulation #define NB_BURST_DURATION_DL ( TAIL_WIDTH + ( 142L * 4L) ) // = 580, required for Demodulation @@ -203,12 +170,7 @@ #define NB_ACQUIS_DURATION ( NB_MARGIN + NB_BURST_DURATION_DL + NB_MARGIN + DL_ABB_DELAY + RX_DMA_DELAY ) // = 636 + DMA delay #define PW_ACQUIS_DURATION ( PW_BURST_DURATION + DL_ABB_DELAY + RX_DMA_DELAY ) // = 288 + DMA delay #define FB_ACQUIS_DURATION ( ( D_NSUBB_IDLE * 48L * 4L ) + ( 48L * 4L ) + DL_ABB_DELAY + RX_DMA_DELAY ) // = 57056 + DMA delay -#if (L1_EDA) && (CODE_VERSION==SIMULATION) - #define FB26_ACQUIS_DURATION_DEFAULT ( ( D_NSUBB_DEDIC * 48L * 4L ) + DL_ABB_DELAY + RX_DMA_DELAY) // = 5984 + DMA delay - #define FB26_ACQUIS_DURATION_FOR_EDA ( ( D_NSUBB_DEDIC_EDA * 48L * 4L ) + DL_ABB_DELAY + RX_DMA_DELAY) // = 5984 + DMA delay -#else #define FB26_ACQUIS_DURATION ( ( D_NSUBB_DEDIC * 48L * 4L ) + DL_ABB_DELAY + RX_DMA_DELAY) // = 5984 + DMA delay -#endif #define START_RX_FB ( PROVISION_TIME ) // = 66 #define START_RX_SB ( PROVISION_TIME ) // = 66 @@ -221,18 +183,10 @@ #define STOP_RX_FB ( (PROVISION_TIME + FB_ACQUIS_DURATION) % TPU_CLOCK_RANGE ) // = 2122 #define STOP_RX_SB ( (START_RX_SB + SB_ACQUIS_DURATION) % TPU_CLOCK_RANGE ) // = 862 -#if ((REL99 == 1) && (FF_BHO == 1)) - #define STOP_RX_FBSB ( (STOP_RX_FB + 800L ) % TPU_CLOCK_RANGE ) // = 2922 -#endif #define STOP_RX_SNB ( (START_RX_SNB + NB_ACQUIS_DURATION) % TPU_CLOCK_RANGE ) // = 702 #define STOP_RX_PW_1 ( (START_RX_PW_1 + PW_ACQUIS_DURATION) % TPU_CLOCK_RANGE ) // = 354 #define STOP_RX_FB26 ( (START_RX_FB26 + FB26_ACQUIS_DURATION) % TPU_CLOCK_RANGE ) // = 4314 -#if (REL99 == 1 && FF_RTD == 1) // RTD feature -#define RTD_UNIT_MARGIN ( ((TPU_CLOCK_RANGE-8)/128L) + 1 ) // unit of RTD is 1/64 TDMA frame -#define RTD_RIGHT_MARGIN ( (TA_MAX/2L) + (RTD_UNIT_MARGIN) ) -#define RTD_LEFT_MARGIN ( RTD_RIGHT_MARGIN ) -#endif //================================ // Definitions used for GPRS
--- a/L1/include/l1_trace.h Thu Jun 09 00:19:28 2016 +0000 +++ b/L1/include/l1_trace.h Thu Jun 09 00:45:00 2016 +0000 @@ -36,58 +36,17 @@ #define TRACE_CHECK_RESULT_OPCODE 1023 // WARNING: UL opcode 1023 reseved for trace version // (cannot be used for trace) -#if (GSM_IDLE_RAM != 0) - #define INTRAM_TRACE_BUFFER_SIZE 128 - extern UWORD32 task_bitmap_idle_ram[2]; - extern UWORD32 mem_task_bitmap_idle_ram[2]; - extern CHAR intram_trace_buffer[INTRAM_TRACE_BUFFER_SIZE]; - extern CHAR * intram_buffer_current_ptr; - extern T_RVT_MSG_LG intram_trace_size; - - void l1_intram_send_trace(void); - -#endif - /****************************** ASCII trace only *****************************************/ #if (L1_BINARY_TRACE == 0) || (TRACE_TYPE == 5) - #if (OP_L1_STANDALONE == 1) - - #if (L1_DYN_DSP_DWNLD == 1 && CODE_VERSION == SIMULATION) - - #if (L1_FF_MULTIBAND == 0) - // Dyn DWNLD (0x0001000) MP3 & MIDI traces activated (0x4000 and 0x2000) - #define DEFAULT_DYN_TRACE_CONFIG 0x00016AE7 - #else - #define DEFAULT_DYN_TRACE_CONFIG ( 0x00016AE7 | (1<<L1_DYN_TRACE_MULTIBAND) ) - #endif - - #else // Below for normal L1 standalone with dynamic download - - #if (L1_FF_MULTIBAND == 0) - // MP3 & MIDI traces activated (0x4000 and 0x2000) - #define DEFAULT_DYN_TRACE_CONFIG 0x028A6AE7 - #else - #define DEFAULT_DYN_TRACE_CONFIG ( 0x028A6AE7 | (1<<L1_DYN_TRACE_MULTIBAND) ) - #endif // L1_FF_MULTIBAND - - #endif // L1_DYN_DSP_DWNLD == 1 && CODE_VERSION == SIMULATION - + #define DEFAULT_DYN_TRACE_CONFIG 0x00000A67 #elif (OP_WCP == 1) - // WCP patch: default config is no Layer1 trace #define DEFAULT_DYN_TRACE_CONFIG 0x00000000 // default was 0x00000BB7 // End WCP patch - #else - - #if (L1_FF_MULTIBAND == 0) - #define DEFAULT_DYN_TRACE_CONFIG 0x00881BB7 - #else - #define DEFAULT_DYN_TRACE_CONFIG ( 0x00881BB7 | (1<<L1_DYN_TRACE_MULTIBAND) ) - #endif - + #define DEFAULT_DYN_TRACE_CONFIG 0x00000BB7 #endif // Possible EVENTS for L1S traces using TRACE_INFO. @@ -115,36 +74,10 @@ #define IT_DSP_ERROR 20 #define TRACE_ADC 21 #define PTCCH_DISABLED 22 - #if (OP_L1_STANDALONE == 0) - #define DYN_TRACE_DEBUG 23 // Currently only work with TRACE_TYPE 4 - #endif + #define DYN_TRACE_DEBUG 23 // Currently only work with TRACE_TYPE 4 #define DEDIC_TCH_BLOCK_STAT 24 - #define DSP_TRACE_DISABLE 25 // Only works with TRACE_TYPE 1 or 4 - #define DSP_TRACE_ENABLE 26 // Only works with TRACE_TYPE 1 or 4 - #if (L1_AUDIO_MCU_ONOFF == 1) - #define L1_AUDIO_UL_ONOFF_TRACE 27 - #define L1_AUDIO_DL_ONOFF_TRACE 28 - #endif - #define SAIC_DEBUG 29 - #define BURST_PARAM 30 - #define TRACE_RATSCCH 31 - #define NAVC_VALUE 32 - #define PWMGT_FAIL_SLEEP 33 - #define KPD_CR 34 - -#if(L1_PCM_EXTRACTION) - #define L1S_PCM_ERROR_TRACE 35 -#endif - #define IQ_LOW 36 - #if FF_TBF //verify these event numbers - #define NO_BLOCKS_PASSED_TO_L3 37 - #define LACK_FREE_RLC_BUFFER 38 - #define RLC_BLOCK_OVERRUN 39 - #define EGPRS_IT_DSP_MISSING 40 - #define EGPRS_IT_DSP_SPURIOUS 41 - #define IR_TESTING 42 - #define RLC_POLL_PARAM 43 - #endif + #define TRACE_RATSCCH 25 + // Wakeup Type for Power management //-------------------------------- #define WAKEUP_FOR_UNDEFINED 0 @@ -166,20 +99,10 @@ #define BIG_SLEEP_DUE_TO_SLEEP_MODE 5 // deep sleep is forbiden by the sleep mode enabled #define BIG_SLEEP_DUE_TO_DSP_TRACES 6 // deep sleep is forbiden by the DSP #define BIG_SLEEP_DUE_TO_BLUETOOTH 7 // deep sleep is forbiden by the Bluetooth module - #define BIG_SLEEP_DUE_TO_CAMERA 8 // deep sleep is forbiden by the camera void Trace_Packet_Transfer (UWORD8 prev_crc_error); // Previous RX blocks CRC_ERROR summary void l1_display_buffer_trace_fct(void); - // Possible cause for IT_DSP_ERROR - //----------------------------------- - #define IT_DSP_ERROR_CPU_OVERLOAD 0 -#if (FF_L1_FAST_DECODING == 1) - #define IT_DSP_ERROR_FAST_DECODING 2 - #define IT_DSP_ERROR_FAST_DECODING_UNEXP 3 -#endif - - //=================================================== //=========== BUFFER TRACE ========================== //=================================================== @@ -424,70 +347,6 @@ UWORD32 rttl1_event_enable; } T_TRACE_CONFIG; -// Disable/enable DSP trace structure -#if (TRACE_TYPE == 1) || (TRACE_TYPE == 4) -#if (MELODY_E2 || L1_MP3 || L1_AAC || L1_DYN_DSP_DWNLD ) - -typedef struct -{ - // Flag for blocking dsp trace while performing e2, mp3, aac or dynamic download activities - BOOL trace_flag_blocked; - // Nested Disable dsp trace counter - UWORD8 nested_disable_count; - // Trace level copy to be restored at the end of e2, mp3, aac or dynamic download activities - UWORD16 dsp_trace_level_copy; -} T_DSP_TRACE_HANDLER; - -#endif -#endif // (TRACE_TYPE == 1) || (TRACE_TYPE == 4) - -#if (TOA_ALGO == 2) -typedef struct -{ - UWORD16 toa_frames_counter; // TOA Frames counter - Number of the TDMA frames (or bursts) which are used for TOA - // updation OR number of times l1ctl_toa() function is invoked - // Reset every TOA_PERIOD_LEN[l1_mode] frames - UWORD16 toa_accumul_counter; // Number of TDMA frames (or bursts) which are actually used for TOA tracking - // <= toa_frames_counter, as only if SNR>0.46875 TOA estimated by DSP is used to - // update the tracking algorithm - WORD16 toa_accumul_value; // TOA_tracking_value accumulated over 'toa_accumul_counter' frames - // Based on this value the shift to be applied is decided -}T_TRACE_TOA; -#endif - -typedef struct -{ - UWORD8 fail_step; // PWMGT Fail Step -> Periph Check OR osload/Timer/Gauging OR While puuting peripherals to sleep - UWORD8 fail_id; // PWMGT Fail ID -> i.e. If Periph Check is the fail step whether failure is because of UART, etc. - UWORD8 fail_cause; // Why the Peripheral returned failure? -}T_TRACE_L1_PWMGR_DEBUG; - -#if (AUDIO_DEBUG == 1) -typedef struct -{ - UWORD8 vocoder_enable_status; - UWORD8 ul_state; - UWORD8 dl_state; - UWORD8 ul_onoff_counter; - UWORD8 dl_onoff_counter; -}T_TRACE_AUDIO_DEBUG; -#endif - -typedef struct -{ - UWORD32 dl_count; /* Number of Downlink SACCH block */ - UWORD32 dl_combined_good_count; /* Number of successfully decoded combined block */ - UWORD32 dl_error_count; /* Total errors */ - UWORD8 srr; /* SACCH Repetition Request */ - UWORD8 sro; /* SACCH Repetition Order */ - /* trace,debug for FER */ - UWORD32 dl_good_norep; /* Number of correctly decoded block which is not a repetition */ - API dl_buffer[12]; /* Downlink buffer */ - BOOL dl_buffer_empty; /* Flag to indicate the downlink buffer is empty/full */ -} -T_TRACE_REPEAT_SACCH; - - // Debug info structure typedef struct { @@ -509,9 +368,6 @@ UWORD8 facch_dl_fail_count_trace; UWORD8 sacch_d_nerr; - #if (FF_REPEATED_SACCH == 1) - T_TRACE_REPEAT_SACCH repeat_sacch; - #endif /* (FF_REPEATED_SACCH == 1) */ UWORD8 rxlev_req_count; BOOL init_trace; @@ -538,10 +394,6 @@ T_RVT_USER_ID gtt_trace_user_id; #endif -#if (L1_MIDI == 1) - T_RVT_USER_ID midi_trace_user_id; -#endif - #if (D_ERROR_STATUS_TRACE_ENABLE) // define a mask array for handling of the d_error_status field UWORD16 d_error_status_masks[2]; @@ -566,37 +418,10 @@ UWORD32 task_bitmap[8]; UWORD32 mem_task_bitmap[8]; - #if (TOA_ALGO == 2) - T_TRACE_TOA toa_trace_var; - #endif - T_TRACE_L1_PWMGR_DEBUG pwmgt_trace_var; - #if(L1_SAIC != 0) - UWORD8 prev_saic_flag_val; - UWORD8 prev_swh_flag_val; - #endif // Dynamic trace T_TRACE_CONFIG config[2]; T_TRACE_CONFIG *current_config; T_TRACE_CONFIG *pending_config; - -#if (TRACE_TYPE == 1) || (TRACE_TYPE == 4) -#if (MELODY_E2 || L1_MP3 || L1_DYN_DSP_DWNLD) - // DSP Trace Handler global variables - T_DSP_TRACE_HANDLER dsptrace_handler_globals; -#endif -#endif // (TRACE_TYPE == 1) || (TRACE_TYPE == 4) -#if (AUDIO_DEBUG == 1) - T_TRACE_AUDIO_DEBUG audio_debug_var; -#endif -#if (L1_RF_KBD_FIX == 1) -UWORD16 prev_correction_ratio; -#endif -#if (FF_REPEATED_DL_FACCH == 1 ) - UWORD8 facch_dl_combined_good_count; /* Number of successfully decoded combined block */ - UWORD8 facch_dl_repetition_block_count; /*Number of repetition block*/ - UWORD8 facch_dl_count_all; /* Number of DL FACCH block*/ - UWORD8 facch_dl_good_block_reported; /* Number of correctly decoded block which is not a repetition */ -#endif } T_TRACE_INFO_STRUCT; @@ -607,40 +432,10 @@ /* Function prototypes */ /***********************/ -void l1_init_trace_var (void); -void l1_trace_init (void); +void l1_trace_init (); void Trace_L1s_Abort (UWORD8 task); void Trace_MCU_DSP_Com_Mismatch (UWORD8 task); void Trace_PM_Equal_0 (UWORD32 pm, UWORD8 task); -#if FF_TBF -void Trace_rlc_ul_param (UWORD8 assignment_id, - UWORD32 fn, - UWORD8 tx_no, - UWORD8 ta, - BOOL fix_alloc_exhaust, - UWORD32 cs_type); -void Trace_rlc_dl_param (UWORD8 assignment_id, - UWORD32 fn, - UWORD8 rx_no, - UWORD8 rlc_blocks_sent, - UWORD8 last_poll_response, - UWORD32 status1, - UWORD32 status2); -void Trace_rlc_poll_param (BOOL poll, - UWORD32 fn, - UWORD8 poll_ts, - UWORD8 tx_alloc, - UWORD8 tx_data, - UWORD8 rx_alloc, - UWORD8 last_poll_resp, - UWORD8 ack_type); -#else -void Trace_rlc_dl_param (UWORD8 assignment_id, - UWORD32 fn, - UWORD32 d_rlcmac_rx_no_gprs, - UWORD8 rx_no, - UWORD8 rlc_blocks_sent, - UWORD8 last_poll_response); void Trace_rlc_ul_param (UWORD8 assignment_id, UWORD8 tx_no, UWORD32 fn, @@ -648,8 +443,13 @@ UWORD32 a_pu_gprs, UWORD32 a_du_gprs, BOOL fix_alloc_exhaust); -#endif -void Trace_uplink_no_TA (void); +void Trace_rlc_dl_param (UWORD8 assignment_id, + UWORD32 fn, + UWORD32 d_rlcmac_rx_no_gprs, + UWORD8 rx_no, + UWORD8 rlc_blocks_sent, + UWORD8 last_poll_response); +void Trace_uplink_no_TA (); void Trace_condensed_pdtch (UWORD8 rx_allocation, UWORD8 tx_allocation); void Trace_dl_ptcch (UWORD8 ordered_ta, UWORD8 crc, @@ -662,9 +462,11 @@ UWORD16 elt5, UWORD16 elt6, UWORD16 elt7, - UWORD16 elt8); -void Trace_d_error_status (void); -void Trace_dsp_debug (void); + UWORD16 elt8 + ); + +void Trace_d_error_status (); +void Trace_dsp_debug (); #if (AMR == 1) void Trace_dsp_amr_debug (void); #endif @@ -676,89 +478,29 @@ UWORD32 param4, UWORD32 param5, UWORD32 param6); -void Trace_L1S_CPU_load (void); -void l1_dsp_cpu_load_read (void); -void Trace_dyn_trace_change (void); +void Trace_L1S_CPU_load (); +void Trace_dyn_trace_change (); + #if (AMR == 1) -void l1_trace_ratscch (UWORD16 fn, UWORD16 amr_change_bitmap); +void l1_trace_ratscch (UWORD16 fn, UWORD16 amr_change_bitmap); #endif + void l1_trace_sleep (UWORD32 start_fn, UWORD32 end_fn, UWORD8 type_sleep, UWORD8 wakeup_type, - UWORD8 big_sleep_type, - UWORD16 int_id); -void l1_trace_fail_sleep (UWORD8 pwmgr_fail_step, - UWORD8 pwmgr_fail_id, - UWORD8 pwmgr_fail_cause); -void l1_trace_sleep_intram (UWORD32 start_fn, - UWORD32 end_fn, - UWORD8 type_sleep, - UWORD8 wakeup_type, - UWORD8 big_sleep_type, - UWORD16 int_id); + UWORD8 big_sleep_type); void l1_trace_gauging_reset (void); void l1_trace_gauging (void); -void l1_trace_gauging_intram (void); -#if (L1_SAIC != 0) -void l1_trace_saic (UWORD32 SWH_flag, UWORD32 SAIC_flag); -#endif - -#if (L1_NAVC_TRACE == 1) - void l1_trace_navc (UWORD32 status, UWORD32 energy_level); -#endif -void l1_trace_burst_param (UWORD32 angle, - UWORD32 snr, - UWORD32 afc, - UWORD32 task, - UWORD32 pm, - UWORD32 toa_val, - UWORD32 IL_for_rxlev); -void l1_log_burst_param (UWORD32 angle, - UWORD32 snr, - UWORD32 afc, - UWORD32 task, - UWORD32 pm, - UWORD32 toa_val, - UWORD32 IL_for_rxlev); void l1_trace_new_toa (void); -void l1_trace_new_toa_intram (void); void l1_trace_toa_not_updated (void); -void l1_trace_IT_DSP_error (UWORD8 cause); +void l1_trace_IT_DSP_error (void); void l1_trace_ADC (UWORD8 type); -void l1_trace_ADC_intram (UWORD8 type); void l1_check_com_mismatch (UWORD8 task); void l1_check_pm_error (UWORD32 pm,UWORD8 task); void Trace_PM_Equal_0_balance (void); void l1_trace_ptcch_disable (void); -void trace_fct (UWORD8 fct_id, UWORD32 radio_freq); -void l1_intram_put_trace (CHAR *msg); -void l1_trace_IT_DSP_error_intram(void); -void Trace_d_error_status_intram (void); -void l1s_trace_mftab (void); -void l1s_trace_mftab (void); - -#if (TRACE_TYPE == 1) || (TRACE_TYPE == 4) -#if (MELODY_E2 || L1_MP3 || L1_DYN_DSP_DWNLD) -void l1_disable_dsp_trace (void); -void l1_enable_dsp_trace (void); -void l1_set_dsp_trace_mask (UWORD16 mask); -UWORD16 l1_get_dsp_trace_mask (void); -#endif -#endif // (TRACE_TYPE == 1) || (TRACE_TYPE == 4) - -#if (L1_AUDIO_MCU_ONOFF == 1) -void l1_trace_ul_audio_onoff(UWORD8 ul_state); -void l1_trace_dl_audio_onoff(UWORD8 dl_state); -#endif -#if FF_TBF -// void l1_trace_egprs (UWORD8 type); - - //For burst power trace.AGC_TRACE - void l1_trace_agc (UWORD8 burst_id, UWORD8 agc); - void l1_trace_burst (UWORD8 *time_slot, UWORD8 burst_id); - void burst_trace_message(void); -#endif +void trace_fct (UWORD8 fct_id, WORD32 radio_freq); /****************/ /* Trace macros */ @@ -796,44 +538,10 @@ #define L1_DYN_TRACE_FULL_LIST_REPORT 10 //NAME/ Full list report #define L1_DYN_TRACE_GTT 11 //NAME/ GTT trace #define L1_DYN_TRACE_DSP_AMR_DEBUG 12 //NAME/ DSP AMR debug trace -#define L1_DYN_TRACE_MIDI 13 //NAME/ MIDI trace -#define L1_DYN_TRACE_MP3 14 //NAME/ MP3 trace -#define L1_DYN_TRACE_GAUGING 15 //NAME/ Gauging parameters #if(L1_DYN_DSP_DWNLD == 1) - #define L1_DYN_TRACE_DYN_DWNLD 16 //NAME/ DYN DWNLD trace + #define L1_DYN_TRACE_DYN_DWNLD 13 //NAME/ DYN DWNLD trace #endif // L1_DYN_DSP_DWNLD == 1 - -#if (L1_SAIC != 0) - #define L1_DYN_TRACE_SAIC_DEBUG 17 //NAME/ SAIC trace -#endif -#define L1_DYN_TRACE_BURST_PARAM 18 //NAME/ Burst Param - -#if (L1_AUDIO_MCU_ONOFF == 1) - #define L1_DYN_TRACE_AUDIO_ONOFF 19 -#endif -#if FF_TBF - #define L1_DYN_TRACE_POLL_PARAM 29 //NAME/ Poll parameters - #endif -// The Below flag is used to enable/disable the API dump over UART -#define L1_DYN_TRACE_API_DUMP 20 //NAME/ API dump - -#define L1_DSP_TRACE_FULL_DUMP 21 // flag for enabling the full trace buffer of DSP on PM error -#if (L1_AAC == 1) -#define L1_DYN_TRACE_AAC 22 //NAME/ AAC trace -#endif -#define L1_DYN_TRACE_PWMGT_FAIL_DEBUG 23 // NAME Power Management Sleep fail Trace - -#if(L1_RF_KBD_FIX == 1) -#define L1_DYN_TRACE_RF_KBD 24 //Make RF KPD trace dynamic -#endif - -#define L1_DYN_TRACE_DSP_CPU_LOAD 25 //NAME/ DSP CPU load trace - -#if (L1_FF_MULTIBAND == 1) -#define L1_DYN_TRACE_MULTIBAND 26 /*MULTIBAND DEBUG trace*/ -#endif - - +#define L1_DYN_TRACE_GAUGING 14 //NAME/ Gauging parameters //END_TRACE_CONF/ #define L1_DYN_TRACE_DL_PDTCH_CRC 6 // DL PDTCH blocks CRC, only used if L1_BINARY_TRACE == 0 @@ -1007,9 +715,6 @@ #define CST_DLL_READ_DCCH 123 //NAME/ dll_read_dcch() #define CST_DLL_READ_SACCH 124 //NAME/ dll_read_sacch() #define CST_L1S_ADJUST_TIME 125 //NAME/ Time adjustment -#if ((REL99 == 1) && (FF_BHO == 1)) - #define CST_L1S_CTRL_FBSB 128 //NAME/ l1s_ctrl_fbsb() -#endif //END_TABLE/ /***********************************************************/ @@ -1446,17 +1151,6 @@ UWORD16 rxqual_sub_nbr_bits; WORD16 rxlev_sub_acc; WORD16 rxlev_full_acc; - #if REL99 - #if FF_EMR - WORD16 rxlev_val_acc; - UWORD8 rxlev_val_nbr_meas; - UWORD32 mean_bep_block_acc; - UWORD16 cv_bep_block_acc; - UWORD8 mean_bep_block_num; - UWORD8 cv_bep_block_num; - UWORD8 nbr_rcvd_blocks; - #endif - #endif //L1_R99 UWORD16 bcch_freq[6]; WORD16 rxlev_acc[6]; BOOL meas_valid; @@ -4588,85 +4282,6 @@ UWORD32 header; } T_TR_MMI_VM_AMR_RECORD_STOP_CON; -/***********************************************************************************************************/ -/* Begin header - //TYPE/ CLASSIC - //NAME/ MMI_VM_AMR_PAUSE_REQ - //FULL/ - " | | | | | |" - "#@Fdl7# |---->| | | VM_AMR_PAUSE_REQ | #" - //COND/ - "#@Fdl7# VM_AMR_PAUSE_REQ" - End header */ -//ID/ -#define TRL1_MMI_VM_AMR_PAUSE_REQ 227 -//STRUCT/ -typedef struct -{ - UWORD32 header; -//-------------------------------------------------- - -} -T_TR_MMI_VM_AMR_PAUSE_REQ; -/***********************************************************************************************************/ -/* Begin header - //TYPE/ CLASSIC - //NAME/ MMI_VM_AMR_RESUME_REQ - //FULL/ - " | | | | | |" - "#@Fdl7# |---->| | | VM_AMR_RESUME_REQ | " - //COND/ - "#@Fdl7# VM_AMR_RESUME_REQ" - End header */ -//ID/ -#define TRL1_MMI_VM_AMR_RESUME_REQ 228 -//STRUCT/ -typedef struct -{ - UWORD32 header; -//-------------------------------------------------- -// UWORD8 session_id; -} -T_TR_MMI_VM_AMR_RESUME_REQ; -/***********************************************************************************************************/ -/* Begin header - //TYPE/ CLASSIC - //NAME/ MMI_VM_AMR_PAUSE_CON - //FULL/ - " | | | | | |" - "#@Fdl7# |---->| | | VM_AMR_PAUSE_CON |" - //COND/ - "#@Fdl7# VM_AMR_PAUSE_CON" - End header */ -//ID/ -#define TRL1_MMI_VM_AMR_PAUSE_CON 229 -//STRUCT/ -typedef struct -{ - UWORD32 header; -//-------------------------------------------------- - } -T_TR_MMI_VM_AMR_PAUSE_CON; -/***********************************************************************************************************/ -/* Begin header - //TYPE/ CLASSIC - //NAME/ MMI_VM_AMR_RESUME_CON - //FULL/ - " | | | | | |" - "#@Fdl7# |---->| | | VM_AMR_RESUME_CON |" - //COND/ - "#@Fdl7# VM_AMR_RESUME_CON" - End header */ -//ID/ -#define TRL1_MMI_VM_AMR_RESUME_CON 230 -//STRUCT/ -typedef struct -{ - UWORD32 header; -//-------------------------------------------------- -} -T_TR_MMI_VM_AMR_RESUME_CON; - /***********************************************************************************************************/ /* Begin header @@ -5981,11 +5596,6 @@ UWORD32 header; //-------------------------------------------------- WORD16 toa_shift; -#if (TOA_ALGO == 2) - UWORD16 toa_frames_counter; - UWORD16 toa_accumul_counter; - UWORD16 toa_accumul_value; -#endif } T_TR_NEW_TOA; @@ -6059,7 +5669,6 @@ #define BIG_SLEEP_DUE_TO_SLEEP_MODE 5 // deep sleep is forbiden by the sleep mode enabled #define BIG_SLEEP_DUE_TO_DSP_TRACES 6 // deep sleep is forbiden by the DSP #define BIG_SLEEP_DUE_TO_BLUETOOTH 7 // deep sleep is forbiden by the Bluetooth module -#define BIG_SLEEP_DUE_TO_CAMERA 8 // deep sleep is forbiden by the camera /***********************************************************************************************************/ /* Begin header @@ -6467,132 +6076,6 @@ } T_TR_L1C_STOP_DEDICATED_DONE; -#if (L1_VOCODER_IF_CHANGE == 1) -/***********************************************************************************************************/ -/* Begin header - //TYPE/ CLASSIC - //NAME/ MMI_TCH_VOCODER_CFG_REQ - //FULL/ - " | | | | | |" - "#@Fdl7# |---->| | | MMI_TCH_VOCODER_CFG_REQ |" - //COND/ - "#@Fdl7# MMI_TCH_VOCODER_CFG_REQ" - End header */ -//ID/ -#define TRL1_MMI_TCH_VOCODER_CFG_REQ 220 -//STRUCT/ -typedef struct -{ - UWORD32 header; -} -T_TR_MMI_TCH_VOCODER_CFG_REQ; - -/***********************************************************************************************************/ -/* Begin header - //TYPE/ CLASSIC - //NAME/ MMI_TCH_VOCODER_CFG_CON - //FULL/ - " | | | | | |" - "#@Fdl7# | |<-| | MMI_TCH_VOCODER_CFG_CON |" - //COND/ - "#@Fdl7# MMI_TCH_VOCODER_CFG_CON" - End header */ -//ID/ -#define TRL1_MMI_TCH_VOCODER_CFG_CON 221 -//STRUCT/ -typedef struct -{ - UWORD32 header; -} -T_TR_MMI_TCH_VOCODER_CFG_CON; - -/***********************************************************************************************************/ -/* Begin header - //TYPE/ CLASSIC - //NAME/ L1_VOCODER_CFG_ENABLE_CON - //FULL/ - " | | | | | |" - "#@Fdl7# | | |<-| | L1_VOCODER_CFG_ENABLE_CON |" - //COND/ - "#@Fdl7# L1_VOCODER_CFG_ENABLE_CON" - End header */ -//ID/ -#define TRL1_L1_VOCODER_CFG_ENABLE_CON 222 -//STRUCT/ -typedef struct -{ - UWORD32 header; -} -T_TR_L1_VOCODER_CFG_ENABLE_CON; - -/***********************************************************************************************************/ -/* Begin header - //TYPE/ CLASSIC - //NAME/ L1_VOCODER_CFG_DISABLE_CON - //FULL/ - " | | | | | |" - "#@Fdl7# | | |<-| | L1_VOCODER_CFG_DISABLE_CON |" - //COND/ - "#@Fdl7# L1_VOCODER_CFG_DISABLE_CON" - End header */ -//ID/ -#define TRL1_L1_VOCODER_CFG_DISABLE_CON 223 -//STRUCT/ -typedef struct -{ - UWORD32 header; -} -T_TR_L1_VOCODER_CFG_DISABLE_CON; -#endif - -/***********************************************************************************************************/ -/* Begin header - //TYPE/ CLASSIC - //NAME/ SAIC Debug - //FULL/ - " | | | | | |----------------------------------------------------------------------------------------------------------------" - "#@Fdl7# | | | O | SAIC | SWH_flag: #@1d#" - //COND/ - "#@Fdl7# New TOA" - End header */ -//ID/ -#define TRL1_SAIC_DEBUG 224 -//STRUCT/ -typedef struct -{ - UWORD32 header; -//-------------------------------------------------- - UWORD32 SWH_flag; - UWORD32 SAIC_flag; -} -T_TR_SAIC_DEBUG; - - -#define TRL1_BURST_PARAM 225 -//STRUCT/ -typedef struct -{ - UWORD32 header; -//-------------------------------------------------- - WORD16 angle; - UWORD16 snr; - WORD16 afc; - UWORD16 pm; - UWORD16 toa; - UWORD8 task; - UWORD8 input_level; -} -T_TR_BURST_PARAM; - -//NAVC - -#define TRL1_L1_NAVC 226 -typedef struct -{ - UWORD32 status; - UWORD32 energy_level; -} -T_TR_NAVC_PARAM; /***********************************************************************************************************/ /* L1 RTT */ @@ -7198,21 +6681,9 @@ T_TR_MMI_VM_AMR_RECORD_START_CON cell214; T_TR_MMI_VM_AMR_RECORD_STOP_REQ cell215; T_TR_MMI_VM_AMR_RECORD_STOP_CON cell216; - T_TR_MMI_VM_AMR_PAUSE_REQ cell227; - T_TR_MMI_VM_AMR_RESUME_REQ cell228; - T_TR_MMI_VM_AMR_PAUSE_CON cell229; - T_TR_MMI_VM_AMR_RESUME_CON cell230; T_TR_MPHC_NCELL_LIST_SYNC_REQ cell217; T_TR_MPHC_STOP_DEDICATED_CON cell218; T_TR_L1C_STOP_DEDICATED_DONE cell219; - #if (L1_VOCODER_IF_CHANGE == 1) - T_TR_MMI_TCH_VOCODER_CFG_REQ cell220; - T_TR_MMI_TCH_VOCODER_CFG_CON cell221; - T_TR_L1_VOCODER_CFG_ENABLE_CON cell222; - T_TR_L1_VOCODER_CFG_DISABLE_CON cell223; - #endif - T_TR_SAIC_DEBUG cell224; - T_TR_BURST_PARAM cell225; // RTT cells T_RTTL1_FN rttcell1; @@ -7239,15 +6710,4 @@ /************************************/ #include "l1_rtt_macro.h" -#if (L1_FF_MULTIBAND == 1) -#if ( (TRACE_TYPE == 1) || (TRACE_TYPE==4) ) -#define L1_MULTIBAND_TRACE_PARAMS l1_multiband_trace_params -#elif (TRACE_TYPE == 5) -#define L1_MULTIBAND_TRACE_PARAMS l1_multiband_trace_params_simu #endif -#define MULTIBAND_PHYSICAL_BAND_TRACE_ID 0 -#define MULTIBAND_ERROR_TRACE_ID 1 -#endif /*if (L1_FF_MULTIBAND == 1)*/ - - -#endif
--- a/L1/include/l1_types.h Thu Jun 09 00:19:28 2016 +0000 +++ b/L1/include/l1_types.h Thu Jun 09 00:45:00 2016 +0000 @@ -10,22 +10,14 @@ //-------------------------------------- // Basic DATA types used along L1 code. //-------------------------------------- - -#ifndef __L1_TYPES_H__ - #define __L1_TYPES_H__ - #if !defined (BOOL_FLAG) #define BOOL_FLAG typedef unsigned char BOOL; -#endif /* #if !defined (BOOL_FLAG) */ +#endif -// FreeCalypso change -#if 1 //(OP_L1_STANDALONE == 1) - - + #if !defined (NUCLEUS) && !defined CHAR_FLAG #define CHAR_FLAG - typedef char CHAR; #endif @@ -38,17 +30,9 @@ typedef unsigned long UWORD32; typedef long WORD32; //-------------------------------------- - -#else - #include "global_types.h" -#endif /* #if (OP_L1_STANDALONE == 1) */ +typedef volatile UWORD16 API; +typedef volatile WORD16 API_SIGNED; - - -typedef volatile UWORD16 API; -typedef volatile WORD16 API_SIGNED; -#endif /* #ifndef __L1_TYPES_H__ */ -
--- a/L1/include/l1_varex.h Thu Jun 09 00:19:28 2016 +0000 +++ b/L1/include/l1_varex.h Thu Jun 09 00:45:00 2016 +0000 @@ -3,60 +3,54 @@ * L1_VAREX.H * * Filename l1_varex.h - * Copyright 2003 (C) Texas Instruments + * Copyright 2003 (C) Texas Instruments * ************* Revision Controle System Header *************/ #ifdef L1_ASYNC_C - T_L1S_GLOBAL l1s __attribute__ ((section (".l1s_global"))); +#if (LONG_JUMP == 3) + #pragma DATA_SECTION(l1s,".l1s_global") + #pragma DATA_SECTION(l1s_dsp_com,".l1s_global") + #pragma DATA_SECTION(l1a_l1s_com,".l1s_global") + #pragma DATA_SECTION(l1s_tpu_com,".l1s_global") + #pragma DATA_SECTION(l1_config,".l1s_global") +#endif + + T_L1S_GLOBAL l1s; T_L1A_GLOBAL l1a; - T_L1A_L1S_COM l1a_l1s_com __attribute__ ((section (".l1s_global"))); - T_L1S_DSP_COM l1s_dsp_com __attribute__ ((section (".l1s_global"))); - T_L1S_TPU_COM l1s_tpu_com __attribute__ ((section (".l1s_global"))); -#if (L1_MP3 == 1) || (L1_MIDI == 1 || (L1_AAC == 1) || (FF_L1_IT_DSP_USF == 1) || (FF_L1_IT_DSP_DTX == 1) || (L1_DYN_DSP_DWNLD == 1)) // equivalent to an API_HISR flag - T_L1A_API_HISR_COM l1a_apihisr_com __attribute__ ((section (".l1s_global"))); -#endif -#if (L1_MP3 == 1) || (L1_MIDI == 1) || (L1_AAC == 1) || (L1_DYN_DSP_DWNLD == 1) - T_L1_API_HISR l1_apihisr __attribute__ ((section (".l1s_global"))); -#endif -#if (L1_MIDI == 1) - T_MIDIPARSER_APIHISR_COM midiparser_apihisr_com - __attribute__ ((section (".l1s_global"))); + T_L1A_L1S_COM l1a_l1s_com; + T_L1S_DSP_COM l1s_dsp_com; + T_L1S_TPU_COM l1s_tpu_com; + + #if (L1_DYN_DSP_DWNLD == 1) // equivalent to an API_HISR flag + T_L1_API_HISR l1_apihisr; + T_L1A_API_HISR_COM l1a_apihisr_com; #endif // variables for L1 configuration - T_L1_CONFIG l1_config __attribute__ ((section (".l1s_global"))); -#else + T_L1_CONFIG l1_config; + +#else // L1_ASYNC_C + extern T_L1S_GLOBAL l1s; extern T_L1A_GLOBAL l1a; extern T_L1A_L1S_COM l1a_l1s_com; extern T_L1S_DSP_COM l1s_dsp_com; extern T_L1S_TPU_COM l1s_tpu_com; -#if (L1_MP3 == 1) || (L1_MIDI == 1) || (L1_AAC == 1) || (FF_L1_IT_DSP_USF == 1) || (FF_L1_IT_DSP_DTX == 1) || (L1_DYN_DSP_DWNLD == 1) // equivalent to an API_HISR flag - extern T_L1A_API_HISR_COM l1a_apihisr_com; -#endif -#if (L1_MP3 == 1) || (L1_MIDI == 1) || (L1_AAC == 1) || (L1_DYN_DSP_DWNLD == 1) + + #if (L1_DYN_DSP_DWNLD == 1) // equivalent to an API_HISR flag extern T_L1_API_HISR l1_apihisr; -#endif -#if (L1_MIDI == 1) - extern T_MIDIPARSER_APIHISR_COM midiparser_apihisr_com; + extern T_L1A_API_HISR_COM l1a_apihisr_com; #endif // variables for L1 configuration extern T_L1_CONFIG l1_config; #endif -#if (L1_FF_MULTIBAND == 1) -// extern T_L1_MULTIBAND_POWER_CLASS multiband_power_class_array[]; -// extern T_MULTIBAND_CONVERSION_DATA multiband_conversion_data[]; -// extern T_MULTIBAND_RF_DATA multiband_rf_data[]; - extern const T_MULTIBAND_RF multiband_rf[RF_NB_SUPPORTED_BANDS + 1]; -#endif /*if(L1_FF_MULTIBAND == 1)*/ - - extern const UWORD8 ramBootCode[]; // dummy DSP code for boot. +
--- a/L1/include/l1_ver.h Thu Jun 09 00:19:28 2016 +0000 +++ b/L1/include/l1_ver.h Thu Jun 09 00:45:00 2016 +0000 @@ -3,7 +3,7 @@ * L1_VER.H * * Filename l1_ver.h - * Copyright 2003 (C) Texas Instruments + * Copyright 2003 (C) Texas Instruments * ************* Revision Controle System Header *************/ @@ -261,11 +261,10 @@ //#define SOFTWAREVERSION 0x1426L // CHG03059, CHG03306, CHG3319, CHG3330, BUG03331, CHG03344, CHG3345, CHG3346, CHG03347, REQ03349, CHG03352 //#define SOFTWAREVERSION 0x1427L // CHG03382, CHG03394, BUG03395, BUG03403, CHG03405, REQ03406 //#define SOFTWAREVERSION 0x1428L // CHG03415, CHG03402, CHG03411, REQ03414, REQ03396, REQ03410, BUG03401, BUG03312, BUG03372. -//#define SOFTWAREVERSION 0x1429L // CHG03417 +//#define SOFTWAREVERSION 0x1429L // CHG03417 //#define SOFTWAREVERSION 0x1430L // CHG03425, BUG03371, REQ03429, REQ03431, CHG03432, CHG03434 //#define SOFTWAREVERSION 0x1431L // CHG2438, BUG2783, BUG3142, BUG3351, BUG3358, BUG3370, BUG3377, BUG3378, BUG3407, BUG3424, CHG3456, BUG3457, CHG3460, BUG3461 -//#define SOFTWAREVERSION 0x1432L // CHG3472 -//#define SOFTWAREVERSION 0x1433L // BUG03423, REQ03464, REQ03465, REQ03466, CHG03467, REQ03468, BUG03469, BUG03471, REQ03477, BUG03483, BUG03484, CHG03485, BUG03486 +//#define SOFTWAREVERSION 0x1432L // CHG3472 //#define DEVELPMTVERSION 0x0001L //#define DEVELPMTVERSION 0x0002L // Corrected TI_4, TI_7, TI_12 @@ -307,83 +306,37 @@ ///////////////////////////////////// // added for new naming conventions -#define PROGRAM_RELEASE_VERSION 0x3200 // TCS 3.0.0 - No protocol stack release done +//#define PROGRAM_RELEASE_VERSION 0x2112 +//#define PROGRAM_RELEASE_VERSION 0x2118 // release 1446 is for TCS2.1.1.8 +//#define PROGRAM_RELEASE_VERSION 0x2119 // release 1448 is for TCS2.1.1.9 +//#define PROGRAM_RELEASE_VERSION 0x211A // release 1450 is for TCS2.1.1.10 +//#define PROGRAM_RELEASE_VERSION 0x211C // release 1451 is for TCS2.1.1.12 -> switching to dynamic download +#define PROGRAM_RELEASE_VERSION 0x211E // release 1452 is for TCS2.1.1.14 -//#define INTERNAL_VERSION 0x1 // First version on ClearCase -//#define INTERNAL_VERSION 0x1 // 1434: L1_MCU-ENH-16756, L1_MCU-ENH-16380, L1_ENV-ENH-16274, - // L1_DRI-ENH-16267, L1_TES-SPR-16117, L1_ENV-ENH-16058, - // L1_MCU-ENH-16034, L1_TES-ENH-16026, L1_DRI-SPR-16005, - // L1_ENV-ENH-15885, L1_ENV-ENH-15884, L1_DRI-ENH-15883, - // L1_MCU-ENH-15873, L1_MCU-SPR-15836, L1_ENV-ENH-15789, - // FLUID-ENH-15702, L1_MCU-SPR-15513, L1_MCU-ENH-15506, - // L1_MCU-CHG-13001 -//#define INTERNAL_VERSION 0x2 // 1434: L1_MCU-ENH-16599, L1_MCU-ENH-16602, L1_MCU-ENH-16593, - // L1_MCU-ENH-17204, L1_MCU-ENH-17209, L1_MCU-ENH-17210, - // L1_MCU-ENH-17324, L1_MCU-ENH-16697 -//#define INTERNAL_VERSION 0x0 // 1435: L1_MCU-ENH-17455, L1_MCU-ENH-17456 -//#define INTERNAL_VERSION 0x1 // 1435: G23M/L1_MCU-FIX-16046, G23M/L1_ALL-FIX-16114, - // G23M/L1_MCU-FIX-17639, G23M/L1_MCU-SPR-17646, - // G23M/L1_MCU-FIX-17664, G23M/L1_MCU-ENH-17683, - // G23M/L1_MCU-SPR-17763, G23M/L1_MCU-SPR-17515, - // G23M/L1_MCU-ENH-18032 - -//#define INTERNAL_VERSION 0x0 -//#define INTERNAL_VERSION 0x1 -//#define INTERNAL_VERSION 0x2 // 1436: 19177,19167,18866,18012,17976,16726,15739,15494,18202,18727,18839,18799,19365 -//#define INTERNAL_VERSION 0x0 // 1437: 18109, 18101, 18063, 17979, 17865, 17769, 16917, 18233, - // 16015, 19341, 19599, 18938, 19570, 19092, 19089, 19708, - // 17684, 19633, 19741, 19752, 19818, 19816, 19823, 19836, - // 19144, 19915, 20091 -//#define INTERNAL_VERSION 0x1 // 1438: L1_MCU_ENH-17504 - // 1437: L1_MCU-SPR-20357, L1_MCU-FIX-20354 -//#define INTERNAL_VERSION 0x2 // 1438: 18136, 18202, 18482, 19178, 19247, 19368 - // 19585, 19639, 19901, 20130, 20187, 20226 - // 20509, 20603, 20739 +/* Internal release numbering */ +//#define INTERNAL_VERSION 0x1 // First version on ClearCase +//#define INTERNAL_VERSION 0x2 // Second subversion on mainline +//#define INTERNAL_VERSION 0x3 // Second subversion on mainline +#define INTERNAL_VERSION 0x0 // Official release -//#define INTERNAL_VERSION 0x1 // 1439: 17561, 17563, 18861, 18897, 18931, 19119, 19151, 19168, 19539 - // 19965, 20269, 20419, 20355, 20665, 20708, 20776, 20781, 21075 - // 21105, 20959, 20902, 20762, 20965, 21280. - // 1440: 20430, 20616, 20657, 20963, 21154, 21249, 21671, 22029, 22102 - // 22131, 22218, 22236, 22358, 22361, 22549 - // 1441: 27674, 27682, 28060, 27756, 27759, 27761, 27762, 27763, 27765, - // 27766, 27769, 27770, 27771, 27772, 24206, 24207, 24208, 24209, - // 29392, 24211, 24212, 24213, 27775, 27776, 24214, 27777, 27778, - // 27779, 24215, 27780, 27781, 24216, 24217, 24218, 29036, 28815, - // 28914, 29038, 28999, 29001, 29003, 29005, 29006, 29007, 29008, - // 29009, 29010, 29014, 29021, 29022, 29023, 29024, 29026, 29027, - // 29028, 29029, 29030, 29032, 29033, 29034, 29037, 29039, 29040, - // 29059, 29060, 29061, 29062, 29063, 29064, 29065, 29066, 29067, - // 29068, 29069, 29070, 29071, 29072, 29073, 29074, 29075, 29076, - // 29079, 29080, 29081, 29082, 29083, 29084, 29085, 29086, 29087, - // 29088, 29089, 29090, 29091, 29092, 29405, 27356, 28417, 26720, - // 24992, 24988, 24401, 24138, 24143, 29406, 23943, 29407, 29408, - // 29409, 29410, 26294, 29415, 29416, 29417, 29418, 28412, 27362, - // 29419, 28420, 28421, 29420, 29423, 29424, 29425, 29426, 29429, - // 29430, 27812, 29431, 29433, 29434, 29436, 29437, 29438, 29440, - // 29442, 29443, 29444, 29445, 29959 - -#define INTERNAL_VERSION 0x1 -//#define INTERNAL_VERSION 0x2 - - -//#define OFFICIAL_VERSION 0x1433 -//#define OFFICIAL_VERSION 0x1434 // L1_DSP-ENH-15589, L1_DSP-ENH-15590, L1_GPR-FIX-12737 -//#define OFFICIAL_VERSION 0x1435 -//#define OFFICIAL_VERSION 0x1436 -//#define OFFICIAL_VERSION 0x1437 -//#define OFFICIAL_VERSION 0x1438 -//#define OFFICIAL_VERSION 0x1439 -//#define OFFICIAL_VERSION 0x1440 -//#define OFFICIAL_VERSION 0x1441 -//#define OFFICIAL_VERSION 0x1446 -//#define OFFICIAL_VERSION 0xA447 -//#define OFFICIAL_VERSION 0xA448 -//#define OFFICIAL_VERSION 0xA449 -//#define OFFICIAL_VERSION 0xA450 -//#define OFFICIAL_VERSION 0xA451 -//#define OFFICIAL_VERSION 0xA452 -//L1 SW version -#define OFFICIAL_VERSION 0xA460 -#define MAINTENANCE_VERSION 0x6011 -#define L1_DRP_COMPAT_MAJOR_VER (0x008A) -#define L1_DRP_COMPAT_MINOR_VER (0x0003) +/* Official external release numbering */ +//#define OFFICIAL_VERSION 0x1432 +//#define OFFICIAL_VERSION 0x1433 +//#define OFFICIAL_VERSION 0x1434 +//#define OFFICIAL_VERSION 0x1435 +//#define OFFICIAL_VERSION 0x1436 +//#define OFFICIAL_VERSION 0x1438 +//#define OFFICIAL_VERSION 0x1439 +//#define OFFICIAL_VERSION 0x1440 +//#define OFFICIAL_VERSION 0x1441 +//#define OFFICIAL_VERSION 0x1442 +//#define OFFICIAL_VERSION 0x1444 +//#define OFFICIAL_VERSION 0x1445 +//#define OFFICIAL_VERSION 0x1446 +//#define OFFICIAL_VERSION 0x1447 +//#define OFFICIAL_VERSION 0x1448 +//#define OFFICIAL_VERSION 0x1449 +//#define OFFICIAL_VERSION 0x1450 +//#define OFFICIAL_VERSION 0x1451 +//#define OFFICIAL_VERSION 0x1453 +#define OFFICIAL_VERSION 0x1454