FreeCalypso > hg > freecalypso-docs

annotate Calypso-test-reset @ 102:49be28a15768

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USB-ID-assignments: new official document location Our master document for assignment of USB IDs that have been allocated to us by FTDI previously resided in doc/USB-IDs in freecalypso-hwlab repository. However, that hw lab hacks repository is not the right place for a long-term official policy document - the present repository is a much better place.
author Mychaela Falconia <falcon@freecalypso.org>
date Mon, 11 Sep 2023 06:32:05 +0000
parents 396d44c543e3
children
Ignore whitespace changes - Everywhere: Within whitespace: At end of lines:
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1 Reset logic and on/off states in the Calypso+Iota chipset
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2 =========================================================
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3
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4 Our beloved Calypso+Iota chipset provides a special reset signal (called
38cc5795d79c Calypso-test-reset article written
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5 nTESTRESET on Leonardo schematics) that is just for testing, development and
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6 debugging, not used at all in the normal life cycle of a phone handset or
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7 modem. This special test reset is triggered when you press the RESET button on
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8 a TI/FreeCalypso development board (D-Sample or FCDEV3B), and it can also be
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9 triggered slightly indirectly through the reset pin on the TI-style JTAG
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10 connector. The way this reset works is very quirky and requires a lot of
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11 explanation, but before one can properly understand this test reset, we first
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12 need to look at the "regular" power-on reset, switch-on and switch-off logic
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13 that works in the absence of nTESTRESET.
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14
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15 Before looking at resets and switch-on and switch-off sequences, we first need
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16 to understand the power domains that are involved. There are two major power
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17 domains of interest: there is the main power domain that is physically powered
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18 off when the mobile device is not in the switched-on state, and there is the
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19 RTC power domain that is powered at all times whenever the battery is physically
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20 present, or perhaps even from a separate backup battery (a tiny coin cell) that
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21 provides RTC power when the main battery is removed. The always-on RTC power
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22 domain allows the real time clock to maintain the time of day while the mobile
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23 is otherwise off (hence the name), and it also provides power to the logic that
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24 allows the rest of the mobile (the main power domain) to be powered on,
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25 initialized, booted, run and eventually switched off again in an orderly manner.
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26
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27 All reset and on/off logic in our chipset happens in the VRPC (Voltage Reference
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28 and Power Control) block in the Iota chip; all of Calypso and the rest of Iota
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29 are fully subservient to this VRPC block. It is crucial to understand the
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30 difference between powering on and off vs. switching on and off: in the
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31 terminology that is established in TI's chip datasheets and application notes,
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32 powering on means physically providing battery power to the chipset (inserting
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33 the battery into a phone that had it removed, or connecting a VBAT power supply
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34 to the orange power input connector on one of our development boards), and
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35 powering off means physically removing all battery power, i.e., yanking the
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36 battery out of a phone or disconnecting the power supply from the development
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37 board. In board designs with a backup battery or a provision for one, it is
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38 even more complicated: a power-on happens when either the main battery or a
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39 backup battery becomes present, and a power-off happens when both batteries are
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40 removed, leaving the Iota chipset without any energy source whatsoever. In
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41 contrast, the actions of a user turning her phone on and off are called
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42 switch-on and switch-off, respectively.
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43
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44 The RTC power domain is powered on and receives its power-on reset (POR) on a
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45 power-on event and loses power only on a full power-off (complete loss of all
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46 battery power), whereas the main power domain is powered on and lifted out of
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47 reset only on a switch-on, and powered back down and held in reset on a
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48 switch-off. The Calypso chip receives two reset signals from the Iota (meaning
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49 that each signal is an output from the Iota and an input to the Calypso):
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50 nRESPWON and ON_nOFF. The nRESPWON signal is asserted (active low) only on a
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51 hardware power-on (and also on nTESTRESET as will be explained in due course)
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52 and stays high (inactive) at all other times, whereas ON_nOFF is driven high on
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53 switch-on and low on switch-off. When the ON_nOFF signal is driven low by the
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54 Iota ABB in the switched-off state, all main (non-RTC) logic in the Calypso is
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55 held in reset, and in any case that logic cannot function as the physical power
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56 to it (coming from LDO regulators in the Iota) will typically be turned off.
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57 When the Iota ABB drives ON_nOFF high on switch-on, it does so after the LDO
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58 regulators for the main power domain have been turned on and have had enough
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59 time to stabilize; in the Calypso chip the transition of ON_nOFF from low to
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60 high causes the ARM7 core to boot.
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61
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62 A true power-on reset happens only when all battery power is removed and
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63 reconnected: in simple designs without a backup battery one would need to
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64 remove the main battery or the power supply providing VBAT and also disconnect
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65 anything that may be feeding power into the system through pull-up resistors;
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66 in more complex designs that feature a backup battery, both the main battery
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67 and the backup battery would need to be removed and reconnected in order to
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68 trigger a POR. Such a complete POR would reset the RTC power domain, and on
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69 exit from the POR the VRPC block will be in the switched-off state, with
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70 everything except the RTC powered off and waiting for the user to press the
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71 PWON button.
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72
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73 The green LED on the FCDEV3B indicates the state of the ON_nOFF signal, and
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74 thus allows you to see if the VRPC block is switched on (LED on) or switched
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75 off (LED off). The actual VRPC state machine in the Iota chip is a little more
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76 complicated and has 5 states, not just two (the states are NOBAT, BACKUP, OFF,
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77 ACTIVE and SLEEP), but I am simplifying here - for the complete details, please
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78 see the VRPC description in Iota datasheet TWL3025_SWRS021.pdf, section 4.10
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79 starting on page 40. The transition from OFF to ACTIVE (switch-on event)
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80 happens whenever the PWON button is pressed or charging voltage is applied (on
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81 hardware that has charging circuits), whereas commanding a switch-off (going
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82 back to OFF) requires having Calypso ARM7 firmware establish communication with
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83 the Iota ABB over SPI and send a DEVOFF command. If the Calypso firmware
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84 requests a switch-off when the PWON button is held down (jumper on FCDEV3B) or
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85 when a charging power source is present, the Iota VRPC goes through a switch-off
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86 immediately followed by a switch-on, effecting a very deep kind of reboot.
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87
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88 nTESTRESET enters the picture
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89 =============================
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90
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91 So where does nTESTRESET fit in the just-described architecture of on/off
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92 switching and resets? Contrary to what one might naively think, it is NOT an
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93 externally-triggerable way to simulate a POR, nor is it simply ANDed or ORed
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94 together with some other internal reset signal. Instead as you can see in
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95 Figure 4-8 on page 43 of the TWL3025_SWRS021.pdf datasheet, it is its own
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96 separate and very special path through the VRPC state machine that is never
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97 exercised at all in normal product operation.
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98
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99 When you press the RESET button or trigger a reset through JTAG connector pin 2
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100 (let's call it XDS_RESET), the VRPC state machine will unconditionally leave
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101 whatever state it was in and will be forced into this special nTESTRESET state
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102 that does not occur at any other time. For as long as nTESTRESET is held low,
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103 both reset signals to the Calypso (nRESPWON and ON_nOFF) will be held low as
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104 well, putting the Calypso into a POR-like superdeep reset, but meanwhile the
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105 LDO regulators are fully turned on, not off! While nTESTRESET is held low, the
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106 green LED on the FCDEV3B will be off (ON_nOFF is low), but the regulators are
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107 on, as can be seen on JTAG connector pin 5 where the V-IO rail is brought out.
15
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108 This combination of ON_nOFF low (green LED off) but regulators on happens only
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109 in this special nTESTRESET-held-low state and not at any other time.
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110
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111 When the RESET button and XDS_RESET are both released, causing nTESTRESET to go
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112 back to high, the VRPC state machine goes from the special nTESTRESET state to
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113 the ACTIVE (switched-on) state via a special direct transition that bypasses
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114 the normal checks. Calypso reset inputs nRESPWON and ON_nOFF go from low to
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115 high at the same time (this is the only time when they do it like this), and
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116 the ARM7 core boots.
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117
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118 Thus the test reset triggered via nTESTRESET is not a simple POR-like reset,
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119 instead it is a very special "deep reset, then unconditional power-on and boot"
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120 kind of operation. As a practical matter, it does its intended job of giving
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121 developers an unconditional and unstoppable way to take control of the chipset
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122 when the ARM7 processor and its code execution are in a runaway state: in the
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123 Calypso+Iota on/off architecture, the most "kosher" way to cleanly reset the
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parents:
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124 system would be a switch-off followed by a switch-on, but a normal switch-off
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
125 is a quite complex operation that has to be performed by ARM7 firmware, and it
38cc5795d79c Calypso-test-reset article written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
126 is thus unavailable when the processor executes something other than perfectly
38cc5795d79c Calypso-test-reset article written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
127 good firmware code with clean soft-power-off functionality. The test reset
38cc5795d79c Calypso-test-reset article written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
128 mechanism provides a solution, although it is a solution that may be quite
38cc5795d79c Calypso-test-reset article written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
129 difficult to understand at first.
38cc5795d79c Calypso-test-reset article written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
130
38cc5795d79c Calypso-test-reset article written
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diff changeset
131 It is also important to note that nTESTRESET acts the same way and puts the
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parents:
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132 chipset into the exact same state regardless of *all* prior state, as in not
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parents:
diff changeset
133 only prior sw state, but also prior hw state: in particular, it works exactly
38cc5795d79c Calypso-test-reset article written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
134 the same way whether the chipset was switched on or switched off prior to
38cc5795d79c Calypso-test-reset article written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
135 nTESTRESET assertion. If the system was previously switched on, running some
38cc5795d79c Calypso-test-reset article written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
136 code that hung or become uncontrollable, nTESTRESET can be thought of as acting
38cc5795d79c Calypso-test-reset article written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
137 mostly like a typical processor reset that most software developers are used to,
38cc5795d79c Calypso-test-reset article written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
138 but if the system was previously switched off, nTESTRESET acts like a different
38cc5795d79c Calypso-test-reset article written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
139 kind of "turn on" command, producing a switch-on that is distinguishable from
38cc5795d79c Calypso-test-reset article written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
140 all other switch-on causes like PWON and charger-plug.
38cc5795d79c Calypso-test-reset article written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
141
38cc5795d79c Calypso-test-reset article written
Mychaela Falconia <falcon@freecalypso.org>
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diff changeset
142 Lack of debouncing
38cc5795d79c Calypso-test-reset article written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
143 ==================
38cc5795d79c Calypso-test-reset article written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
144
38cc5795d79c Calypso-test-reset article written
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diff changeset
145 It is important to note that there is no debouncing circuit for nTESTRESET
38cc5795d79c Calypso-test-reset article written
Mychaela Falconia <falcon@freecalypso.org>
parents:
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146 inside the Iota chip, like there is for the regular PWON button. Thus shorting
38cc5795d79c Calypso-test-reset article written
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parents:
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147 nTESTRESET to GND directly with a finger-actuated pushbutton switch is not
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Mychaela Falconia <falcon@freecalypso.org>
parents:
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148 particularly good, although TI's Leonardo schematics depict just such an
38cc5795d79c Calypso-test-reset article written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
149 arrangement, and it works OK on the FCDEV3B in practice.
38cc5795d79c Calypso-test-reset article written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
150
38cc5795d79c Calypso-test-reset article written
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diff changeset
151 The entity that drives nTESTRESET to the Calypso+Iota system takes full
38cc5795d79c Calypso-test-reset article written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
152 responsibility for ensuring proper timing. The reset which is propagated from
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
153 nTESTRESET to nRESPWON and ON_nOFF needs to have a certain duration in order to
38cc5795d79c Calypso-test-reset article written
Mychaela Falconia <falcon@freecalypso.org>
parents:
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154 reset all logic properly, and there is nothing in the chipset itself to assure
38cc5795d79c Calypso-test-reset article written
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parents:
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155 such, unlike what happens on normal switch-on sequences - instead it is the
38cc5795d79c Calypso-test-reset article written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
156 responsibility of the nTESTRESET driving source. The exact timing requirements
38cc5795d79c Calypso-test-reset article written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
157 are not stated anywhere (at least none that we could find), but if you are
38cc5795d79c Calypso-test-reset article written
Mychaela Falconia <falcon@freecalypso.org>
parents:
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158 driving nTESTRESET from a programmatic source (presumably via the XDS_RESET
38cc5795d79c Calypso-test-reset article written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
159 signal path described below), I would give it a 50 ms pulse.
38cc5795d79c Calypso-test-reset article written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
160
38cc5795d79c Calypso-test-reset article written
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parents:
diff changeset
161 When nTESTRESET is shorted to GND with a finger-actuated pushbutton switch, one
38cc5795d79c Calypso-test-reset article written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
162 needs to watch out for contact bounce. If the dry contact switch does a lot of
38cc5795d79c Calypso-test-reset article written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
163 make-break bounce, that make-break noise will translate directly into Calypso
38cc5795d79c Calypso-test-reset article written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
164 and Iota resets being asserted and negated just as rapidly, which is certainly
38cc5795d79c Calypso-test-reset article written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
165 not clean. The final release from reset is the most important part though: if
38cc5795d79c Calypso-test-reset article written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
166 the system is put through a bunch of erratic resets as a result of contact
38cc5795d79c Calypso-test-reset article written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
167 bounce on the initial RESET button press, there should be no problem if there
38cc5795d79c Calypso-test-reset article written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
168 is a long solid reset at the end, with a clean release from it. But if the
38cc5795d79c Calypso-test-reset article written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
169 release from reset is also accompanied by contact bounce with make-break events
38cc5795d79c Calypso-test-reset article written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
170 on the order of microseconds, then the chipset may enter garbage state by way
38cc5795d79c Calypso-test-reset article written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
171 of an improperly timed reset. The nTESTRESET signal was clearly designed to be
38cc5795d79c Calypso-test-reset article written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
172 driven by development systems that can produce controlled timing, not by
38cc5795d79c Calypso-test-reset article written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
173 bounce-prone electromechanical switches driven by bounce-prone human fingers.
38cc5795d79c Calypso-test-reset article written
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parents:
diff changeset
174
38cc5795d79c Calypso-test-reset article written
Mychaela Falconia <falcon@freecalypso.org>
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diff changeset
175 nTESTRESET vs. XDS_RESET
38cc5795d79c Calypso-test-reset article written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
176 ========================
38cc5795d79c Calypso-test-reset article written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
177
38cc5795d79c Calypso-test-reset article written
Mychaela Falconia <falcon@freecalypso.org>
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diff changeset
178 In its native form the internal nTESTRESET signal is pulled up to a non-logic
38cc5795d79c Calypso-test-reset article written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
179 voltage rail (specifically UPR, which normally follows VBAT in the absence of
38cc5795d79c Calypso-test-reset article written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
180 backup batteries), and it can be shorted or pulled to GND either by pushbutton
38cc5795d79c Calypso-test-reset article written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
181 switches (aside from the contact bounce problem noted above) or by OC/OD
38cc5795d79c Calypso-test-reset article written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
182 drivers. It cannot, however, be driven by any kind of external push-pull
38cc5795d79c Calypso-test-reset article written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
183 driver, and more generally it cannot be connected to any circuit that operates
38cc5795d79c Calypso-test-reset article written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
184 on standard logic voltages like 3.3 V - the VBAT rail will typically be in the
38cc5795d79c Calypso-test-reset article written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
185 3.6 to 4.2 V range, which is too high for external 3.3 V logic.
38cc5795d79c Calypso-test-reset article written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
186
38cc5795d79c Calypso-test-reset article written
Mychaela Falconia <falcon@freecalypso.org>
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diff changeset
187 But TI Back In The Day had a need to drive this test reset from their XDS510
38cc5795d79c Calypso-test-reset article written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
188 and XDS560 "emulator" pods, and the only reset signal those pods put out is the
38cc5795d79c Calypso-test-reset article written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
189 one that was originally intended for JTAG TRST (which does not exist in the
38cc5795d79c Calypso-test-reset article written
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parents:
diff changeset
190 Calypso+Iota chipset), driven with a push-pull driver. TI's solution was to
38cc5795d79c Calypso-test-reset article written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
191 insert a clever transistor circuit between JTAG connector pin 2 (the pin that
38cc5795d79c Calypso-test-reset article written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
192 was originally intended to be TRST) and the internal nTESTRESET signal; this
38cc5795d79c Calypso-test-reset article written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
193 circuit is depicted on the available Leonardo schematics, it has been replicated
38cc5795d79c Calypso-test-reset article written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
194 on our FCDEV3B, and we have every reason to believe that it is the same on TI's
38cc5795d79c Calypso-test-reset article written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
195 D-Sample board as well. The effect of this circuit is that whenever the
38cc5795d79c Calypso-test-reset article written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
196 external XDS_RESET signal is driven low and the internal V-IO rail has power
38cc5795d79c Calypso-test-reset article written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
197 (see below), the internal nTESTRESET signal is driven low (asserted), and
38cc5795d79c Calypso-test-reset article written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
198 whenever the external XDS_RESET signal is either driven high or left alone, the
38cc5795d79c Calypso-test-reset article written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
199 internal nTESTRESET signal is left alone, high from the pull-up to UPR - but
38cc5795d79c Calypso-test-reset article written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
200 the nTESTRESET and XDS_RESET electrical nets are never exposed directly to each
38cc5795d79c Calypso-test-reset article written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
201 other's voltages.
38cc5795d79c Calypso-test-reset article written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
202
38cc5795d79c Calypso-test-reset article written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
203 This clever solution does however have one side effect which is visible to
38cc5795d79c Calypso-test-reset article written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
204 developers working with these boards: the reset signal isolation circuit can
38cc5795d79c Calypso-test-reset article written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
205 only propagate an asserted low from XDS_RESET to nTESTRESET when the V-IO rail
38cc5795d79c Calypso-test-reset article written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
206 has power, i.e., when Iota regulators are turned on - and in the normal
38cc5795d79c Calypso-test-reset article written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
207 switched-off state these regulators are turned off. Thus the operator needs to
38cc5795d79c Calypso-test-reset article written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
208 first cause a switch-on or at least a regulator turn-on by pressing either the
38cc5795d79c Calypso-test-reset article written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
209 PWON button or the RESET button, and once V-IO is on, the external host driving
38cc5795d79c Calypso-test-reset article written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
210 the XDS_RESET signal via the JTAG connector can take over.
38cc5795d79c Calypso-test-reset article written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
211
38cc5795d79c Calypso-test-reset article written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
212 Another unexpected quirk is that XDS_RESET can still sometimes work even though
38cc5795d79c Calypso-test-reset article written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
213 the Iota regulators are off (VRPC in the switched-off state) if some leakage
38cc5795d79c Calypso-test-reset article written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
214 power is being fed into the V-IO rail from UART or JTAG lines through pull-up
38cc5795d79c Calypso-test-reset article written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
215 resistors - but this behaviour should be considered an unfortunate design
38cc5795d79c Calypso-test-reset article written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
216 blemish, not something to be relied on.
38cc5795d79c Calypso-test-reset article written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
217
38cc5795d79c Calypso-test-reset article written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
218 Test reset, then switch-off, then switch-on quirk
38cc5795d79c Calypso-test-reset article written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
219 =================================================
38cc5795d79c Calypso-test-reset article written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
220
38cc5795d79c Calypso-test-reset article written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
221 If you use any version of FreeCalypso host tools earlier than the upcoming
38cc5795d79c Calypso-test-reset article written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
222 fc-host-tools-r11 release with an FCDEV3B, you might have noticed a really odd
38cc5795d79c Calypso-test-reset article written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
223 quirk: if you make an fc-loadtool entry via the RESET button instead of PWON,
38cc5795d79c Calypso-test-reset article written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
224 then exit your loadtool session cleanly, such that the green LED goes out, the
38cc5795d79c Calypso-test-reset article written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
225 board ends up in a weird state - if you then do a subsequent switch-on via PWON,
38cc5795d79c Calypso-test-reset article written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
226 something goes wrong (fc-loadtool entry doesn't work, regular fw also hangs
38cc5795d79c Calypso-test-reset article written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
227 instead of producing rvinterf output) - it seems as though if you have done a
38cc5795d79c Calypso-test-reset article written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
228 RESET once, only another RESET works from then on, and PWON stops working
38cc5795d79c Calypso-test-reset article written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
229 correctly. Yet if you press the RESET button without fc-loadtool and let the
38cc5795d79c Calypso-test-reset article written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
230 regular firmware boot from this nTESTRESET switch-on, and then execute a
38cc5795d79c Calypso-test-reset article written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
231 switch-off through the firmware (AT@POFF, fc-shell poweroff, or press, hold and
38cc5795d79c Calypso-test-reset article written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
232 release the PWON button) the board is powered off in a clean state - subsequent
38cc5795d79c Calypso-test-reset article written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
233 PWON works just fine. What in the world is going on?
38cc5795d79c Calypso-test-reset article written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
234
38cc5795d79c Calypso-test-reset article written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
235 The secret magic was discovered by carefully studying the TCS211 firmware code
38cc5795d79c Calypso-test-reset article written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
236 we've inherited from TI. It turns out that our Iota chip has at least one
38cc5795d79c Calypso-test-reset article written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
237 secret undocumented register (or perhaps many more, who knows) that is not
38cc5795d79c Calypso-test-reset article written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
238 documented in the TWL3025_SWRS021.pdf datasheet, and any Calypso programs (full
38cc5795d79c Calypso-test-reset article written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
239 firmwares or standalone programs like our loadagent) that execute a Iota
38cc5795d79c Calypso-test-reset article written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
240 poweroff (really switch-off) operation need to make a special write to this
38cc5795d79c Calypso-test-reset article written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
241 magic register in order to avoid trouble in the test reset, then switch-off,
38cc5795d79c Calypso-test-reset article written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
242 then switch-on sequence.
38cc5795d79c Calypso-test-reset article written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
243
38cc5795d79c Calypso-test-reset article written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
244 We are calling this undocumented Iota register VRPCAUX (its official name is
38cc5795d79c Calypso-test-reset article written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
245 unknown, but there is a seemingly-corresponding register in TI's newer Syren
38cc5795d79c Calypso-test-reset article written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
246 ABB chip which the firmware calls VRPCAUX, and the name logically fits in terms
38cc5795d79c Calypso-test-reset article written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
247 of the function), and it is accessed via undocumented register page 2.
38cc5795d79c Calypso-test-reset article written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
248 Officially both Iota and Syren ABB chips only have register pages 0 and 1, but
38cc5795d79c Calypso-test-reset article written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
249 it turns out that both chips also have an undocumented page 2 - and in order to
38cc5795d79c Calypso-test-reset article written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
250 access this secret page 2, one first needs to issue a special (also secret)
38cc5795d79c Calypso-test-reset article written
Mychaela Falconia <falcon@freecalypso.org>
parents:
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251 unlock command through yet other registers - whew!
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252
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253 So just *why* do we need to mess around with secret undocumented Iota registers
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254 from our production code? From what we can tell, this VRPCAUX register lives
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255 in the VRPC block in the RTC power domain, and it preserves its state when the
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256 rest of the system is powered down in the switched-off state. Apparently this
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257 register controls some aspects of the switch-on process, and when an nTESTRESET
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258 reset-and-boot sequence is performed, this VRPCAUX register is loaded with a
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259 different configuration than on normal POR. It appears that the "normal" value
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260 of VRPCAUX in the absence of test reset operations is 0x007 (bit meaning unknown
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261 of course when we are dealing with secret undocumented stuff), and this value
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262 is needed for switch-on and possibly other things (sleep entry and exit, ABB
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263 interrupts, who knows) to work correctly. But if we boot via nTESTRESET and
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264 read the secret register, we see 0x2E7 instead - and if we do a normal DEVOFF
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265 command without changing it to 0x007 first, we get into the broken state where
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266 PWON switch-ons don't work. (It is very reassuring though that another
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267 nTESTRESET always works no matter what - so it looks like this debug reset is
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268 truly irrespective of all prior hw state.)
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269
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270 TI's TCS211 firmware has a bit of magic in its boot code path in the ABB_on()
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271 function in the chipsetsw/drivers/drv_core/abb/abb.c module, and it has this
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272 attention-drawing comment:
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273
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274 // Restore the ABB checks and debouncing if start on TESTRESETZ
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275
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276 The code following this comment goes through the gymnastics of enabling access
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277 to register page 2, then writing 0x007 into the register which we've named
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278 VRPCAUX. (That's what it does for Iota; for Syren it also writes a few other
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279 registers also in that same undocumented page 2.) Reproducing these steps in
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280 our target-utils code (loadagent and friends) has resulted in the problem
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281 behaviour going away: now we can enter fc-loadtool via the RESET button, then
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282 exit loadtool (loadagent poweroff command executed on the target), and the
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283 board is powered off cleanly, with both PWON and RESET working for subsequent
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284 switch-ons. Whew!