FreeCalypso > hg > freecalypso-docs
annotate DUART28-PPD-surprise @ 102:49be28a15768
USB-ID-assignments: new official document location
Our master document for assignment of USB IDs that have been allocated
to us by FTDI previously resided in doc/USB-IDs in freecalypso-hwlab
repository. However, that hw lab hacks repository is not the right
place for a long-term official policy document - the present repository
is a much better place.
author | Mychaela Falconia <falcon@freecalypso.org> |
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date | Mon, 11 Sep 2023 06:32:05 +0000 |
parents | 2ac10b2cde4f |
children |
rev | line source |
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1 DUART28 partial power-down surprise behaviour |
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2 ============================================= |
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3 |
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4 FreeCalypso DUART28 adapter was specifically designed to handle partial |
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5 power-down scenarios as gracefully as possible. There are two possible PPD |
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6 scenarios: |
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7 |
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8 1) USB host is connected (USB power present), but the connected Calypso device |
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9 is in the switched-off state in the Iota VRPC sense. This condition occurs all |
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10 the time in standard FreeCalypso workflows. |
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11 |
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12 2) The connected Calypso device is up and running, but there is no USB host |
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13 connected. This scenario is practically relevant only when the Calypso device |
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14 is equipped with LCD and keypad peripherals and runs handset firmware that is |
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15 capable of untethered operation. |
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16 |
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17 As we have learned through experience with Caramel2 boards, PPD scenario 1 |
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18 would be best handled on the Calypso device side by inserting an LVC buffer |
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19 powered from Calypso V-IO into Calypso input signal paths, rather than on the |
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20 USB adapter side. However, for already existing Calypso boards which don't have |
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21 any such LVC buffers, DUART28 provides some improvement over the alternatives: |
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22 current feeding into powered-down Calypso inputs is reduced to 1.27 mA per pin, |
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23 and the outputs from the adapter are 2.8V rather than 3.3V. |
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24 |
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25 For PPD scenario 2 (which matters for Caramel2 in the Luna configuration) we |
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26 were hoping that the combination of LVC input and output buffers on the DUART28 |
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27 side and UART data line pull-up resistors on the Caramel2 side would do the |
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28 trick, and produce the graceful behaviour we were after. Unfortunately though, |
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29 this PPD scenario does not work as well in practice as we hoped for at design |
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30 time. |
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31 |
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32 DUART28 design includes pull-up resistors to the adapter's 2.8V rail in front of |
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33 all 6 LVC input buffers. These pull-up resistors are there to keep these LVC |
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34 inputs from floating (and thus propagating garbage, possibly even rapidly |
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35 oscillating garbage, to FT2232D inputs) in the following scenarios: |
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36 |
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37 1) PPD scenario 1; |
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38 |
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39 2) Even more importantly, partial connection scenarios. DSR input is currently |
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40 expected to be almost always unconnected, as none of our Calypso devices except |
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41 GTM900 feature DSR outputs; RI input is likewise connected only very rarely |
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42 (only available on Caramel2 and requires a separate wire connection), and there |
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43 is no DCD output on FCDEV3B, causing DCD input to be unconnected as well when |
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44 working with FCDEV3B. |
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45 |
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46 However, these pull-up resistors create a nasty surprise in PPD scenario 2: |
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47 current from Calypso outputs flows in the reverse direction through these |
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48 pull-up resistors into the powered-down DUART28 adapter's P_2V8 rail, enough |
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49 power flows into that rail to power up the other LVC buffer serving adapter |
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50 outputs, those outputs drive low because the inputs coming from FT2232D are |
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51 powered-down low, and the inputs to Calypso UARTs become low instead of high. |
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52 Calypso UARTs apparently don't like it when their RxD inputs are continuously |
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53 low (break condition), and all Calypso sleep modes are disabled as the result. |
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54 The lack of sleep becomes visible on Caramel2 with the yellow STATUS LED |
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55 remaining lit continuously, rather than flashing with sleep-wake activity as it |
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56 does in expected normal operation. |
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57 |
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58 What is incredible about this erratic behaviour scenario is how little power it |
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59 takes to turn on the LVC buffer serving adapter outputs. With 3 out of 4 |
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60 Calypso outputs driving high, the maximum total current that can flow through |
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61 the 3 100 kOhm resistors that stand in the way is 84 uA. The voltage measured |
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62 at the P_2V8 circuit node in this condition is about 1.22 V, i.e., out of the |
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63 2.8 V put out by Calypso, about 1.6 V drops across the 100 kOhm resistors (thus |
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64 it seems that only about 16 uA flows through each resistor), and the unlucky |
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65 74LVC541A buffer IC gets powered up with just 48 uA at 1.22 V. In this erratic |
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66 condition, the outputs of this buffer IC drive low strongly enough to overpower |
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67 the 100 kOhm pull-ups on Calypso inputs, and those latter inputs sense low |
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68 instead of high. |
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69 |
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70 Measuring voltages at other circuit nodes in this state, we see that P_5V rests |
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71 at about 0.89 V - we are seeing reverse leakage through the 2.8V LDO regulator, |
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72 from its output to its input. However, P_3V3 (the output of the other LDO |
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73 regulator) rises to no more than 8 mV - thankfully, not enough power comes in |
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74 through these back paths to turn on another separate LDO, and no spurious resets |
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75 are triggered via the 74LVC2G07 boot control circuit. |
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76 |
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77 Possible solutions |
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78 ================== |
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79 |
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80 There are two general approaches we can take: |
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81 |
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82 1) We can create DUART28 V2 with a more complex design for these pull-ups: |
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83 perhaps we can insert diodes somewhere to block the reverse current flow through |
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84 pull-up resistors, or seeing that P_3V3 is not powered on by this erratic back |
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85 feeding, we could add a third separate LDO regulator just for these pull-ups. |
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86 |
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87 2) We can just live with this defect, as it is not particularly serious. |
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88 |
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89 It is worth noting that the erratic behaviour in question occurs ONLY in PPD |
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90 scenario 2, and this PPD scenario is relevant ONLY for Caramel2+Luna setups: |
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91 not for FCDEV3B, and not for Caramel2 used in a modem configuration. Given how |
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92 few FC community members are expected to work with Luna, and given that we have |
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93 a large surplus of unsold DUART28 boards, a simple solution would be to issue |
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94 two DUART28 boards to every community member who works with Luna, keep one board |
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95 unmodified (all 6 input pull-up resistors intact per the original design), and |
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96 modify the other board for Caramel2+Luna configuration. |
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97 |
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98 If a DUART28 adapter board is to be modified specifically for C2+Luna, the |
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99 modification will consist of removing 4 0402 discrete resistors: R11, R12, R14 |
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100 and R16. These are pull-up resistors on RxD, CTS, DCD and RxD2 inputs - these |
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101 4 signals are the ones driven from Caramel2+Luna to DUART28. OTOH, the other |
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102 two pull-up resistors for DSR and RI need to remain: there is no DSR output on |
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103 Caramel2, and Calypso GPIO1 (which could otherwise be RI) is made inaccessible |
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104 by Luna cabling. |
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105 |
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106 A DUART28 adapter board that has been modified in this manner should be used |
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107 only with Caramel2 and not with FCDEV3B. (Connecting FCDEV3B would result in a |
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108 floating LVC buffer input propagating garbage to FT2232D DCD input, which is |
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109 bad.) Furthermore, even with Caramel2 (with or without Luna) certain user |
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110 behaviours will need to be adjusted when using a sans-pull-up DUART28 adapter: |
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111 specifically, all operations with fc-loadtool (flashing), fc-iram (miscellaneous |
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112 run-from-RAM programs) and fc-xram (FFS editor) need to be performed through the |
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113 secondary UART (the one that carries RVTMUX with running firmware), rather than |
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114 the primary UART that carries the main AT command channel. In contrast, the |
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115 ttyUSB device corresponding to the primary UART should only be opened when the |
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116 Calypso+Iota chipset is switched on and the firmware is running. The reason |
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117 for these user guidelines is that when a modified-DUART28 ttyUSB port is opened |
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118 while the Calypso+Iota chipset is switched off, FT2232D inputs will be receiving |
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119 garbage. The primary UART channel has flow control and modem control signals, |
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Mychaela Falconia <falcon@freecalypso.org>
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120 whereas the secondary UART is data leads only - thus the Linux host will see |
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121 less bogosity on the latter. |