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FCDEV3B-repackaging: minor grammar fixes
author Mychaela Falconia <falcon@freecalypso.org>
date Wed, 10 Oct 2018 16:33:11 +0000
parents 020df28341d0
children 1dbc8c5d9698
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020df28341d0 FCDEV3B-repackaging article written
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1 Repackaging FreeCalypso modem into different physical form factors
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2 ==================================================================
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3
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4 As of this writing, our FreeCalypso Triband Modem Solution has reached the
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5 status of a finished product: it is no longer experimental or developmental,
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6 it is now fully fit for operational use on live public GSM networks in end user
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7 applications that need a standards-compliant GSM+GPRS modem. However, at the
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8 present moment it is only available in the physical form factor of a development
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9 board (FCDEV3B) that was originally designed to serve as a software/firmware
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10 development platform, and as such it is not ideally suited for use as an end
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11 product. For end use applications it would be highly desirable to take our
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12 proven FC Triband Modem Solution (FC-TMS) as realized on the FCDEV3B and
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13 repackage it into other physical form factors. This repackaging can be done
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14 in two ways:
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15
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16 Approach 1 (strongly preferred): the party who desires to have our FC-TMS in a
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17 particular form factor gets in touch with FreeCalypso Central, engages in a
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18 discussion with us to arrive at the new form factor to be implemented (it needs
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19 to satisfy your requirements and be feasible for us to implement), then funds
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20 the cost of PCB layout labor to turn the new form factor modem into reality.
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21 More specifically, we would do the design at the schematics+BOM level while the
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22 the PCB layout step would have to be outsourced at cost.
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23
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24 Approach 2 (NOT preferred, but can sometimes be agreed to in limited cases):
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25 someone else does the repackaging work under their own control.
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26
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27 In the case of Approach 1 the new modem product will always be guaranteed to
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28 work flawlessly and be fully compatible with our FreeCalypso sw and fw
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29 architecture because in this case the hardware design is personally supervised
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30 by the Mother of FreeCalypso and must receive her approval prior to being
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31 released to layout and then to fabrication. In the case of Approach 2 this
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32 assurance is lacking. This document provides some technical guidelines that
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33 MUST be followed in order for a new modem hw product to stand a chance at being
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34 compatible with FreeCalypso; anyone who follows Approach 2 against our
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35 recommendation but still wishes to have a chance at receiving support from us
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36 MUST follow these design guidelines.
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37
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38 LEGAL NOTICE: Following these technical guidelines does NOT by itself grant you
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39 a license to use our FreeCalypso trademark on your hardware products; this
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40 trademark is personally owned by Mychaela N. Falconia and only she has the
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41 authority to license its use at her sole discretion. Similarly our agreement
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42 with GSMA does NOT allow us to sublet any part of our IMEI number range to any
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43 other parties; any IMEI number ranges that may be allocated by GSMA to
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44 FreeCalypso products may ONLY be used for those products that are physically
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45 produced by Falconia Partners LLC from start to finish and not any others.
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46
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47 Basic technical guidelines
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48 ==========================
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49
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50 The purpose of these guidelines is to make it possible for the same firmware
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51 build configuration to support both our existing FCDEV3B and various
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52 repackagings of the underlying core modem solution (FC-TMS), i.e., to have the
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53 same official FC Magnetite firmware builds for target fcdev3b run not only on
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54 the original development board, but on all physical repackagings of the same
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55 core modem solution. To make such firmware reuse possible, the following
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56 hardware design constraints MUST be followed:
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57
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58 * The flash+RAM chip must be the same Spansion S71PL129NC0HFW4B as used on our
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59 FCDEV3B, and it must be wired the same way: first flash chip select on Calypso
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60 nCS0, RAM on nCS1, second flash chip select on nCS2. The flash reset line
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61 needs to be wired the same way as on FCDEV3B V2, otherwise Calypso sleep modes
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62 will be broken. We realize that this flash and RAM capacity (16 MiB and
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63 8 MiB, respectively) is extreme overkill for typical modem applications
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64 outside of development, but supporting multiple flash chip types would
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65 introduce a configuration management burden which we are not willing to
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66 take on.
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67
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68 * Calypso's unused DSR_MODEM/LPG pin was left unconnected in Openmoko's version
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69 but on our FCDEV3B it is tied to GND on the board. Other boards seeking to
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70 be FreeCalypso-compatible need to have this pin tied to GND as well because
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71 our firmware leaves this pin in its default power-up config of DSR_MODEM input
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72 and does not change it to LPG output - leaving it unconnected would cause it
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73 to float.
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74
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75 * Our firmware configures Calypso GPIO 3 as an input; GPIOs 0-2 and those
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76 multifunction pins which are unused and configured as GPIOs (TSPDI/IO4,
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77 BCLKX/IO6, MCUEN1/IO8 and MCUEN2/IO13) are configured as outputs. Board
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78 wiring must be compatible with these directions: those pins which our fw
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79 drives as outputs can be simply left unconnected, while GPIO 3 needs to be
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80 sensibly driven or tied off as explained below.
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81
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82 * If someone needs a modem that produces an Openmoko-style application processor
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83 wakeup signal (asserted by the fw when the modem needs to send something to
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84 the host but is blocked by CTS being held high), this signal should be
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85 connected to GPIO 0. Openmoko used GPIO 1 for this purpose, but in
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86 FreeCalypso GPIO 1 is taken because we use it for the loudspeaker control
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87 signal like on TI's D-Sample and Leonardo boards, hence we are moving the AP
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88 wakeup signal to GPIO 0, to be implemented if and when anyone builds a modem
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89 based on FC-TMS that needs to provide such a signal.
2
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90
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91 * If your product includes a loudspeaker amplifier like on our FCDEV3B, connect
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92 its on/off control input to GPIO 1, otherwise leave our GPIO 1 output
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93 unconnected.
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94
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95 * Our fw produces a DCD modem control output on GPIO 2; if you are connecting
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96 the MODEM UART channel to an RS-232 port or to a USB-serial chip with a full
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97 set of modem control signals, connect DCD to GPIO 2.
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98
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99 * Our fw treats GPIO 3 as a DTR modem control input following TI's C-Sample and
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100 D-Sample boards. If your product has a real DTR signal coming from an RS-232
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101 interface or from a USB-serial chip, connect it to GPIO 3, otherwise GPIO 3
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102 needs to be pulled down to GND like on Leonardo and FCDEV3B.
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103
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104 * If you are connecting the MODEM UART channel to a full RS-232 port or to a
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105 USB-serial chip with a full set of modem control signals, you should connect
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106 DSR and RI to TSPDI/IO4 and MCUEN1/IO8, respectively. Right now our fw
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107 drives IO4 low and IO8 high, corresponding to DSR asserted and RI negated
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108 (normal quiescent state), and connecting the signals in this way allows the
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109 possibility of extending the fw to drive them in some more intelligent manner
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110 if need be.
2
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111
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112 * Both Calypso UARTs need to be wired in an accessible way so that our standard
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113 FC Magnetite firmware can be used with the AT command interface on the MODEM
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114 UART and RVTMUX on the IrDA UART.
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115
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116 * Our fw configures the MODEM UART with hardware flow control enabled; if your
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117 applications lacks RTS/CTS signals, then Calypso's CTS_MODEM signal needs to
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118 be pulled down to GND so it is seen as asserted.
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119
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120 * Our fw configures the 4 MCSI/GPIO pins as MCSI rather than GPIO. If your
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121 board does not use MCSI because you are tapping VSP instead or not using any
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122 digital voice interface at all, then you should put pull-down resistors on
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123 MCSI_RXD, MCSI_CLK and MCSI_FSYNCH, otherwise these signals will float.
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124
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125 Tapping VSP for the digital voice interface
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126 ===========================================
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127
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128 The Calypso+Iota chipset includes an interface called VSP for Voice Serial Port;
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129 per TI's design intent it is a strictly private interface between Calypso and
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130 Iota chips, but it is possible to tap into this interface to get an external
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131 digital voice channel. TI's official method for getting a digital voice channel
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132 out of a Calypso modem is to use MCSI in their so-called "Bluetooth headset"
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133 mode, however, our experiments on the FCDEV3B have revealed that this interface
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134 does not work the way one would naively expect. Unless we can convince TI to
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135 dig up and release the sources for the Calypso DSP ROM, which we obviously
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136 cannot count on, we won't be able to use MCSI reliably until and unless we
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137 undertake to fully reverse their DSP ROM code from disassembly, which would be
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138 an extremely major and very costly undertaking. Because of this unfortunate
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139 situation, the alternative way of tapping into VSP needs to be given
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140 consideration.
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141
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142 Tapping into VSP is absolutely not possible on our current FCDEV3B, as the
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143 signals in question are currently routed directly from one BGA to another and
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144 do not come up to the surface at any accessible point. The same situation holds
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145 on every other existing Calypso phone and modem known to us - after all, VSP was
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146 meant to be a private chip-to-chip interface. Instead we are presenting the
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147 idea of tapping VSP as a possibility for anyone who undertakes to repackage our
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148 FC-TMS into some new form factor and desires a digital voice channel while at
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149 it.
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150
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151 In TI's standard solution VSP clock and frame sync signals are generated by the
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152 Iota ABB and are inputs to the Calypso DBB. Because they are inputs to the
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153 Calypso, it may be tempting to disconnect them from the ABB and have them
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154 originate from an external source instead - however, TI's DSP code in the ROM
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155 was most certainly written with the assumption that these signals will only
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156 ever be driven by their ABB and never by anyone else, hence having them come
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157 from a source whose timing does not come from the Calypso can cause all kinds
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158 of strangeness which we will never be able to debug properly because the DSP is
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159 a mysterious black box. Therefore, my (Mother Mychaela's) stance is that if
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160 you break the VSP connection between Calypso and Iota, then you are entirely on
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161 your own - don't expect any help from me. Instead my idea is to tap into VSP
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162 without breaking it, specifically:
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163
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164 * Keep the clock and frame sync connection between Calypso and Iota, with Iota
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165 remaining the driver on these nets - but also bring these signals out
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166 externally, so external logic can sync itself to this interface as well.
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167
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168 * Do likewise for the line that carries downlink voice from the DBB to the ABB:
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169 let the ABB receive it and use it to drive the analogue earpiece output (which
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170 would be unconnected in a digital voice application), but let external logic
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171 receive it too.
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172
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173 * Break only the line that carries uplink voice from the ABB to the DBB: bring
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174 the Iota output side on one external interface pin and the Calypso input side
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175 on another external interface pin. Putting a jumper on these adjacent header
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176 pins would restore TI's original configuration and allow uplink voice to come
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177 from an analogue microphone connected to the ABB, and if a digital uplink
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178 voice source is desired, remove the jumper and have an external source provide
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179 the bits which would otherwise come from Iota's voice ADC.
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180
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181 The above approach would provide a usable digital voice interface that would be
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182 completely transparent (invisible) to the Calypso DSP and even to the ARM-side
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183 firmware, hence it should work without any nasty surprises.