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annotate MEMIF-wait-states @ 37:ac33ec9a07d9

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DUART28-with-FCDEV3B: the end going to DUART28 can be either blue or grey
author Mychaela Falconia <falcon@freecalypso.org>
date Wed, 20 Jan 2021 23:18:34 +0000
parents c01155dec65b
children
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17
3d65bdaf00da MEMIF-wait-states article written
Mychaela Falconia <falcon@freecalypso.org>
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1 The Calypso chip's MEMIF (ARM memory interface) block has a few configuration
3d65bdaf00da MEMIF-wait-states article written
Mychaela Falconia <falcon@freecalypso.org>
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2 registers; most settings in these registers are quite straightforward, but the
3d65bdaf00da MEMIF-wait-states article written
Mychaela Falconia <falcon@freecalypso.org>
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3 WS setting (number of wait states to be inserted for external memory access)
3d65bdaf00da MEMIF-wait-states article written
Mychaela Falconia <falcon@freecalypso.org>
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4 requires some non-trivial analysis.
3d65bdaf00da MEMIF-wait-states article written
Mychaela Falconia <falcon@freecalypso.org>
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5
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Mychaela Falconia <falcon@freecalypso.org>
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6 Calypso MEMIF timings are described on pages 7 through 11 of this TI document:
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7
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8 ftp://ftp.freecalypso.org/pub/GSM/Calypso/cal000_a.pdf
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9
25
c01155dec65b MEMIF-wait-states: updates for the newly discovered CAL000/A v0.8 document
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10 as well as this more recently discovered newer version:
c01155dec65b MEMIF-wait-states: updates for the newly discovered CAL000/A v0.8 document
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11
c01155dec65b MEMIF-wait-states: updates for the newly discovered CAL000/A v0.8 document
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12 ftp://ftp.freecalypso.org/pub/GSM/Calypso/cal000_a_v0.8.pdf
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13
17
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14 When running on a Calypso C035 target, our TCS211 reference fw as well as most
3d65bdaf00da MEMIF-wait-states article written
Mychaela Falconia <falcon@freecalypso.org>
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15 vendor firmwares we've examined run the ARM7 core at its maximum clock frequency
3d65bdaf00da MEMIF-wait-states article written
Mychaela Falconia <falcon@freecalypso.org>
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16 of 52 MHz. These same firmwares typically configure WS=3 for both flash and
3d65bdaf00da MEMIF-wait-states article written
Mychaela Falconia <falcon@freecalypso.org>
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17 XRAM. Most Calypso-based phones and modems have flash and RAM chips with 70 ns
3d65bdaf00da MEMIF-wait-states article written
Mychaela Falconia <falcon@freecalypso.org>
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18 access time, and for a long time it seemed that this combination of ARM7 at
3d65bdaf00da MEMIF-wait-states article written
Mychaela Falconia <falcon@freecalypso.org>
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19 52 MHz and WS=3 was OK for 70 ns memories: one ARM7 clock cycle at 52 MHz is
3d65bdaf00da MEMIF-wait-states article written
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20 19.23 ns, WS=3 means 4 cycles total per access (it's an N+1 arrangement),
3d65bdaf00da MEMIF-wait-states article written
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21 19.23 ns * 4 = 76.92 ns, thus it should be OK for 70 ns memories, right? Not
3d65bdaf00da MEMIF-wait-states article written
Mychaela Falconia <falcon@freecalypso.org>
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22 so fast: as shown in the formula on cal000_a.pdf page 11 and can be seen from
3d65bdaf00da MEMIF-wait-states article written
Mychaela Falconia <falcon@freecalypso.org>
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23 the timing diagrams, two other timing parameters (tda and tsu) also need to be
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c01155dec65b MEMIF-wait-states: updates for the newly discovered CAL000/A v0.8 document
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24 factored in. The sum of tda+tsu for 2.8V MEMIF as given in the CAL000/A v0.2
c01155dec65b MEMIF-wait-states: updates for the newly discovered CAL000/A v0.8 document
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25 document is 10.5 ns, thus if we run the ARM7 core at 52 MHz and set WS=3, the
c01155dec65b MEMIF-wait-states: updates for the newly discovered CAL000/A v0.8 document
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26 available safe window for memory access time is only about 66 ns, which is 4 ns
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27 short of the 70 ns flash and RAM access time specs.
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28
c01155dec65b MEMIF-wait-states: updates for the newly discovered CAL000/A v0.8 document
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29 The more recently discovered version 0.8 of this same CAL000/A document
c01155dec65b MEMIF-wait-states: updates for the newly discovered CAL000/A v0.8 document
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30 indicates that the tables for 2.8V and 1.8V MEMIF were erroneously swapped in
c01155dec65b MEMIF-wait-states: updates for the newly discovered CAL000/A v0.8 document
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31 the older version, and the new correct tda+tsu number for 2.8V MEMIF now appears
c01155dec65b MEMIF-wait-states: updates for the newly discovered CAL000/A v0.8 document
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32 to be 8.0 ns rather than 10.5 ns. The available safe window for memory access
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33 time with WS=3 thus becomes 68.92 ns - this new figure is much closer to 70 ns,
c01155dec65b MEMIF-wait-states: updates for the newly discovered CAL000/A v0.8 document
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34 but it is still a negative margin, short by 1.08 ns.
17
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35
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36 TI's reference fw setting of WS=3 in conjuction with ARM7 running at 52 MHz has
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37 made its way into the official firmwares of Openmoko devices and several Compal
3d65bdaf00da MEMIF-wait-states article written
Mychaela Falconia <falcon@freecalypso.org>
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38 phones, including Mot C11x/12x, Mot C139/140 and Sony Ericsson J100. At least
3d65bdaf00da MEMIF-wait-states article written
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39 in the case of Openmoko we know that the hardware features a flash chip with
3d65bdaf00da MEMIF-wait-states article written
Mychaela Falconia <falcon@freecalypso.org>
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40 70 ns access time (the combined flash+RAM chip is K5A3281CTM-D755, with the
3d65bdaf00da MEMIF-wait-states article written
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41 suffix meaning 70 ns access time for flash and 55 ns for RAM), and in the case
3d65bdaf00da MEMIF-wait-states article written
Mychaela Falconia <falcon@freecalypso.org>
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42 of Compal phones it is highly unlikely that they used flash chips faster than
3d65bdaf00da MEMIF-wait-states article written
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43 70 ns, thus we have strong evidence that the access time spec is being violated
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44 by about 1.1 ns. It works in practice because the official specs are guaranteed
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45 worst-case numbers and the shortcoming is very small, but it is still wrong in
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46 the strict sense.
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47
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48 We have strong evidence that this WS=3 setting comes from TI's mainline
3d65bdaf00da MEMIF-wait-states article written
Mychaela Falconia <falcon@freecalypso.org>
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49 reference fw, as opposed to being customized by or for Openmoko or Compal.
3d65bdaf00da MEMIF-wait-states article written
Mychaela Falconia <falcon@freecalypso.org>
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50 The evidence is in the following instruction sequence which appears verbatim-
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51 identical across Openmoko's, Mot C11x/12x and C139/140 firmware versions:
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52
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53 ldr r1, =0xFFFFFB00
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54 mov r0, #0xA3
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55 strh r0, [r1, #0]
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56 strh r0, [r1, #2]
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57 mov r2, #0xA5
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58 strh r2, [r1, #4]
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59 strh r0, [r1, #6]
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60 mov r0, #0x80
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61 strh r0, [r1, #0xA]
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62 mov r0, #0xC0
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63 strh r0, [r1, #0xC]
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64 mov r0, #0x40
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65 strh r0, [r1, #8]
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66
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67 (The SE J100 version differs only in the nCS2 configuration; apparently this
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68 SE J100 phone has its ringtone melody generator chip hooked up to nCS2, whereas
3d65bdaf00da MEMIF-wait-states article written
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69 on both OM's modem and Mot C11x/12x/139/140 this chip select is unused and
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Mychaela Falconia <falcon@freecalypso.org>
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70 unconnected, meaning that its setting is a dummy just like nCS3 and nCS4.)
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71
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72 The above instruction sequence has been reconstructed into the following
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73 sequence of C macro calls:
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74
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75 MEM_INIT_CS0(3, MEM_DVS_16, MEM_WRITE_EN, 0);
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76 MEM_INIT_CS1(3, MEM_DVS_16, MEM_WRITE_EN, 0);
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77 MEM_INIT_CS2(5, MEM_DVS_16, MEM_WRITE_EN, 0);
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78 MEM_INIT_CS3(3, MEM_DVS_16, MEM_WRITE_EN, 0);
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79 MEM_INIT_CS4(0, MEM_DVS_8, MEM_WRITE_EN, 0);
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80
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81 MEM_INIT_CS6(0, MEM_DVS_32, MEM_WRITE_EN, 0);
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82 MEM_INIT_CS7(0, MEM_DVS_32, MEM_WRITE_DIS, 0);
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83
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84 (The last two lines setting nCS6 and nCS7 don't need to be considered, as those
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85 are internal to the Calypso chip itself.)
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86
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87 Thus we see that what appears to be TI's mainline code sets WS=3 for both nCS0
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Mychaela Falconia <falcon@freecalypso.org>
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88 and nCS1 (flash and XRAM, respectively), and then sets what appears to be a
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Mychaela Falconia <falcon@freecalypso.org>
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89 dummy config for the unused nCS2, nCS3 and nCS4. I say "appears to be" because
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90 we have no original source with comments, only a COFF binary object which our
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91 reconstructed recompilable C code has been made to match.
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92
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93 We may never know the truth unless we miraculously find a surviving copy of the
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94 original (not reconstructed from disassembly) init.c source from TCS211, but my
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95 (Mother Mychaela's) current working hypothesis is that the above MEMIF settings
3d65bdaf00da MEMIF-wait-states article written
Mychaela Falconia <falcon@freecalypso.org>
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96 were originally made for the D-Sample board and never changed for Leonardo.
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Mychaela Falconia <falcon@freecalypso.org>
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97 The D-Sample board has flash on nCS0, main XRAM bank on nCS1, an additional
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Mychaela Falconia <falcon@freecalypso.org>
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98 XRAM bank (typically unused) on nCS2 and peripherals (principally the LCD) on
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Mychaela Falconia <falcon@freecalypso.org>
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99 nCS3. Furthermore, the original D-Sample boards had Calypso C05 chips populated
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100 on them, and that chip version has no nCS4, only CS4 which is muxed with ADD22
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Mychaela Falconia <falcon@freecalypso.org>
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101 and used for the latter on the D-Sample.
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102
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103 I further hypothetize that the above MEMIF settings were likely cast into code
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Mychaela Falconia <falcon@freecalypso.org>
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104 in the days of Calypso C05, and that the WS=3 setting was computed when the
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105 ARM7 core ran at 39 MHz. The combination of ARM7 at 39 MHz, WS=3 and the more
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106 generous tda+tsu = 10.5 ns adjustment from the older cal000_a.pdf document
17
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Mychaela Falconia <falcon@freecalypso.org>
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107 (officially corresponding to Calypso C035 F751774) gives an access time of
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Mychaela Falconia <falcon@freecalypso.org>
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108 92 ns, which is very sensible. The hypothesis further goes that later TI moved
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Mychaela Falconia <falcon@freecalypso.org>
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109 to Calypso C035 silicon and started running the ARM7 core at 52 MHz, but the WS
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Mychaela Falconia <falcon@freecalypso.org>
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110 setting was never changed (overlooked), and the 92 ns access time turned into a
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111 mere 68.92 ns. The latter works with 70 ns memories in practice despite being
17
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112 strictly incorrect (negative margin), and so the error escaped notice.
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113
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114 Solution adopted for FreeCalypso
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115 ================================
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116
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117 Pirelli's firmware on the DP-L10 sets WS=4 for both flash and XRAM, and we have
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118 always used the same setting in FreeCalypso when running on this target. When
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119 we made our FCDEV3B hardware using the same Spansion flash+RAM chip copied from
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120 the Pirelli DP-L10, we adopted the same WS=4 setting for our own FreeCalypso
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121 hardware family on the reasoning that it is needed for this chip. But now we
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122 have a better theoretical foundation: the flash+RAM chip in question has 70 ns
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123 access time for both flash and pSRAM parts, same as most other flash and RAM
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124 chips used in most Calypso devices, and the WS=4 setting should really be used
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125 for all Calypso C035 targets (ARM7 at 52 MHz) with 70 ns memories. Thus the
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126 new FreeCalypso strategy is to treat WS=4 as the generic default for Calypso
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127 C035 platforms unless explicitly overridden for specific targets, and to stop
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128 treating TI's reconstructed setup with WS=3 as canonical.
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129
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130 When running on Openmoko GTA01/02, Mot C11x/12x, Mot C139/140 and SE J100
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131 targets (this specific list), we are going to keep WS=3 for nCS0 and nCS1 and
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132 the dummies for nCS2, nCS3 and nCS4 unchanged for now, i.e., run with exactly
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133 the same MEMIF settings as each manufacturer's respective original official fw.
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134 The reason is political: we are not the product manufacturer of record, and the
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135 error of negative design margin in the memory access timings is the liability
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136 of FIC/Openmoko and Compal/Motorola/SE, not us. If we change from WS=3 to WS=4
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137 on these targets, our firmware will necessarily run a little slower, and given
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138 that the original official fw "works just fine", we may be accused of needlessly
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139 or artificially slowing down our aftermarket fw. But when we market our own
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140 handset or modem products under the FreeCalypso trademark, then the full
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141 responsibility for the entire product (hw+fw) falls on us, hence we use the
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142 correct WS=4 setting.
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143
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144 Interim WS setting during boot
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145 ==============================
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146
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147 There is one more complication to this picture. The MEMIF settings discussed
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148 above for the operational phase with Calypso DPLL producing fast clocks are
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149 made in the Init_Target() function, but there is another interim setting
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150 established early on in assembly code, used prior to DPLL enabling, when the
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151 ARM7 core runs at unmultiplied 13 MHz or 26 MHz as fed to the Calypso by the
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152 board. This interim setting is first set in bootloader.s, then again in int.s
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153 (with the definition residing in the included init.asm file), and the registers
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154 are set to 0x2A1, meaning WS=1 and 1 dummy cycle.
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155
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156 Unlike the situation with the censored init.c source file, we have the original
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157 source for the assembly modules in question, and the only preprocessor
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158 conditionals found therein are based on BOARD and CHIPSET symbols. Remember
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159 that TI's Leonardo board never got its own BOARD number, instead it shares
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160 BOARD=41 with D-Sample, yet the two boards have different Calypso clock inputs:
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161 13 MHz on the DS, 26 MHz on the Leonardo. The C code in init.c (this part
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162 survived in the LoCosto source) uses a preprocessor conditional on the RF_FAM
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163 symbol to differentiate between 13 MHz and 26 MHz input clock arrangements, but
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164 there is no conditional of any such sort in the assembly code. Thus it is my
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165 (Mother Mychaela's) educated guess that the WS=1 setting was chosen assuming a
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166 13 MHz clock, and when Leonardo came along with its 26 MHz clock, the problem
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167 spot was once again overlooked.
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168
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169 WS=1 at 13 MHz is equivalent to WS=7 at 52 MHz, thus there is plenty of margin.
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170 But WS=1 at 26 MHz is equivalent to WS=3 at 52 MHz, once again putting us in
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171 the troubled territory of negative margin with 70 ns flash and RAM chips.
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172 Except that this case is even more difficult for firmware engineers to spot:
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173 Pirelli's fw still has the same 0x2A1 setting in its early boot path, i.e.,
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174 their fw engineers have changed WS=3 to WS=4 for the main body of the fw, but
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175 missed the early boot code.
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176
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177 The solution adopted for FreeCalypso is to change the early MEMIF setting from
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178 0x2A1 to 0x2A2, i.e., set WS=2 for the interim boot phase.