FreeCalypso > hg > freecalypso-docs
annotate Calypso-PWM-light @ 77:da3bb12c2e6f
FC-handset-spec: overhaul of Mother's vision for FC Venus board
author | Mychaela Falconia <falcon@freecalypso.org> |
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date | Sun, 19 Sep 2021 03:40:13 +0000 |
parents | 1cdd0f0a6e70 |
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rev | line source |
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Calypso-PWM-light and Calypso-buzzer-output articles written
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1 The Calypso chip has a PWM light output called LT/PWL - a digital output pin |
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2 that can be configured as either LT or PWL. The documentation we got from TI |
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3 is not exhaustively complete in describing the exact behaviour and output |
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4 waveforms of these two modes, thus I (Mother Mychaela) did a little bit of lab |
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5 experimentation to complete the picture. All experimental observations were |
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6 made with an oscilloscope probe placed on the LT/PWL signal on a FreeCalypso |
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7 Caramel2 board. |
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8 |
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9 LT mode |
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10 ======= |
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11 |
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12 LT functionality of the LT/PWL output is implemented in the ARMIO block, |
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13 together with GPIO and keypad functions. LT output stays at constant low level |
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14 (zero light) only when the LIGHT bit in BUZZ_LIGHT_REG (FFFE:480E) is cleared; |
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15 if the LIGHT bit is set, then a small amount of light will be emitted even if |
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16 LIGHT_LEVEL_REG is set to 0, contrary to CAL207 document saying "no light" in |
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17 this case. Light levels 0 through 63 as written into LIGHT_LEVEL_REG really |
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18 correspond to 1/64 through 64/64 in terms of the actual emitted PWM duty cycles. |
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19 If the register is written with the maximum light level of 63, then LT output |
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20 is a continuous high level, with no o'scope-observable PWM activity. If the |
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21 register is written with any other value, then PWM activity becomes visible on |
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22 an oscilloscope, with each full cycle period equal to 64 periods of CLK13M, |
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23 i.e., PWM frequency equals 203.125 kHz, the master 13 MHz clock divided by 64. |
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24 The shape of this PWM output is totally straightforward: if LIGHT_LEVEL_REG is |
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25 set to 0, LT output is high for one CLK13M period and low for 63 periods, then |
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26 repeat; if LIGHT_LEVEL_REG is set to 1, LT output is high for 2 CLK13M periods |
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27 and low for 62 periods, and so forth, with LIGHT_LEVEL_REG set to 63 resulting |
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28 in LT being high in all 64 slots, i.e., continuous high output with no visible |
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29 PWM activity. |
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30 |
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31 PWL mode |
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32 ======== |
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33 |
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34 The description of PWL in the CAL207 document is reasonably good; only a few |
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35 additional notes need to be made: |
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36 |
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37 * By the fundamental principles of how all LFSRs work, an LFSR of N bits CANNOT |
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38 have a period of 2**N, instead the greatest period that can be achieved with |
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39 careful choice of polynomial is 2**N-1. Calypso PWL block features an 8-bit |
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40 LFSR, TI's choice of polynomial (hard-wired in the silicon) is a proper one, |
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41 thus the period is 255. |
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42 |
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43 * Two alternate hw implementations are possible: XOR implementation would |
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44 produce an LFSR with valid values [1,255], whereas XNOR implementation would |
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45 produce an LFSR with valid values [0,254]. Obviously we have no way to look |
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46 inside Calypso silicon, but the visible behaviour with different comparator |
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47 values suggests that the internal LFSR runs in the [1,255] range. There must |
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48 be some reset logic in the hw that prevents a stuck value of 0. |
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49 |
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50 * The visible output on the PWL pin repeats every 255 cycles of CLK32K, and the |
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51 average light intensity ranges from 0/255 to 254/255 in 1/255 steps. If |
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52 PWL_LEVEL_REG is set to either 0 or 1, PWL output is continuous low; if the |
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53 register is set to 2, PWL output is 1/255 (on for just one CLK32K cycle out of |
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54 255), and if the register is set to maximum of 255, PWL output is NOT |
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55 continuous high as CAL207 claims, but instead it is 254/255, i.e., on for 254 |
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56 out of every 255 CLK32K periods. |
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57 |
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58 Deep sleep interaction |
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59 ====================== |
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60 |
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61 LT mode uses CLK13M, thus it is incompatible with deep sleep. PWL uses CLK32K |
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62 instead, thus deep sleep is perfectly OK with this light on. |