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TCH-tap-modes: document FACCH/H observations
author Mychaela Falconia <falcon@freecalypso.org>
date Mon, 22 Jul 2024 23:02:54 +0000
parents 28c1cb869d91
children
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1 It has been discovered that the DSP ROM in the Calypso GSM baseband processor
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2 makes it possible to "tap" into speech traffic on GSM traffic channels (TCH):
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3
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4 1) In the downlink direction, the signal processing chain which every GSM MS
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5 must implement includes a GSM 05.03 channel decoder, operating in one of
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6 several variants as necessary for each supported TCH mode, followed by speech
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7 decoders for each supported codec. TI's DSP naturally implements this
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8 required signal processing chain, and this implementation includes one nifty
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9 feature: the bits that make up the internal interface from GSM 05.03 channel
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10 decoder output to the input of speech decoders are written into the NDB API
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11 RAM page that is also accessible to the ARM core, and these bits can be
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12 externally read out. The act of reading these bits is completely
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13 non-invasive (we are only reading bits that are already there, not modifying
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14 anything), thus we can sniff TCH downlink on any voice call in real time
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15 without disrupting or impacting standard type-approved GSM MS operation in
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16 any way.
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17
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18 2) In the uplink direction, there is a reverse signal processing chain in which
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19 the output of the internal speech encoder for the selected codec feeds into
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20 the input of the corresponding GSM 05.03 channel encoder. In this direction
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21 there are two tapping possibilities:
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22
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23 2a) There is a buffer in the NDB API RAM page from which one can read the bits
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24 that pass from the speech encoder output to the channel encoder input -
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25 let's call this form of TCH tap "uplink sniffing";
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26
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27 2b) There is a special mode in which the output of the internal speech encoder
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28 is effectively suppressed and the input to the channel encoder comes from
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29 another NDB API RAM buffer that needs to be filled by ARM firmware - let's
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30 call this form of TCH tap "uplink substitution".
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31
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32 Sources of knowledge about these DSP functions
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33 ==============================================
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34
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35 For the functions of TCH DL sniffing (tap 1 in the above summary) and TCH UL
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36 substitution (tap 2b in the above summary), the primary source of knowledge is
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37 the defunct '#if TRACE_TYPE==3' code in TSM30 and LoCosto L1 sources. I call
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38 this code defunct because the TRACE_TYPE preprocessor symbol is set to 4 (not 3)
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39 in both TCS211 and LoCosto versions, and appears to be set to 0 (all trace
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40 disabled) in the ancient TSM30 build. This code appears to be some very old
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41 test mode, apparently sending some test bit patterns into TCH UL and expecting
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42 the same bit patterns back on TCH DL, presumably with a test instrument such as
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43 CMU200 providing a loopback from UL to DL on this test TCH, and has only
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44 survived in an incomplete form:
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45
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46 * There are '#if TRACE_TYPE==3' stanzas in l1_cmplx.c, in both TSM30 and LoCosto
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47 versions, that implement DSP buffer writing for TCH UL substitution (TCH/F
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48 only) and timing control for TCH DL buffer reading (both TCH/F and TCH/H),
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49 calling a function named play_trace() for the latter.
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50
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51 * There is no play_trace() code in the LoCosto source. but there is an
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52 hw_debug.c source module in the TSM30 code drop under MCU/Layer1/L1c/Src,
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53 and it contains (presumed) TI-legacy play_trace() and play_diagnostics()
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54 functions, once again under '#if (TRACE_TYPE==3)'. play_trace() reads the
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55 DSP's TCH DL buffer and saves the bits in an ARM firmware RAM buffer, and
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56 then play_diagnostics() analyzes the captured booty - and studying the second
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57 function is how we learn the apparent original intent of doing test bit
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58 patterns on TCH.
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59
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60 * The code that feeds "UL play" test bit patterns to the earlier-mentioned
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61 '#if TRACE_TYPE==3' TCH UL substitution code in l1_cmplx.c (apparently once
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62 hacked into dll_read_dcch() and tx_tch_data()) has not been found anywhere.
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63
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64 For TCH tap 2a in our summary at the beginning of this article (non-invasive
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65 sniffing of TCH UL bits produced by the internal speech encoder) there does not
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66 exist any authoritative source of knowledge. It naturally follows from
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67 otherwise-known Calypso DSP architecture that these internally produced TCH UL
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68 bits should reside in the "main" a_du_0 buffer (or in a_du_1 when TCH/H
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69 subchannel 1 is active), and I (Mother Mychaela) have heard an anecdotal report
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70 (from someone who once worked with Calypso in a non-community-based manner) that
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71 these UL bits could indeed be read out of this buffer - but in the absence of
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72 an authoritative source, we don't know when would be the correct time to read
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73 this buffer.
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74
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75 In our current state of knowledge, only TCH DL sniffing can be exercised safely:
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76 for UL sniffing we don't know the correct time when the buffer would need to be
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77 read, while active UL substitution is obviously an invasive hack involving a DSP
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78 debug or test feature that is never used in standard GSM MS operation.
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79
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80 Support for different speech codecs
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81 ===================================
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82
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83 When it comes to passively sniffing TCH DL and/or UL, we are merely reading bits
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84 that are already there, and basic reasoning tells us that the DSP's DL and UL
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85 buffers involved in this exercise exist in all speech TCH modes supported by
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86 the DSP: FR1, HR1, EFR and AMR. However:
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87
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88 * The ancient '#if TRACE_TYPE==3' reference code exists only for FR1, HR1 and
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89 EFR - it clearly predates the addition of AMR in the later Calypso DSP
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90 versions.
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91
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92 * FR1, HR1 and EFR are the only codecs for which we (FreeCalypso community) know
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93 the format in which TCH DL bits appear in the DSP's a_dd_0 and a_dd_1 buffers.
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94
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95 * I (Mother Mychaela) have heard an anecdotal report (from the same
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96 non-community-based party mentioned earlier) that TCH DL bits could be read
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97 out of a_dd_0 buffer in TCH/AFS (AMR) mode - but I never got any details.
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98
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99 In contrast with passive sniffing, active TCH UL substitution requires explicit
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100 support from the DSP - and this explicit DSP support is known to exist for
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101 certain only for TCH/FS and TCH/EFS channel modes, i.e., for FR1 and EFR codecs
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102 only. In the case of TCH/HS channel mode (HR1 codec), it *appears* that the DSP
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103 supports UL substitution in this mode too, but this combination has only been
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104 exercised by OsmocomBB people (the original '#if TRACE_TYPE==3' code for UL play
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105 only supports TCH/F), and FreeCalypso policy is to treat everything coming out
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106 of OBB as highly suspect.
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107
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108 What about AMR? The anecdotal report (from the same already-mentioned party) is
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109 that TCH UL substitution that works for FR1 and EFR appears to NOT work for AMR
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110 - that's all I know - but frankly speaking, given that it's a weird DSP debug
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111 mode that is never needed in standard GSM MS operation, I find it more
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112 surprising that it works for FR1 and EFR than the observation that it doesn't
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113 work for AMR.
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114
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115 FreeCalypso support for TCH tap functions
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116 =========================================
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117
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118 TCH DL sniffing and UL substitution provisions were initially implemented in
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119 FreeCalypso back in 2016, but only in the Citrine version, which was deemed to
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120 be a dead end later that same year. However, this functionality is now being
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121 resurrected, and it has been incorporated into our production FC Tourmaline
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122 firmware as of 2022-12-13.
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123
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124 In order to activate the function of TCH DL sniffing and save the recording of a
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parents:
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125 TCH DL session into a file, one needs to use the fc-shell utility from FC host
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parents:
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126 tools, specifically the tch record command in an interactive fc-shell session.
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127 The format in which TCH DL tap traffic is passed over RVTMUX (an original
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parents:
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128 FreeCalypso invention) has changed in a slight but incompatible way between the
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parents:
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129 original hackish version from 2016 and the new production version as of 2022,
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parents:
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130 and capturing TCH DL with new firmware requires the updated version of fc-shell
106
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131 that was released as part of fc-host-tools-r18. The current (developed in late
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132 2022) incarnation of FreeCalypso TCH DL sniffing feature supports FR1, HR1 and
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parents: 95
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133 EFR codecs; initially only FR1 and EFR were tested, but in 2024 HR1 joined the
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parents: 95
diff changeset
134 tested and known-working set.
95
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parents:
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135
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136 The function of TCH UL substitution is currently implemented in FC Tourmaline
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Mychaela Falconia <falcon@freecalypso.org>
parents:
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137 only for FR1 and EFR (no HR1, no AMR), and it likewise requires running an
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Mychaela Falconia <falcon@freecalypso.org>
parents:
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138 interactive fc-shell session in which you would invoke the tool's tch play
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Mychaela Falconia <falcon@freecalypso.org>
parents:
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139 command. In the case of TCH UL play feature there has been NO change in the
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
140 RVTMUX transport format between 2016 and 2022 versions.
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Mychaela Falconia <falcon@freecalypso.org>
parents:
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141
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Mychaela Falconia <falcon@freecalypso.org>
parents:
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142 TCH DL DSP buffers and capture format
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Mychaela Falconia <falcon@freecalypso.org>
parents:
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143 =====================================
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144
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145 The DSP's NDB API page has two buffers in which TCH DL bits appear: a_dd_0 and
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Mychaela Falconia <falcon@freecalypso.org>
parents:
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146 a_dd_1. All TCH/F modes use a_dd_0, but TCH/H uses one buffer or the other
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Mychaela Falconia <falcon@freecalypso.org>
parents:
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147 depending on the subchannel: subchannel 0 uses a_dd_0, subchannel 1 uses a_dd_1.
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Mychaela Falconia <falcon@freecalypso.org>
parents:
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148 (It is certainly a strange design - the DSP won't be able to receive and decode
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Mychaela Falconia <falcon@freecalypso.org>
parents:
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149 the "wrong" subchannel because it doesn't know the ciphering key for the other
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Mychaela Falconia <falcon@freecalypso.org>
parents:
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150 MS - but perhaps the designers of this DSP architecture aeons ago found this
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
151 design to somehow flow more naturally with their scheduling of DSP tasks.) Each
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Mychaela Falconia <falcon@freecalypso.org>
parents:
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152 buffer consists of 22 16-bit words - they were originally 20 words, but then
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Mychaela Falconia <falcon@freecalypso.org>
parents:
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153 extended to 22 words to support CSD 14.4 kbps mode.
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Mychaela Falconia <falcon@freecalypso.org>
parents:
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154
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parents:
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155 Each TCH buffer in the DSP's NDB API page consists of 3 status or header words
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
156 followed by N words of payload, where N depends on TCH mode: 17 for TCH/FS and
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Mychaela Falconia <falcon@freecalypso.org>
parents:
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157 TCH/EFS, 8 for TCH/HS, and not-yet-studied for AMR and CSD. Let's begin our
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
158 analysis with the 3 status words that make up the buffer header:
8a45cd92e3c3 TCH-tap-modes: new article
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
159
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Mychaela Falconia <falcon@freecalypso.org>
parents:
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160 Status word 0 (a_dd_0[0] or a_dd_1[0]) is a word of flag bits. We don't know
106
28c1cb869d91 TCH-tap-modes: updates for TCH/HS
Mychaela Falconia <falcon@freecalypso.org>
parents: 95
diff changeset
161 the meaning of every bit in this word, but here are the bit meanings we've been
28c1cb869d91 TCH-tap-modes: updates for TCH/HS
Mychaela Falconia <falcon@freecalypso.org>
parents: 95
diff changeset
162 able to figure out so far, looking at TCH/FS, TCH/EFS and more recently TCH/HS
28c1cb869d91 TCH-tap-modes: updates for TCH/HS
Mychaela Falconia <falcon@freecalypso.org>
parents: 95
diff changeset
163 DL captures:
95
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parents:
diff changeset
164
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Mychaela Falconia <falcon@freecalypso.org>
parents:
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165 * Bit 15 (B_BLUD) is a "buffer filled" or "data present" flag. This flag is
8a45cd92e3c3 TCH-tap-modes: new article
Mychaela Falconia <falcon@freecalypso.org>
parents:
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166 observed as 1 in *almost* every 20 ms window in which a traffic frame is
8a45cd92e3c3 TCH-tap-modes: new article
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
167 expected (fn_report_mod13_mod4 == 0 in l1s_read_dedic_dl(), case TCHTF),
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
168 except for certain instances early in the call setup process which remain to
8a45cd92e3c3 TCH-tap-modes: new article
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
169 be studied.
8a45cd92e3c3 TCH-tap-modes: new article
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
170
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Mychaela Falconia <falcon@freecalypso.org>
parents:
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171 * Bit 14 (B_AF) will be set if the block of 8 half-bursts (block diagonal
8a45cd92e3c3 TCH-tap-modes: new article
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
172 interleaving of GSM 05.03) corresponding to this buffer was channel-decoded
8a45cd92e3c3 TCH-tap-modes: new article
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
173 as speech rather than as FACCH - see further analysis below.
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
174
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
175 * Bit 9 (B_ECRC) has only ever been observed as 1 when B_AF is set, i.e., when
8a45cd92e3c3 TCH-tap-modes: new article
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
176 the speech-not-FACCH channel decoder was invoked. In the case of TCH/EFS this
8a45cd92e3c3 TCH-tap-modes: new article
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
177 bit is set to 1 if the EFR-added CRC-8 was bad, and cleared if this CRC-8 was
8a45cd92e3c3 TCH-tap-modes: new article
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
178 good; in the case of TCH/FS this bit has always been observed as 1 and should
8a45cd92e3c3 TCH-tap-modes: new article
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
179 be ignored because there is no CRC-8 in TCH/FS.
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
180
106
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parents: 95
diff changeset
181 (Update for TCH/HS: in this channel mode this bit has always been observed
28c1cb869d91 TCH-tap-modes: updates for TCH/HS
Mychaela Falconia <falcon@freecalypso.org>
parents: 95
diff changeset
182 as 0.)
28c1cb869d91 TCH-tap-modes: updates for TCH/HS
Mychaela Falconia <falcon@freecalypso.org>
parents: 95
diff changeset
183
95
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parents:
diff changeset
184 * Bit 7 has always been observed as 1 wheneven B_BLUD is set but B_AF is
8a45cd92e3c3 TCH-tap-modes: new article
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
185 cleared, i.e., whenever the block was channel-decoded in FACCH rather than
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
186 speech mode.
8a45cd92e3c3 TCH-tap-modes: new article
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
187
8a45cd92e3c3 TCH-tap-modes: new article
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
188 * Bits 6:5 indicate the result of FIRE decoding in the event that the FACCH
8a45cd92e3c3 TCH-tap-modes: new article
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
189 decoder was invoked.
8a45cd92e3c3 TCH-tap-modes: new article
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
190
8a45cd92e3c3 TCH-tap-modes: new article
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
191 * Bits 4:3 carry the ternary SID flag encoded as in section 6.1.1 of GSM 06.31
8a45cd92e3c3 TCH-tap-modes: new article
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
192 and 06.81, but only when the speech-not-FACCH channel decoder was invoked as
8a45cd92e3c3 TCH-tap-modes: new article
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
193 indicated by B_AF.
8a45cd92e3c3 TCH-tap-modes: new article
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
194
106
28c1cb869d91 TCH-tap-modes: updates for TCH/HS
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parents: 95
diff changeset
195 (Update for TCH/HS: these bits apply to HR codec too, following GSM 06.41
28c1cb869d91 TCH-tap-modes: updates for TCH/HS
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parents: 95
diff changeset
196 section 6.1.1 now.)
28c1cb869d91 TCH-tap-modes: updates for TCH/HS
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parents: 95
diff changeset
197
95
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parents:
diff changeset
198 * Bit 2 is BFI as defined in section 6.1.1 of GSM 06.31 and 06.81. Whenever
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
199 the block was decoded as FACCH (bit 14 clear, bit 7 set), bit 2 has always
8a45cd92e3c3 TCH-tap-modes: new article
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
200 been observed as set, agreeing with the stipulation in GSM 06.31 and 06.81
8a45cd92e3c3 TCH-tap-modes: new article
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
201 that BFI=1 whenever a FACCH frame has been received. However, in the case of
8a45cd92e3c3 TCH-tap-modes: new article
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
202 TCH/EFS it appears that CRC-8 status (reported in bit 9) is NOT factored into
8a45cd92e3c3 TCH-tap-modes: new article
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
203 the logic that sets bit 2 - it appears that the subsequent speech decoding
8a45cd92e3c3 TCH-tap-modes: new article
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
204 logic is expected to OR bits 2 and 9 together to get the BFI flag for the Rx
8a45cd92e3c3 TCH-tap-modes: new article
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
205 DTX handler of GSM 06.81.
8a45cd92e3c3 TCH-tap-modes: new article
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
206
106
28c1cb869d91 TCH-tap-modes: updates for TCH/HS
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parents: 95
diff changeset
207 (Update for TCH/HS: bit 2 is BFI in HR codec too.)
28c1cb869d91 TCH-tap-modes: updates for TCH/HS
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parents: 95
diff changeset
208
28c1cb869d91 TCH-tap-modes: updates for TCH/HS
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parents: 95
diff changeset
209 * Bit 1 is seen only in TCH/HS, and appears to be the elusive BCI flag whose
28c1cb869d91 TCH-tap-modes: updates for TCH/HS
Mychaela Falconia <falcon@freecalypso.org>
parents: 95
diff changeset
210 existence has been figured out from ETSI GSM 06.06 reid.c source. See this
28c1cb869d91 TCH-tap-modes: updates for TCH/HS
Mychaela Falconia <falcon@freecalypso.org>
parents: 95
diff changeset
211 article for more information:
28c1cb869d91 TCH-tap-modes: updates for TCH/HS
Mychaela Falconia <falcon@freecalypso.org>
parents: 95
diff changeset
212
28c1cb869d91 TCH-tap-modes: updates for TCH/HS
Mychaela Falconia <falcon@freecalypso.org>
parents: 95
diff changeset
213 https://osmocom.org/projects/retro-gsm/wiki/HRv1_error_flags
28c1cb869d91 TCH-tap-modes: updates for TCH/HS
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parents: 95
diff changeset
214
28c1cb869d91 TCH-tap-modes: updates for TCH/HS
Mychaela Falconia <falcon@freecalypso.org>
parents: 95
diff changeset
215 * Bit 0 is UFI for TCH/HS only.
28c1cb869d91 TCH-tap-modes: updates for TCH/HS
Mychaela Falconia <falcon@freecalypso.org>
parents: 95
diff changeset
216
95
8a45cd92e3c3 TCH-tap-modes: new article
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
217 In the case of 20 ms blocks (reassembled from 8 half-bursts) that were channel-
8a45cd92e3c3 TCH-tap-modes: new article
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
218 decoded as speech rather than FACCH, the observed behavior is that bits 15 and
8a45cd92e3c3 TCH-tap-modes: new article
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
219 14 are set, the payload portion of the buffer is filled with the output from the
8a45cd92e3c3 TCH-tap-modes: new article
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
220 channel decoder, and bits 4:3 are set from this payload by the bit-counting rule
8a45cd92e3c3 TCH-tap-modes: new article
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
221 of section 6.1.1 of GSM 06.31 and 06.81 irrespective of the good-or-bad status
8a45cd92e3c3 TCH-tap-modes: new article
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
222 in bits 2 and 9. However, when bit 14 is clear and bit 7 is set, indicating
8a45cd92e3c3 TCH-tap-modes: new article
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
223 that the block (from 8 half-bursts) was channel-decoded in FACCH mode, the
8a45cd92e3c3 TCH-tap-modes: new article
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
224 following additional behavior is observed:
8a45cd92e3c3 TCH-tap-modes: new article
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
225
8a45cd92e3c3 TCH-tap-modes: new article
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
226 * The payload portion of the buffer remains unchanged from its previous content,
8a45cd92e3c3 TCH-tap-modes: new article
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
227 last written when a frame was channel-decoded in speech-not-FACCH mode;
8a45cd92e3c3 TCH-tap-modes: new article
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
228
8a45cd92e3c3 TCH-tap-modes: new article
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
229 * Bit 2 is set, bit 9 is cleared;
8a45cd92e3c3 TCH-tap-modes: new article
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
230
8a45cd92e3c3 TCH-tap-modes: new article
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
231 * Bits 4:3 are cleared even when they previously indicated SID based on the bit
8a45cd92e3c3 TCH-tap-modes: new article
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
232 pattern in the payload portion of the buffer, even when that SID-encoding
8a45cd92e3c3 TCH-tap-modes: new article
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
233 payload is still there.
8a45cd92e3c3 TCH-tap-modes: new article
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
234
8a45cd92e3c3 TCH-tap-modes: new article
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
235 In the standard TCH DL signal processing chain, GSM 05.03 channel decoding is
8a45cd92e3c3 TCH-tap-modes: new article
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
236 followed by the Rx DTX handler of GSM 06.31 or 06.81 for TCH/FS or TCH/EFS,
8a45cd92e3c3 TCH-tap-modes: new article
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
237 respectively. It appears that the Rx DTX handler implemented in TI's DSP is
8a45cd92e3c3 TCH-tap-modes: new article
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
238 driven by this status word 0 at the head of the buffer, and we can only guess
8a45cd92e3c3 TCH-tap-modes: new article
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
239 as to its exact logic. At this point it bears reminding that the functions of
8a45cd92e3c3 TCH-tap-modes: new article
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
240 the Rx DTX handler are not rigidly prescribed in the specs: in the case of EFR
8a45cd92e3c3 TCH-tap-modes: new article
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
241 the bit-exact reference implementation is normative only in certain aspects
8a45cd92e3c3 TCH-tap-modes: new article
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
242 (e.g., comfort noise generation after receiving SID), but is considered a non-
8a45cd92e3c3 TCH-tap-modes: new article
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
243 normative example in some other key aspects (all GSM 06.61 functions, including
8a45cd92e3c3 TCH-tap-modes: new article
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
244 what happens when a FACCH block was received when speech frames were expected),
8a45cd92e3c3 TCH-tap-modes: new article
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
245 and in the case of FR1 there is no bit-exact reference implementation at all,
8a45cd92e3c3 TCH-tap-modes: new article
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
246 only general guidance.
8a45cd92e3c3 TCH-tap-modes: new article
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
247
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
248 Having the curiosity of a cat, I (Mother Mychaela) naturally desire to know
8a45cd92e3c3 TCH-tap-modes: new article
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
249 exactly how the Rx DTX handler (the bridge between the channel decoder and the
8a45cd92e3c3 TCH-tap-modes: new article
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
250 speech decoder) works in TI's DSP. A full static reversing job on the DSP ROM
8a45cd92e3c3 TCH-tap-modes: new article
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
251 would provide complete answers, but is a very daunting proposition, thus I am
8a45cd92e3c3 TCH-tap-modes: new article
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
252 also looking at the idea of behavioral analysis: the output of the speech
8a45cd92e3c3 TCH-tap-modes: new article
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
253 decoder can be captured from MCSI on FCDEV3B hardware, or from the VSP tap on
8a45cd92e3c3 TCH-tap-modes: new article
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
254 FC Venus if we ever build that board, and if we combine that speech decoder
8a45cd92e3c3 TCH-tap-modes: new article
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
255 output capture with the currently-discussed capture of TCH DL buffers, we may
8a45cd92e3c3 TCH-tap-modes: new article
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
256 be able to glean some insight into the workings of the Rx DTX handler block: we
8a45cd92e3c3 TCH-tap-modes: new article
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
257 could implement a candidate Rx DTX handler clone in software and compare the
8a45cd92e3c3 TCH-tap-modes: new article
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
258 output (of this proposed handler followed by the spec-defined speech decoder)
8a45cd92e3c3 TCH-tap-modes: new article
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
259 against the actual speech output from the DSP.
8a45cd92e3c3 TCH-tap-modes: new article
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
260
8a45cd92e3c3 TCH-tap-modes: new article
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
261 Back to our exposition of TCH DL buffer content:
8a45cd92e3c3 TCH-tap-modes: new article
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
262
8a45cd92e3c3 TCH-tap-modes: new article
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
263 Status word 1 (a_dd_0[1] or a_dd_1[1]) is some kind of DSP measurement or count
8a45cd92e3c3 TCH-tap-modes: new article
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
264 which Calypso ARM fw does not need to look at, except when debugging - the only
8a45cd92e3c3 TCH-tap-modes: new article
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
265 code which I (Mother Mychaela) could find that does anything with this DSP
8a45cd92e3c3 TCH-tap-modes: new article
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
266 status word is the ancient play_diagnostics() code in the TSM30 version
8a45cd92e3c3 TCH-tap-modes: new article
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
267 (obviously never included in any production fw); this code looks at the unknown
8a45cd92e3c3 TCH-tap-modes: new article
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
268 word in question and calls it "D_MACC". This play_diagnostics() code compares
8a45cd92e3c3 TCH-tap-modes: new article
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
269 the D_MACC reading against a threshold, and if the per-block reading is below
8a45cd92e3c3 TCH-tap-modes: new article
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
270 the threshold, an error message is printed. That's all we know!
8a45cd92e3c3 TCH-tap-modes: new article
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
271
8a45cd92e3c3 TCH-tap-modes: new article
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
272 Status word 2 (a_dd_0[2] or a_dd_1[2]) is a bit error count: the code in
8a45cd92e3c3 TCH-tap-modes: new article
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
273 l1s_read_dedic_dl() reads this error count and uses it for RXQUAL computation
8a45cd92e3c3 TCH-tap-modes: new article
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
274 for measurement reports.
8a45cd92e3c3 TCH-tap-modes: new article
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
275
8a45cd92e3c3 TCH-tap-modes: new article
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
276 If one's area of interest is in replicating Rx DTX handling and speech decoding
8a45cd92e3c3 TCH-tap-modes: new article
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
277 that happens in the DSP, status words 1 and 2 can probably be ignored - instead
8a45cd92e3c3 TCH-tap-modes: new article
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
278 the important parts are status word 0 (extensively covered above) and the
8a45cd92e3c3 TCH-tap-modes: new article
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
279 payload portion of the buffer.
8a45cd92e3c3 TCH-tap-modes: new article
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
280
8a45cd92e3c3 TCH-tap-modes: new article
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
281 The payload portion of the buffer consists of some number of 16-bit words: 17
8a45cd92e3c3 TCH-tap-modes: new article
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
282 of them for TCH/FS and TCH/EFS, or 8 of them for TCH/HS. The DSP does not have
8a45cd92e3c3 TCH-tap-modes: new article
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
283 any notion of 8-bit bytes, instead it operates on 16-bit words as its elementary
8a45cd92e3c3 TCH-tap-modes: new article
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
284 data unit. The ordering of bits within these 16-bit words (in the payload
8a45cd92e3c3 TCH-tap-modes: new article
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
285 portion of TCH buffers) is from the most-significant bit toward the least-
8a45cd92e3c3 TCH-tap-modes: new article
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
286 significant bit, thus when these TCH buffers are transferred via octet-oriented
8a45cd92e3c3 TCH-tap-modes: new article
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
287 interfaces, the upper byte of each word should be transferred first, even though
8a45cd92e3c3 TCH-tap-modes: new article
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
288 this byte order is counter to the little-endian byte order of the Calypso ARM
8a45cd92e3c3 TCH-tap-modes: new article
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
289 core.
8a45cd92e3c3 TCH-tap-modes: new article
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
290
8a45cd92e3c3 TCH-tap-modes: new article
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
291 In the case of TCH/FS and TCH/EFS, the fill order of bits in the payload words
8a45cd92e3c3 TCH-tap-modes: new article
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
292 is as follows, starting with the most-significant bit of buffer word 3 (first
8a45cd92e3c3 TCH-tap-modes: new article
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
293 word of the payload portion):
8a45cd92e3c3 TCH-tap-modes: new article
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
294
8a45cd92e3c3 TCH-tap-modes: new article
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
295 * 182 bits of class 1;
8a45cd92e3c3 TCH-tap-modes: new article
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
296
8a45cd92e3c3 TCH-tap-modes: new article
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
297 * 4 dummy bits (always observed as 0);
8a45cd92e3c3 TCH-tap-modes: new article
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
298
8a45cd92e3c3 TCH-tap-modes: new article
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
299 * 78 bits of class 2;
8a45cd92e3c3 TCH-tap-modes: new article
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
300
8a45cd92e3c3 TCH-tap-modes: new article
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
301 * the last 8 bits of a_dd_0[19] are unused.
8a45cd92e3c3 TCH-tap-modes: new article
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
302
8a45cd92e3c3 TCH-tap-modes: new article
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
303 In the case of TCH/HS, the fill order is similar, but modified as appropriate
8a45cd92e3c3 TCH-tap-modes: new article
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
304 for TCH/HS:
8a45cd92e3c3 TCH-tap-modes: new article
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
305
8a45cd92e3c3 TCH-tap-modes: new article
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
306 * 95 bits of class 1;
8a45cd92e3c3 TCH-tap-modes: new article
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
307
8a45cd92e3c3 TCH-tap-modes: new article
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
308 * 4 dummy bits;
8a45cd92e3c3 TCH-tap-modes: new article
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
309
8a45cd92e3c3 TCH-tap-modes: new article
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
310 * 17 bits of class 2;
8a45cd92e3c3 TCH-tap-modes: new article
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
311
8a45cd92e3c3 TCH-tap-modes: new article
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
312 * the last 12 bits of a_dd_0[10] or a_dd_1[10] are unused.
8a45cd92e3c3 TCH-tap-modes: new article
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
313
8a45cd92e3c3 TCH-tap-modes: new article
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
314 Aside from the insertion of 4 extra dummy bits at the boundary between class 1
8a45cd92e3c3 TCH-tap-modes: new article
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
315 and class 2, the overall bit order is that of GSM 05.03 Figure 1 interface 1.
8a45cd92e3c3 TCH-tap-modes: new article
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
316
8a45cd92e3c3 TCH-tap-modes: new article
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
317 In the case of TCH/EFS, the following additional considerations apply:
8a45cd92e3c3 TCH-tap-modes: new article
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
318
8a45cd92e3c3 TCH-tap-modes: new article
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
319 * Bits [65:73] in all received DL frames, where CRC-8 would go in the 260-bit
8a45cd92e3c3 TCH-tap-modes: new article
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
320 frame of GSM 05.03 interface 1 for EFR, are always observed as 0, whether
8a45cd92e3c3 TCH-tap-modes: new article
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
321 this CRC-8 was good (a_dd_0[0] bit 9 clear) or bad (a_dd_0[0] bit 9 set).
8a45cd92e3c3 TCH-tap-modes: new article
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
322
8a45cd92e3c3 TCH-tap-modes: new article
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
323 * The handling of repetition bits (4 bits of 244-bit EFR codec frame, each of
8a45cd92e3c3 TCH-tap-modes: new article
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
324 which is triplicated in the channel encoding for transmission) is unclear.
8a45cd92e3c3 TCH-tap-modes: new article
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
325
8a45cd92e3c3 TCH-tap-modes: new article
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
326 Further detail regarding the repetition bits of TCH/EFS: distinct bit positions
8a45cd92e3c3 TCH-tap-modes: new article
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
327 exist in the 260-bit frame of GSM 05.03 interface 1 (which is the frame format
8a45cd92e3c3 TCH-tap-modes: new article
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
328 in the TCH buffers of TI's DSP) for each of the 3 copies of each of the 4
8a45cd92e3c3 TCH-tap-modes: new article
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
329 triplicated bits. It is obvious that correct decoding of these triplicated bits
8a45cd92e3c3 TCH-tap-modes: new article
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
330 requires a majority-vote function just like the one implemented in TMR systems
8a45cd92e3c3 TCH-tap-modes: new article
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
331 in space gear - but it is not absolutely and unquestionably obvious where this
8a45cd92e3c3 TCH-tap-modes: new article
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
332 TMR voting function is implemented in the Rx processing chain of TI's DSP. It
8a45cd92e3c3 TCH-tap-modes: new article
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
333 *appears* that this majority-vote function has already been performed by the DSP
8a45cd92e3c3 TCH-tap-modes: new article
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
334 function that writes a_dd_0, and that the first bit position out of each group
8a45cd92e3c3 TCH-tap-modes: new article
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
335 of 3 holds the output of this voting function, so that the subsequent speech
8a45cd92e3c3 TCH-tap-modes: new article
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
336 decoder only needs to use those "cooked" bits - but there is this mystery:
8a45cd92e3c3 TCH-tap-modes: new article
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
337
8a45cd92e3c3 TCH-tap-modes: new article
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
338 * At certain times, particularly during the main part of a test call, TCH DL
8a45cd92e3c3 TCH-tap-modes: new article
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
339 buffer readouts contain zeros in the "extra" repetition bit positions: for
8a45cd92e3c3 TCH-tap-modes: new article
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
340 each group of 3 bits, the first will contain 0 or 1, but the other two will
8a45cd92e3c3 TCH-tap-modes: new article
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
341 always be 0.
8a45cd92e3c3 TCH-tap-modes: new article
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
342
8a45cd92e3c3 TCH-tap-modes: new article
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
343 * At other times, seemingly in the beginning and ending parts of test calls,
8a45cd92e3c3 TCH-tap-modes: new article
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
344 TCH DL buffer readouts contain matching bit values in all 3 positions: for
8a45cd92e3c3 TCH-tap-modes: new article
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
345 each group of 3 bits, if the first bit is 0, the other two will also be 0, or
8a45cd92e3c3 TCH-tap-modes: new article
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
346 if the first bit is 1, then the other two will also be 1.
8a45cd92e3c3 TCH-tap-modes: new article
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
347
8a45cd92e3c3 TCH-tap-modes: new article
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
348 One possibility is that the DSP applies the required majority-voting function,
8a45cd92e3c3 TCH-tap-modes: new article
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
349 writes its output into the first bit position of each group of 3, but then
8a45cd92e3c3 TCH-tap-modes: new article
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
350 sometimes (and not at other times) applies another function that writes the
8a45cd92e3c3 TCH-tap-modes: new article
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
351 voting function output into the remaining bit positions, perhaps for loopback
8a45cd92e3c3 TCH-tap-modes: new article
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
352 of TCH DL into TCH UL. More study is needed in this area.
8a45cd92e3c3 TCH-tap-modes: new article
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
353
107
dfa5f99631a6 TCH-tap-modes: document FACCH/H observations
Mychaela Falconia <falcon@freecalypso.org>
parents: 106
diff changeset
354 Appearance of FACCH in TCH/HS downlink
dfa5f99631a6 TCH-tap-modes: document FACCH/H observations
Mychaela Falconia <falcon@freecalypso.org>
parents: 106
diff changeset
355 --------------------------------------
dfa5f99631a6 TCH-tap-modes: document FACCH/H observations
Mychaela Falconia <falcon@freecalypso.org>
parents: 106
diff changeset
356
dfa5f99631a6 TCH-tap-modes: document FACCH/H observations
Mychaela Falconia <falcon@freecalypso.org>
parents: 106
diff changeset
357 All mentions of FACCH handling in the previous description refer only to TCH/F.
dfa5f99631a6 TCH-tap-modes: document FACCH/H observations
Mychaela Falconia <falcon@freecalypso.org>
parents: 106
diff changeset
358 In the case of TCH/HS, the following differences in FACCH handling are seen:
dfa5f99631a6 TCH-tap-modes: document FACCH/H observations
Mychaela Falconia <falcon@freecalypso.org>
parents: 106
diff changeset
359
dfa5f99631a6 TCH-tap-modes: document FACCH/H observations
Mychaela Falconia <falcon@freecalypso.org>
parents: 106
diff changeset
360 * Bits [7:5] described earlier for the case of FACCH/F are never seen set in
dfa5f99631a6 TCH-tap-modes: document FACCH/H observations
Mychaela Falconia <falcon@freecalypso.org>
parents: 106
diff changeset
361 TCH/HS DL captures.
dfa5f99631a6 TCH-tap-modes: document FACCH/H observations
Mychaela Falconia <falcon@freecalypso.org>
parents: 106
diff changeset
362
dfa5f99631a6 TCH-tap-modes: document FACCH/H observations
Mychaela Falconia <falcon@freecalypso.org>
parents: 106
diff changeset
363 * In the first 20 ms frame position stolen for FACCH/H, status word 0 is seen
dfa5f99631a6 TCH-tap-modes: document FACCH/H observations
Mychaela Falconia <falcon@freecalypso.org>
parents: 106
diff changeset
364 as 0xC007 (looks like regular BFI), status word 1 is set to 0 (instead of
dfa5f99631a6 TCH-tap-modes: document FACCH/H observations
Mychaela Falconia <falcon@freecalypso.org>
parents: 106
diff changeset
365 whatever D_MACC is), and it is not clear whether or not status word 2 is
dfa5f99631a6 TCH-tap-modes: document FACCH/H observations
Mychaela Falconia <falcon@freecalypso.org>
parents: 106
diff changeset
366 still filled with the bit error count from the convolutional decoding step.
dfa5f99631a6 TCH-tap-modes: document FACCH/H observations
Mychaela Falconia <falcon@freecalypso.org>
parents: 106
diff changeset
367 (We've only seen 0 in that word.) The payload bits are filled with what
dfa5f99631a6 TCH-tap-modes: document FACCH/H observations
Mychaela Falconia <falcon@freecalypso.org>
parents: 106
diff changeset
368 looks like garbage, in contrast with FACCH/F behavior of retaining previous
dfa5f99631a6 TCH-tap-modes: document FACCH/H observations
Mychaela Falconia <falcon@freecalypso.org>
parents: 106
diff changeset
369 buffer content.
dfa5f99631a6 TCH-tap-modes: document FACCH/H observations
Mychaela Falconia <falcon@freecalypso.org>
parents: 106
diff changeset
370
dfa5f99631a6 TCH-tap-modes: document FACCH/H observations
Mychaela Falconia <falcon@freecalypso.org>
parents: 106
diff changeset
371 * In the second 20 ms frame position stolen for FACCH/H, status word 0 is seen
dfa5f99631a6 TCH-tap-modes: document FACCH/H observations
Mychaela Falconia <falcon@freecalypso.org>
parents: 106
diff changeset
372 as 0, status word 1 looks like correct D_MACC after 456 rather than 228 bits
dfa5f99631a6 TCH-tap-modes: document FACCH/H observations
Mychaela Falconia <falcon@freecalypso.org>
parents: 106
diff changeset
373 have been decoded, and status word 2 contains 0xFFFF. The "garbage" in the
dfa5f99631a6 TCH-tap-modes: document FACCH/H observations
Mychaela Falconia <falcon@freecalypso.org>
parents: 106
diff changeset
374 payload bits stays the same from the first half of FACCH/H.
dfa5f99631a6 TCH-tap-modes: document FACCH/H observations
Mychaela Falconia <falcon@freecalypso.org>
parents: 106
diff changeset
375
95
8a45cd92e3c3 TCH-tap-modes: new article
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
376 FreeCalypso file format for TCH DL captures
8a45cd92e3c3 TCH-tap-modes: new article
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
377 ===========================================
8a45cd92e3c3 TCH-tap-modes: new article
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
378
8a45cd92e3c3 TCH-tap-modes: new article
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
379 The file format written by fc-shell tch record command is ASCII hex, line-based,
8a45cd92e3c3 TCH-tap-modes: new article
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
380 with one line for every captured 20 ms window. The new format as of 2022 is:
8a45cd92e3c3 TCH-tap-modes: new article
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
381
8a45cd92e3c3 TCH-tap-modes: new article
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
382 * Each line begins with an FR, HR or EFR keyword indicating which variant of
8a45cd92e3c3 TCH-tap-modes: new article
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
383 TCH DL has been captured;
8a45cd92e3c3 TCH-tap-modes: new article
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
384
8a45cd92e3c3 TCH-tap-modes: new article
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
385 * This keyword is followed by 3 space-separated DSP status words, each written
8a45cd92e3c3 TCH-tap-modes: new article
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
386 as 4 hex digits;
8a45cd92e3c3 TCH-tap-modes: new article
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
387
8a45cd92e3c3 TCH-tap-modes: new article
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
388 * The main body of the frame is written as 33 (TCH/FS & TCH/EFS) or 15 (TCH/HS)
8a45cd92e3c3 TCH-tap-modes: new article
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
389 hex bytes, produced from the payload portion of the TCH DL buffer by turning
8a45cd92e3c3 TCH-tap-modes: new article
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
390 each 16-bit word into 2 bytes (MSB first) and discarding the last byte that
8a45cd92e3c3 TCH-tap-modes: new article
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
391 is unused (always 0);
8a45cd92e3c3 TCH-tap-modes: new article
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
392
8a45cd92e3c3 TCH-tap-modes: new article
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
393 * Each line ends with a frame number in decimal, specifically the value of
8a45cd92e3c3 TCH-tap-modes: new article
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
394 fn_mod_104 variable in the l1s_read_dedic_dl() function when the DSP buffer
8a45cd92e3c3 TCH-tap-modes: new article
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
395 was read.
8a45cd92e3c3 TCH-tap-modes: new article
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
396
8a45cd92e3c3 TCH-tap-modes: new article
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
397 The addition of the frame number field allows these TCH DL captures to be
8a45cd92e3c3 TCH-tap-modes: new article
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
398 reconciled against the SACCH multiframe structure, which matters for the rules
8a45cd92e3c3 TCH-tap-modes: new article
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
399 of DTX.
8a45cd92e3c3 TCH-tap-modes: new article
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
400
8a45cd92e3c3 TCH-tap-modes: new article
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
401 TCH UL substitution: open questions
8a45cd92e3c3 TCH-tap-modes: new article
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
402 ===================================
8a45cd92e3c3 TCH-tap-modes: new article
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
403
8a45cd92e3c3 TCH-tap-modes: new article
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
404 Moving from the mostly-understood realm of TCH DL capture into the much more
8a45cd92e3c3 TCH-tap-modes: new article
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
405 experimental realm of TCH UL substitution, we have some open questions: how does
8a45cd92e3c3 TCH-tap-modes: new article
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
406 this DSP special mode really work? Here is what we know: if we load externally
8a45cd92e3c3 TCH-tap-modes: new article
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
407 sourced speech frames into otherwise-unused a_du_1 DSP buffer at the time of
8a45cd92e3c3 TCH-tap-modes: new article
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
408 (fn_report_mod13_mod4 == 3), which is the same time when FACCH or CSD UL would
8a45cd92e3c3 TCH-tap-modes: new article
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
409 be expected, and set B_PLAY_UL bit in DSP NDB API word d_tch_mode, the speech
8a45cd92e3c3 TCH-tap-modes: new article
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
410 frame stream going to the other end of the call will be the one we feed into
8a45cd92e3c3 TCH-tap-modes: new article
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
411 a_du_1 instead of the one produced from the microphone input by the internal
8a45cd92e3c3 TCH-tap-modes: new article
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
412 speech encoder. But here are the parts we don't know:
8a45cd92e3c3 TCH-tap-modes: new article
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
413
8a45cd92e3c3 TCH-tap-modes: new article
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
414 * If one were to set B_PLAY_UL in d_tch_mode but not feed external UL input
8a45cd92e3c3 TCH-tap-modes: new article
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
415 into a_du_1 buffer at the needed time, what will happen?
8a45cd92e3c3 TCH-tap-modes: new article
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
416
8a45cd92e3c3 TCH-tap-modes: new article
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
417 * Vice-versa, if one were to load a_du_1 and set its B_BLUD bit without setting
8a45cd92e3c3 TCH-tap-modes: new article
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
418 B_PLAY_UL in d_tch_mode, what will happen?
8a45cd92e3c3 TCH-tap-modes: new article
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
419
8a45cd92e3c3 TCH-tap-modes: new article
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
420 * Can the frame stream fed into a_du_1 be encoded in DTX-enabled mode, including
8a45cd92e3c3 TCH-tap-modes: new article
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
421 SID frames? If this possibility is allowed, what magic bits would need to be
8a45cd92e3c3 TCH-tap-modes: new article
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
422 set where in order to get the correct behavior from the DSP's subsequent
8a45cd92e3c3 TCH-tap-modes: new article
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
423 burst-by-burst DTX logic?
8a45cd92e3c3 TCH-tap-modes: new article
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
424
8a45cd92e3c3 TCH-tap-modes: new article
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
425 TCH UL substitution: implemented PoC
8a45cd92e3c3 TCH-tap-modes: new article
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
426 ====================================
8a45cd92e3c3 TCH-tap-modes: new article
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
427
8a45cd92e3c3 TCH-tap-modes: new article
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
428 Back in 2016 we implemented a proof-of-concept TCH UL play feature in
8a45cd92e3c3 TCH-tap-modes: new article
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
429 FreeCalypso (only for TCH/FS and TCH/EFS), and the same PoC has been retained
8a45cd92e3c3 TCH-tap-modes: new article
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
430 when the overall TCH tap facility has been mainlined in late 2022. Having this
8a45cd92e3c3 TCH-tap-modes: new article
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
431 highly experimental (not fit for production use) TCH UL play code present in our
8a45cd92e3c3 TCH-tap-modes: new article
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
432 current production fw is deemed acceptable because this code will never be
8a45cd92e3c3 TCH-tap-modes: new article
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
433 invoked unless the user sends TCH_ULBITS_REQ packets to the running fw via
8a45cd92e3c3 TCH-tap-modes: new article
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
434 RVTMUX - and if you do send such packets (via tch play command in an fc-shell
8a45cd92e3c3 TCH-tap-modes: new article
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
435 session or by any other means), you are leaving the realm of production-approved
8a45cd92e3c3 TCH-tap-modes: new article
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
436 functionality and entering the realm of wild experimentation.
8a45cd92e3c3 TCH-tap-modes: new article
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
437
8a45cd92e3c3 TCH-tap-modes: new article
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
438 The PoC TCH UL play mechanism consists of a small buffer (holding up to 4 FR1 or
8a45cd92e3c3 TCH-tap-modes: new article
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
439 EFR frames) implemented in the ARM firmware; this buffer is filled by arriving
8a45cd92e3c3 TCH-tap-modes: new article
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
440 TCH_ULBITS_REQ packets and drained by the tchf_substitute_uplink() function
8a45cd92e3c3 TCH-tap-modes: new article
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
441 called from l1s_ctrl_tchtf(). Specifically, a flag named tch_ul_play_mode is
8a45cd92e3c3 TCH-tap-modes: new article
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
442 set when TCH_ULBITS_REQ input is received, telling l1s_ctrl_tchtf() to start
8a45cd92e3c3 TCH-tap-modes: new article
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
443 calling tchf_substitute_uplink() when (fn_report_mod13_mod4 == 3); the called
8a45cd92e3c3 TCH-tap-modes: new article
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
444 function drains an uplink frame from the ring buffer, writes it into the DSP's
8a45cd92e3c3 TCH-tap-modes: new article
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
445 a_du_1 buffer, sets B_PLAY_UL in d_tch_mode and sends a TCH_ULBITS_CONF packet
8a45cd92e3c3 TCH-tap-modes: new article
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
446 back to the host. If the ring buffer is empty, the function clears both
8a45cd92e3c3 TCH-tap-modes: new article
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
447 B_PLAY_UL and the firmware's tch_ul_play_mode flag, ending the special TCH UL
8a45cd92e3c3 TCH-tap-modes: new article
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
448 play mode.
8a45cd92e3c3 TCH-tap-modes: new article
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
449
8a45cd92e3c3 TCH-tap-modes: new article
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
450 This PoC mechanism is meant to be exercised with tch play command in an
8a45cd92e3c3 TCH-tap-modes: new article
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
451 interactive fc-shell session: this command reads an ASCII line-based uplink data
8a45cd92e3c3 TCH-tap-modes: new article
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
452 file and sends it to the firmware frame by frame, paced by TCH_ULBITS_CONF
8a45cd92e3c3 TCH-tap-modes: new article
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
453 packets from the target. The input to this command is a line-based ASCII hex
8a45cd92e3c3 TCH-tap-modes: new article
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
454 file similar to the format written by tch record, but simplified: each line is
8a45cd92e3c3 TCH-tap-modes: new article
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
455 just the 33-byte frame to be sent (in TI DSP buffer format, following GSM 05.03
8a45cd92e3c3 TCH-tap-modes: new article
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
456 interface 1), without any flags or status words or frame numbers.