FreeCalypso > hg > freecalypso-docs

annotate GTM900-design-guide @ 67:ed686a290f2d

Find changesets by keywords (author, files, the commit message), revision number or hash, or revset expression.
FC-handset-spec: LCD and backlight specification changes to ungate Venus board design
author Mychaela Falconia <falcon@freecalypso.org>
date Sat, 03 Jul 2021 07:01:39 +0000
parents 658010a51ff4
children
Ignore whitespace changes - Everywhere: Within whitespace: At end of lines:
rev   line source
30
658010a51ff4 GTM900-design-guide written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1 As of this writing (2020-09), the Mother's company Falconia Partners LLC is
658010a51ff4 GTM900-design-guide written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
2 actively in the process of bringing to market a new FreeCalypso hardware
658010a51ff4 GTM900-design-guide written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
3 solution based on our FC Tango module, and we also have an FTDI-based
658010a51ff4 GTM900-design-guide written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
4 (specifically FT2232D) adapter for connecting to Calypso UARTs (both of them)
658010a51ff4 GTM900-design-guide written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
5 and for controlling the Calypso module's PWON and RESET, allowing remote
658010a51ff4 GTM900-design-guide written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
6 control of Calypso power and boot in physically unattended environments.
658010a51ff4 GTM900-design-guide written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
7 However, this Tango-based solution is expected to become available some time
658010a51ff4 GTM900-design-guide written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
8 in 2020-12 (up to 3 months from now), and we realize that some people may not
658010a51ff4 GTM900-design-guide written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
9 be able to wait this long - some people may have an immediate need for some
658010a51ff4 GTM900-design-guide written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
10 working solution right now.
658010a51ff4 GTM900-design-guide written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
11
658010a51ff4 GTM900-design-guide written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
12 We are also aware that our European colleagues over at Sysmocom are working on
658010a51ff4 GTM900-design-guide written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
13 a competing solution based on the Huawei GTM900 Calypso modem module, but are
658010a51ff4 GTM900-design-guide written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
14 going totally the wrong way about it, and seem to be running into roadblocks
658010a51ff4 GTM900-design-guide written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
15 resulting from their earlier bad design choices. In light of this observed
658010a51ff4 GTM900-design-guide written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
16 situation, the present document has been put together to provide some guidance
658010a51ff4 GTM900-design-guide written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
17 to those who are currently misguided. If someone needs a working solution
658010a51ff4 GTM900-design-guide written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
18 right now, cannot wait another 3 months for our company to deliver our Tango-
658010a51ff4 GTM900-design-guide written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
19 based Caramel2+DUART28 solution, is looking at using GTM900 for the Calypso
658010a51ff4 GTM900-design-guide written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
20 module, and would be willing to use an FT2232x (either D or H) chip instead of
658010a51ff4 GTM900-design-guide written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
21 Sysmocom's poor choice of Silabs CP2105, this document will tell you exactly how
658010a51ff4 GTM900-design-guide written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
22 you should hook everything up in order to produce a guaranteed-working solution
658010a51ff4 GTM900-design-guide written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
23 without wasting time and energy on multiple design iterations.
658010a51ff4 GTM900-design-guide written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
24
658010a51ff4 GTM900-design-guide written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
25 FT2232x chip and EEPROM
658010a51ff4 GTM900-design-guide written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
26 =======================
658010a51ff4 GTM900-design-guide written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
27
658010a51ff4 GTM900-design-guide written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
28 Either FT2232D or FT2232H should work equally well, hence the choice between
658010a51ff4 GTM900-design-guide written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
29 the two is up to the board designer's preference. Our DUART28 adapter uses
658010a51ff4 GTM900-design-guide written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
30 FT2232D, and this choice was made primarily in the hope of easing the onerous
658010a51ff4 GTM900-design-guide written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
31 requirement of PCB controlled impedance (90 ohm differential) for USB traces:
658010a51ff4 GTM900-design-guide written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
32 FT2232H supports USB high speed, and this USB HS capability is thought to make
658010a51ff4 GTM900-design-guide written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
33 the controlled impedance requirement more stringent. Our competitor CP2105 has
658010a51ff4 GTM900-design-guide written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
34 no USB HS capability just like FT2232D, hence the latter was chosen to match.
658010a51ff4 GTM900-design-guide written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
35 But if the 90 ohm controlled impedance requirement is not a problem for you,
658010a51ff4 GTM900-design-guide written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
36 then by all means go ahead and use the newer and apparently more popular
658010a51ff4 GTM900-design-guide written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
37 FT2232H.
658010a51ff4 GTM900-design-guide written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
38
658010a51ff4 GTM900-design-guide written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
39 Whichever FT2232x chip you choose, you should include an EEPROM in your board
658010a51ff4 GTM900-design-guide written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
40 design. This EEPROM is officially optional per FTDI, but if you omit it, you
658010a51ff4 GTM900-design-guide written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
41 lose the ability to set a custom USB VID:PID. If you are only interested in
658010a51ff4 GTM900-design-guide written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
42 the two Calypso UARTs and don't need programmatic control of PWON and RESET,
658010a51ff4 GTM900-design-guide written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
43 then using the FT2232x chip's default USB VID:PID of 0x0403:0x6010 (with or
658010a51ff4 GTM900-design-guide written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
44 without an EEPROM) is perfectly fine. However, if you are going to do what I
658010a51ff4 GTM900-design-guide written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
45 recommend below in terms of using (otherwise unused) FT2232x Channel B RTS and
658010a51ff4 GTM900-design-guide written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
46 DTR outputs to control PWON and RESET, then you will need to apply a custom
658010a51ff4 GTM900-design-guide written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
47 patch to the Linux kernel's ftdi_sio driver (see freecalypso-hwlab Hg
658010a51ff4 GTM900-design-guide written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
48 repository) in order to make this mechanism practically usable. If you are
658010a51ff4 GTM900-design-guide written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
49 going to be applying any kind of custom patches to that ftdi_sio driver, having
658010a51ff4 GTM900-design-guide written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
50 a custom USB VID:PID will be very helpful in order to apply the needed quirks
658010a51ff4 GTM900-design-guide written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
51 conditionally, hence the EEPROM becomes necessary.
658010a51ff4 GTM900-design-guide written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
52
658010a51ff4 GTM900-design-guide written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
53 LEGAL NOTE: Falconia Partners LLC has received an official allocation of 8 PIDs
658010a51ff4 GTM900-design-guide written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
54 from FTDI out of FTDI's USB VID, but these USB IDs are _ONLY_ for hardware
658010a51ff4 GTM900-design-guide written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
55 products that are physically produced by Falconia Partners LLC - other parties
658010a51ff4 GTM900-design-guide written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
56 may not use these USB IDs without our explicit permission. Therefore, if you
658010a51ff4 GTM900-design-guide written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
57 are going to use a custom USB VID:PID, you will need to provide your own.
658010a51ff4 GTM900-design-guide written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
58
658010a51ff4 GTM900-design-guide written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
59 Dual UART signal connections
658010a51ff4 GTM900-design-guide written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
60 ============================
658010a51ff4 GTM900-design-guide written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
61
658010a51ff4 GTM900-design-guide written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
62 Unlike CP2105, the two channels of FT2232x are perfectly symmetric, hence the
658010a51ff4 GTM900-design-guide written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
63 choice of which FT2232x channel should be connected to which Calypso UART is
658010a51ff4 GTM900-design-guide written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
64 arbitrary. As the Mother of FreeCalypso, I very strongly encourage everyone to
658010a51ff4 GTM900-design-guide written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
65 use this convention: Calypso MODEM UART (the one for which Huawei brought out 8
658010a51ff4 GTM900-design-guide written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
66 wires with full modem control) should be connected to FT2232x Channel A, and
658010a51ff4 GTM900-design-guide written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
67 Calypso IrDA UART (the one for which there are only two wires) should be
658010a51ff4 GTM900-design-guide written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
68 connected to FT2232x Channel B.
658010a51ff4 GTM900-design-guide written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
69
658010a51ff4 GTM900-design-guide written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
70 If you are going for the lowest cost in terms of component count and PCB real
658010a51ff4 GTM900-design-guide written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
71 estate, it is perfectly acceptable to connect FT2232x I/O pins directly to
658010a51ff4 GTM900-design-guide written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
72 Calypso UART pins. Yes, FT2232x outputs operate at 3.3V and cannot be brought
658010a51ff4 GTM900-design-guide written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
73 down to Calypso native 2.8V, but if you read TI Calypso datasheets (document
658010a51ff4 GTM900-design-guide written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
74 CAL000/A in particular), is says quite clearly that input voltages of up to
658010a51ff4 GTM900-design-guide written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
75 VDDS+0.5V are acceptable, i.e., the inputs are tolerant of 3.3V. This situation
658010a51ff4 GTM900-design-guide written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
76 becomes a little less than ideal during Calypso sleep modes (the higher voltage
658010a51ff4 GTM900-design-guide written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
77 feeds into the chipset's V-IO rail and brings that rail a little higher than
658010a51ff4 GTM900-design-guide written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
78 normal), but engineering is all about trade-offs and compromises, and sometimes
658010a51ff4 GTM900-design-guide written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
79 it is necessary to trade off between perfection and cost.
658010a51ff4 GTM900-design-guide written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
80
658010a51ff4 GTM900-design-guide written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
81 If you do wish to feed proper 2.8V signals to the Calypso instead of 3.3V, the
658010a51ff4 GTM900-design-guide written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
82 easiest way to do so would be to insert LVC buffers into signal paths from
658010a51ff4 GTM900-design-guide written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
83 FT2232x outputs to Calypso UART inputs. Power the LVC buffer IC from the
658010a51ff4 GTM900-design-guide written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
84 Calypso+Iota chipset's V-IO rail, which Huawei brought out on an interface pin
658010a51ff4 GTM900-design-guide written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
85 they named "VDD". There will be no problem with partial power-down conditions
658010a51ff4 GTM900-design-guide written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
86 (USB on, Calypso off) because LVC buffers are specifically designed for such
658010a51ff4 GTM900-design-guide written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
87 operation and have very low Ioff specs in the uA range.
658010a51ff4 GTM900-design-guide written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
88
658010a51ff4 GTM900-design-guide written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
89 Our DUART28 adapter also includes another LVC buffer going the other way, in
658010a51ff4 GTM900-design-guide written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
90 the path from Calypso UART outputs to FT2232x inputs, but it is included for
658010a51ff4 GTM900-design-guide written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
91 only one reason: in order to gracefully support the other partial power-down
658010a51ff4 GTM900-design-guide written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
92 scenario of Calypso up and running, but no USB host connected and thus no USB
658010a51ff4 GTM900-design-guide written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
93 power. If this latter scenario is not a concern for your application, then
658010a51ff4 GTM900-design-guide written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
94 there is absolutely no problem with connecting Calypso UART outputs directly to
658010a51ff4 GTM900-design-guide written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
95 FT2232x inputs without any buffers.
658010a51ff4 GTM900-design-guide written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
96
658010a51ff4 GTM900-design-guide written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
97 Controlling PWON and RESET
658010a51ff4 GTM900-design-guide written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
98 ==========================
658010a51ff4 GTM900-design-guide written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
99
658010a51ff4 GTM900-design-guide written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
100 FT2232x RTS and DTR outputs are normally CMOS high (RS-232 inactive) when no
658010a51ff4 GTM900-design-guide written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
101 one is poking at them, but the standard Linux kernel ftdi_sio driver (following
658010a51ff4 GTM900-design-guide written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
102 POSIX stipulations, apparently) unconditionally makes them both CMOS low
658010a51ff4 GTM900-design-guide written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
103 (RS-232 active) when the ttyUSBx device is opened. If you look in our
658010a51ff4 GTM900-design-guide written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
104 freecalypso-hwlab Hg repository, you will find a patch to this driver (a quirk
658010a51ff4 GTM900-design-guide written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
105 conditionalized on a custom USB VID:PID) that suppresses this automatic
658010a51ff4 GTM900-design-guide written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
106 assertion of RTS & DTR on ttyUSBx device open, allowing userspace applications
658010a51ff4 GTM900-design-guide written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
107 to control them explicitly with TIOCMBIS and TIOCMBIC ioctls.
658010a51ff4 GTM900-design-guide written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
108
658010a51ff4 GTM900-design-guide written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
109 Our upcoming Caramel2+DUART28 solution will include an optional (one may connect
658010a51ff4 GTM900-design-guide written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
110 the needed jumper wires or leave them unconnected) provision for controlling
658010a51ff4 GTM900-design-guide written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
111 the Calypso+Iota chipset's PWON and RESET with otherwise unused FT2232 Channel B
658010a51ff4 GTM900-design-guide written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
112 RTS & DTR outputs. The arrangement we have implemented is that when ChanB RTS
658010a51ff4 GTM900-design-guide written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
113 is asserted (CMOS low, TIOCMBIS), Calypso PWON is triggered, and when ChanB DTR
658010a51ff4 GTM900-design-guide written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
114 is asserted, Calypso RESET is triggered. We recommend that others follow the
658010a51ff4 GTM900-design-guide written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
115 same convention.
658010a51ff4 GTM900-design-guide written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
116
658010a51ff4 GTM900-design-guide written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
117 PWON wiring
658010a51ff4 GTM900-design-guide written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
118 -----------
658010a51ff4 GTM900-design-guide written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
119
658010a51ff4 GTM900-design-guide written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
120 The Calypso+Iota chipset's (Iota really) PWON input is internally pulled up to
658010a51ff4 GTM900-design-guide written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
121 raw VBAT, thus it must not be connected directly to any ordinary 3.3V or 2.8V
658010a51ff4 GTM900-design-guide written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
122 logic - instead it needs to be driven with an OC or OD buffer. If it is to be
658010a51ff4 GTM900-design-guide written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
123 controlled with ChanB RTS (FT2232x BDBUS2 output), the ideal circuit is a simple
658010a51ff4 GTM900-design-guide written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
124 non-inverting OD buffer such as Nexperia 74LVC1G07; the OD buffer IC's Vdd
658010a51ff4 GTM900-design-guide written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
125 supply should be connected to the FT2232x chip's 3.3V I/O supply rail.
658010a51ff4 GTM900-design-guide written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
126
658010a51ff4 GTM900-design-guide written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
127 RESET wiring
658010a51ff4 GTM900-design-guide written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
128 ------------
658010a51ff4 GTM900-design-guide written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
129
658010a51ff4 GTM900-design-guide written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
130 The RESET input is different between Huawei GTM900 and FC Tango modules. On FC
658010a51ff4 GTM900-design-guide written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
131 Tango it is raw Iota nTESTRESET and thus needs to be driven in the same way as
658010a51ff4 GTM900-design-guide written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
132 PWON described above, but GTM900 internally incorporates the JTAG reset circuit
658010a51ff4 GTM900-design-guide written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
133 depicted on TI's Leonardo schematics, and the RESET signal they bring out is
658010a51ff4 GTM900-design-guide written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
134 what we (FreeCalypso) call XDS_RESET - see the Calypso-test-reset article. It
658010a51ff4 GTM900-design-guide written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
135 is acceptable to drive XDS_RESET with an OC/OD driver just like PWON or raw
658010a51ff4 GTM900-design-guide written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
136 nTESTRESET, but this OC/OD driver becomes optional with XDS_RESET - thanks to
658010a51ff4 GTM900-design-guide written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
137 the transistor circuit inside the GTM900 module, it is perfectly acceptable to
658010a51ff4 GTM900-design-guide written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
138 wire FT2232x BDBUS4 output (ChanB DTR) directly to GTM900 RST input, and it will
658010a51ff4 GTM900-design-guide written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
139 work per our convention, triggering a reset when ChanB DTR is asserted.
658010a51ff4 GTM900-design-guide written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
140
658010a51ff4 GTM900-design-guide written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
141 The XDS_RESET transistor circuit inside GTM900 does have one unpleasant side
658010a51ff4 GTM900-design-guide written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
142 effect though: on modules like FC Tango that bring out raw nTESTRESET, that
658010a51ff4 GTM900-design-guide written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
143 reset includes a built-in Switch-ON function, and PWON effectively becomes
658010a51ff4 GTM900-design-guide written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
144 optional - one can fully control the module using only RESET and soft poweroff
658010a51ff4 GTM900-design-guide written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
145 - but the same does NOT hold on GTM900. XDS_RESET may or may not work (no
658010a51ff4 GTM900-design-guide written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
146 guarantees) when the Calypso+Iota chipset is in VRPC switched-off state, thus
658010a51ff4 GTM900-design-guide written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
147 one must do a switch-on with PWON first, and then drive a reset if necessary.
658010a51ff4 GTM900-design-guide written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
148 And no, driving XDS_RESET with an OC/OD buffer won't do anything to eliminate
658010a51ff4 GTM900-design-guide written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
149 this unpleasant side effect - you just have to live with it for as long as you
658010a51ff4 GTM900-design-guide written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
150 use GTM900 modules and not FC Tango.