--- a/MEMIF-wait-states	Sat Nov 09 23:45:15 2019 +0000
+++ b/MEMIF-wait-states	Sun Nov 10 01:26:11 2019 +0000
@@ -7,6 +7,10 @@
 
 ftp://ftp.freecalypso.org/pub/GSM/Calypso/cal000_a.pdf
 
+as well as this more recently discovered newer version:
+
+ftp://ftp.freecalypso.org/pub/GSM/Calypso/cal000_a_v0.8.pdf
+
 When running on a Calypso C035 target, our TCS211 reference fw as well as most
 vendor firmwares we've examined run the ARM7 core at its maximum clock frequency
 of 52 MHz.  These same firmwares typically configure WS=3 for both flash and
@@ -17,10 +21,17 @@
 19.23 ns * 4 = 76.92 ns, thus it should be OK for 70 ns memories, right?  Not
 so fast: as shown in the formula on cal000_a.pdf page 11 and can be seen from
 the timing diagrams, two other timing parameters (tda and tsu) also need to be
-factored in.  The sum of tda+tsu for 2.8V MEMIF as given in the only document
-we have available is 10.5 ns, thus if we run the ARM7 core at 52 MHz and set
-WS=3, the available safe window for memory access time is only about 66 ns,
-which is 4 ns short of the 70 ns flash and RAM access time specs.
+factored in.  The sum of tda+tsu for 2.8V MEMIF as given in the CAL000/A v0.2
+document is 10.5 ns, thus if we run the ARM7 core at 52 MHz and set WS=3, the
+available safe window for memory access time is only about 66 ns, which is 4 ns
+short of the 70 ns flash and RAM access time specs.
+
+The more recently discovered version 0.8 of this same CAL000/A document
+indicates that the tables for 2.8V and 1.8V MEMIF were erroneously swapped in
+the older version, and the new correct tda+tsu number for 2.8V MEMIF now appears
+to be 8.0 ns rather than 10.5 ns.  The available safe window for memory access
+time with WS=3 thus becomes 68.92 ns - this new figure is much closer to 70 ns,
+but it is still a negative margin, short by 1.08 ns.
 
 TI's reference fw setting of WS=3 in conjuction with ARM7 running at 52 MHz has
 made its way into the official firmwares of Openmoko devices and several Compal
@@ -30,8 +41,9 @@
 suffix meaning 70 ns access time for flash and 55 ns for RAM), and in the case
 of Compal phones it is highly unlikely that they used flash chips faster than
 70 ns, thus we have strong evidence that the access time spec is being violated
-by about 4 ns.  It works in practice because the official specs are guaranteed
-worst-case numbers, but it is still wrong in the strict sense.
+by about 1.1 ns.  It works in practice because the official specs are guaranteed
+worst-case numbers and the shortcoming is very small, but it is still wrong in
+the strict sense.
 
 We have strong evidence that this WS=3 setting comes from TI's mainline
 reference fw, as opposed to being customized by or for Openmoko or Compal.
@@ -90,13 +102,13 @@
 
 I further hypothetize that the above MEMIF settings were likely cast into code
 in the days of Calypso C05, and that the WS=3 setting was computed when the
-ARM7 core ran at 39 MHz.  The combination of ARM7 at 39 MHz, WS=3 and the same
-tda+tsu = 10.5 ns adjustment from the available cal000_a.pdf document
+ARM7 core ran at 39 MHz.  The combination of ARM7 at 39 MHz, WS=3 and the more
+generous tda+tsu = 10.5 ns adjustment from the older cal000_a.pdf document
 (officially corresponding to Calypso C035 F751774) gives an access time of
 92 ns, which is very sensible.  The hypothesis further goes that later TI moved
 to Calypso C035 silicon and started running the ARM7 core at 52 MHz, but the WS
 setting was never changed (overlooked), and the 92 ns access time turned into a
-mere 66 ns.  The latter works with 70 ns memories in practice despite being
+mere 68.92 ns.  The latter works with 70 ns memories in practice despite being
 strictly incorrect (negative margin), and so the error escaped notice.
 
 Solution adopted for FreeCalypso