# HG changeset patch
# User Mychaela Falconia <falcon@freecalypso.org>
# Date 1561848318 0
# Node ID 6d02f30e35addec6d6922ffd01cb97ac8137c86f
# Parent  66879ce73b3ef8bb4fc25d1719a90436ba996037
doc/Calypso-OpenOCD-Howto: noted lack of performance optimizations

diff -r 66879ce73b3e -r 6d02f30e35ad doc/Calypso-OpenOCD-Howto
--- a/doc/Calypso-OpenOCD-Howto	Wed Jun 26 23:04:26 2019 +0000
+++ b/doc/Calypso-OpenOCD-Howto	Sat Jun 29 22:45:18 2019 +0000
@@ -105,7 +105,7 @@
 mysterious 0xB instruction and DR scan that are needed in order to enable halts
 on TI's modified version of the ARM7TDMI core.  Once you have halted as above,
 you can resume and halt again without needing to re-execute the enable_halt
-step; the only time when the enable_halt steps will need to be repeated is when
+step; the only time when the enable_halt step will need to be repeated is when
 the Calypso is reset.
 
 You can safely halt the Calypso in this manner when the flash is blank and the
@@ -164,9 +164,10 @@
 It will be up to you to design whatever circuit you wish to use to produce an
 OC/OD driver that can be triggered from OpenOCD, but connecting RPWON aka DLPWR
 directly to an FT2232x I/O pin is not acceptable.  Copying the circuit from
-TI/FC development boards that propagates XDS_RESET into nTESTRESET won't work:
-this circuit only works when the V-IO regulator is already on, but RPWON is not
-a reset and will need to be triggered when the chipset is fully "cold".
+TI/FC development boards that propagates XDS_RESET into nTESTRESET won't work
+either: this circuit only works when the V-IO regulator is already on, but
+RPWON is not a reset and will need to be triggered when the chipset is fully
+"cold".
 
 You will also need to figure out the appropriate timing.  You will need to
 insert a certain delay between RPWON assertion and the 'jtag arp_init' step in
@@ -189,3 +190,19 @@
 
 The boot ROM will run while fc-loadtool is sending its beacons, fc-loadtool
 will load and run loadagent, and you can then recover the flash.
+
+Lack of performance optimizations
+=================================
+
+Our PoC OpenOCD-on-Calypso config does not set up a work area (an area of
+system RAM that is declared as a scratchpad for OpenOCD), nor does it enable
+arm7_9 dcc_downloads or arm7_9 fast_memory_access.  These omissions are
+intentional, as those performance optimizations are outside of the scope of
+what I set out to do, which is to prove Calypso JTAG as working and provide a
+"golden reference" setup.
+
+If you wish to set up an area in Calypso IRAM as a work area for OpenOCD, which
+is a prerequisite for arm7_9 dcc_downloads, you will need to choose the location
+based on your specific application - whether a given area will be suitable or
+not will depend on exactly what you are debugging and exactly what you are
+trying to do, which is once again outside of the scope of this PoC.