FreeCalypso > hg > freecalypso-reveng
annotate frbl/reconst/boot.c @ 382:4307b57229d3
miscprog: tone-convert written, compiles
author | Mychaela Falconia <falcon@freecalypso.org> |
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date | Wed, 10 Nov 2021 00:04:12 +0000 |
parents | 4e1d7ce0ee71 |
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rev | line source |
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frbl/reconst/boot.c: import from TI's FLUID package
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1 /****************************************************************************** |
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2 * FLUID (Flash Loader Utility Independent of Device) |
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3 * |
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4 * (C) Delta Technologies 2001. |
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5 * Cleanup, modifications and extensions by Mads Meisner-Jensen, mmj@ti.com. |
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6 * |
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7 * Target Bootloader |
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8 * |
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9 * $Id: boot.c 1.18 Mon, 28 Apr 2003 08:49:16 +0200 tsj $ |
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10 * |
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11 ******************************************************************************/ |
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12 |
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13 #include "chipset.cfg" |
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14 #include "target.h" |
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15 |
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16 |
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17 #define DEBUG_TRACE 0 |
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18 |
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19 |
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20 // Protocol version of this bootloader |
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21 |
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22 // Version 0: Original, unmodified Delta Technology Bootloader. |
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23 |
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24 // Version 1: First Fluid Bootloader. 'B'audrate command and 'V'ersion |
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25 // command. Backward compatibly with version 0. |
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26 |
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27 // Version 2: 'H'ardware chipset query command. Debug/Trace |
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28 // functionality. Backward compatibly with version 0, 1. Fixed bug where |
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29 // IND$CALL was used to start command interpreter instead of private jump() |
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30 // function |
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31 |
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32 // Version 3: Generic 'Q'uery command. Discontinued 'H'ardware query command |
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33 // from version 2. |
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34 |
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35 #define BOOTLOADER_VERSION '3' |
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36 |
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37 |
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38 /****************************************************************************** |
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39 * Bootstrap/Init |
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40 ******************************************************************************/ |
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41 |
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42 // Initialize stackpointer according to chipset. Note that we ALWAYS do |
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43 // this, no matter if we were laoded with JTAG or if we were compiled-in. |
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44 |
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45 #if (CHIPSET == 3) |
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46 asm("STACK_INIT .equ 03000000h"); |
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47 asm("STACK_ADD .equ 00020000h ; 128kB"); |
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48 #elif (CHIPSET == 7 || CHIPSET == 8 || CHIPSET == 10 || CHIPSET == 11) |
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49 asm("STACK_INIT .equ 00800000h"); |
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50 asm("STACK_ADD .equ 00020000h ; 128kB"); |
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51 #elif (CHIPSET == 12) |
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52 asm("STACK_INIT .equ 08000000h"); |
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53 asm("STACK_ADD .equ 00020000h ; 128kB"); |
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54 #else |
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55 #error Unknown target hardware selected |
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56 #endif |
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57 |
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58 #ifdef FLUID_BOOT_STAND_ALONE |
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59 asm(" .def _c_int00 "); |
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60 asm("_c_int00:"); |
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61 #endif |
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62 |
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63 asm(" .state32 "); |
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64 asm(" mov sp,#STACK_INIT"); |
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65 asm(" add sp,sp,#STACK_ADD"); |
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66 asm(" adr lr,start_end + 1 ; module end address with lsb set"); |
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67 asm(" bx lr ; branch to start"); |
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68 asm(" nop"); |
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69 asm("start_end:"); |
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70 |
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71 |
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72 |
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73 /****************************************************************************** |
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74 * Main |
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75 ******************************************************************************/ |
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76 |
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77 uint32 uart_base; |
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78 |
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79 void jump(uint32, uint32); |
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80 |
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81 static void putchar(uint8 ch); |
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82 uint8 getchar(void); |
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83 void uart_init(UBYTE dlh, UBYTE dll); |
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84 void hardware_init(uint16 *code); |
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85 |
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86 void fluid_bootloader(void) |
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87 { |
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88 uint8 ch; |
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89 uint16 *mem; |
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90 union32_t addr; |
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91 union16_t size; |
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92 union16_t data; |
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93 uint8 uart_dlh, uart_dll; |
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94 uint16 chip_id_code; |
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95 |
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96 hardware_init(&chip_id_code); |
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97 |
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98 uart_base = UART_BASE_MODEM; |
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99 uart_init(0, 0x07); // baudrate = 115200kbps |
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100 uart_base = UART_BASE_IRDA; |
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101 uart_init(0, 0x07); // baudrate = 115200kbps |
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102 |
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103 #ifdef TESTBOOT |
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104 while (1) { |
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105 uart_base = UART_BASE_MODEM; |
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106 if ((REGISTER_8_READ(uart_base + UART_LSR) & STAT_RXRDY)) |
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107 break; |
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108 uart_base = UART_BASE_IRDA; |
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109 if ((REGISTER_8_READ(uart_base + UART_LSR) & STAT_RXRDY)) |
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110 break; |
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111 } |
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112 while (getchar() != 0xAA) |
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113 ; |
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114 while (getchar() != 0x01) |
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115 ; |
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116 while (getchar() != 0xDD) |
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117 ; |
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118 #endif |
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119 |
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120 while (1) { |
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121 uart_base = UART_BASE_MODEM; |
315
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122 putchar(PROTO_HELLO); |
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123 if ((REGISTER_8_READ(uart_base + UART_LSR) & STAT_RXRDY)) |
315
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124 break; |
318
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125 uart_base = UART_BASE_IRDA; |
315
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126 putchar(PROTO_HELLO); |
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127 if ((REGISTER_8_READ(uart_base + UART_LSR) & STAT_RXRDY)) |
315
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128 break; |
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129 } |
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130 while (1) { |
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131 ch = getchar(); |
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132 switch (ch) { |
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133 case PROTO_VERSION: |
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134 putchar(BOOTLOADER_VERSION); |
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135 break; |
318
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136 /* FreeCalypso reconstruction of TCS211 boot.obj */ |
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137 case PROTO_HARDWARE: |
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138 putchar('0'); |
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139 break; |
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140 /* end FC reconstruction */ |
315
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141 case PROTO_QUERY: |
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142 ch = getchar(); |
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143 if (ch == PROTO_QUERY_CHIP) { |
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144 data.i = chip_id_code; |
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145 putchar(data.b[0]); |
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146 putchar(data.b[1]); |
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147 putchar(0); |
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148 putchar(0); |
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149 } |
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150 else { |
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151 putchar(PROTO_ERROR); |
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152 } |
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153 break; |
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154 case PROTO_BAUDRATE: |
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155 ch = getchar(); // Get DLH |
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156 case 0: |
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157 uart_init(ch, getchar()); |
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158 break; |
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159 case PROTO_DOWNLOAD: |
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160 addr.b[0] = getchar(); |
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161 addr.b[1] = getchar(); |
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162 addr.b[2] = getchar(); |
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163 addr.b[3] = getchar(); |
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164 size.b[0] = getchar(); |
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165 size.b[1] = getchar(); |
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166 putchar(PROTO_READY); |
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167 mem = (uint16 *) addr.i; |
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168 while (size.i--) { |
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169 // Data bytes arrive in reverse order due to little endian mode |
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170 data.b[1] = getchar(); |
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171 data.b[0] = getchar(); |
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172 *mem++ = data.i; |
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173 } |
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174 |
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175 #if DEBUG_TRACE |
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176 // Insert convenient tracing here... |
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177 #endif |
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178 // Start the program we loaded. |
318
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179 jump(uart_base, addr.i); |
315
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180 break; |
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181 default: |
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182 putchar(PROTO_ERROR); |
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183 } |
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184 } |
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185 } |
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186 |
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187 // Little assembly function that makes a jump to the address/argument, |
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188 // similar to the compiler's IND$CALL. We do not use the compiler's IND$CALL |
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189 // because when we compile for non-standalone, IND$CALL is already |
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190 // defined. We expect that the base address of the UART is in R0, so it can |
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191 // be properly passed on to the command interpreter. |
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192 asm("$jump:"); |
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193 asm(" bx r1"); |
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194 |
318
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317
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195 static void putchar(uint8 ch) |
315
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196 { |
318
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197 PUTCHAR_FUNCTION_CODE(uart_base) |
315
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198 } |
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199 |
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200 uint8 getchar(void) |
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201 { |
318
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202 GETCHAR_FUNCTION_CODE(uart_base) |
315
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203 } |
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204 |
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205 |
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206 /****************************************************************************** |
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207 * Initialization |
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208 ******************************************************************************/ |
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209 #if (CHIPSET == 3) |
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210 #define IQ_MASK (0xFFFFFA02) /* Mask Interrupt Register */ |
316
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315
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211 #elif (CHIPSET == 7 || CHIPSET == 8 || CHIPSET == 10 || CHIPSET == 11) \ |
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212 || (CHIPSET == 12) |
315
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213 #define IQ_MASK1 (0xFFFFFA08) /* Mask Interrupt Register 1 */ |
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214 #define IQ_MASK2 (0xFFFFFA0A) /* Mask Interrupt Register 2 */ |
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215 #else |
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216 #error Unknown target hardware selected |
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217 #endif |
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218 |
317
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diff
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219 /* FreeCalypso reconstruction: definition missing from TCS211 target.h */ |
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220 #define CHIP_ID_CODE 0xFFFEF000 |
315
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221 |
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222 void hardware_init(uint16 *chip_id_code) |
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223 { |
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224 uint16 clk; |
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225 char chip_set = 0; |
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226 |
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227 // We read the chipset version directly from the hardware because |
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228 // otherwise the stand-alone bootloader (to be downloaded with JTAG) is |
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229 // obviously not target independent! |
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230 *chip_id_code = *((volatile uint16 *) CHIP_ID_CODE); |
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231 |
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232 |
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233 // We should only intialize the hardware if we were downloaded with JTAG |
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234 |
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235 #ifdef FLUID_BOOT_STAND_ALONE |
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236 |
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237 // FIXME: we should perhaps have different init depending on chipset |
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238 // detected? |
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239 |
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240 // Mask all interrupts |
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241 #if (CHIPSET == 3) |
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242 *((volatile uint16 *) IQ_MASK) = 0xFFFF; |
316
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243 #elif (CHIPSET == 7 || CHIPSET == 8 || CHIPSET == 10 || CHIPSET == 11) |
315
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244 *((volatile uint16 *) IQ_MASK1) = 0xFFFF; |
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245 *((volatile uint16 *) IQ_MASK2) = 0x001F; |
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246 #elif (CHIPSET == 12) |
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247 *((volatile uint16 *) IQ_MASK1) = 0xFFFF; |
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248 *((volatile uint16 *) IQ_MASK2) = 0xFFFF; //BJO Check IRQ_29_MSK - should it be 0 ? |
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249 #endif |
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250 |
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251 // Disable watchdog timer |
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252 *((volatile uint16 *) WATCHDOG_TIM_MODE) = 0xF5; |
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253 *((volatile uint16 *) WATCHDOG_TIM_MODE) = 0xA0; |
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254 #if (CHIPSET == 12) //BJO Check this (documented?) |
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255 *((volatile uint16 *) WATCHDOG_TIM_MODE+80) = 0xF5; // Secure watchdog CALPLUS |
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256 *((volatile uint16 *) WATCHDOG_TIM_MODE+80) = 0xA0; // Secure watchdog CALPLUS |
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257 #endif |
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258 |
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259 |
316
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260 #if (CHIPSET == 3) || (CHIPSET == 7 || CHIPSET == 8 || CHIPSET == 10 || CHIPSET == 11) |
315
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261 // FIXME: Describe exactly how the CSs are initialized |
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262 *((volatile uint16 *) CS0_MEM_REG) = 0x2A1; |
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263 *((volatile uint16 *) CS1_MEM_REG) = 0x2A1; |
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264 *((volatile uint16 *) CS2_MEM_REG) = 0x2A1; |
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265 *((volatile uint16 *) CS3_MEM_REG) = 0x283; |
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266 *((volatile uint16 *) CS4_MEM_REG) = 0x283; |
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267 *((volatile uint16 *) CS6_MEM_REG) = 0x2C0; |
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268 #elif (CHIPSET == 12) |
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269 *((volatile uint16 *) CS0_MEM_REG) = 0x2A3; //*BJO Check these settings |
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270 *((volatile uint16 *) CS1_MEM_REG) = 0x2A3; |
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271 *((volatile uint16 *) CS2_MEM_REG) = 0x2A3; |
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272 *((volatile uint16 *) CS3_MEM_REG) = 0x2A3; |
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273 *((volatile uint16 *) CS4_MEM_REG) = 0x2A3; |
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274 *((volatile uint16 *) CS5_MEM_REG) = 0x2A3; |
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275 #endif |
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276 |
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277 |
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278 #if (CHIPSET == 3) |
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279 clk = *(volatile uint16 *) CLKM_CNTL_ARM_CLK; |
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280 clk &= ~(0x0C | 0x30); |
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281 clk |= (2 << 4); |
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282 *(volatile uint16 *) CLKM_CNTL_ARM_CLK = clk; |
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283 |
316
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284 #elif (CHIPSET == 7 || CHIPSET == 8 || CHIPSET == 10 || CHIPSET == 11) |
315
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285 |
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286 // Reset DPLL register |
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287 * (volatile uint16 *) MEM_DPLL_ADDR = DPLL_RESET_VALUE; |
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288 |
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289 // Wait that DPLL is in BYPASS mode |
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290 while (((* (volatile uint16 *) MEM_DPLL_ADDR) & 1) != 1) |
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291 ; |
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292 |
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293 // Reset CLKM register |
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294 *(volatile uint16 *) MEM_CLKM_ADDR = CLKM_CNTL_ARM_CLK_RST; |
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295 |
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296 #elif (CHIPSET == 12) |
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297 |
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298 *((volatile uint8*)CTNL_CLK) = 0x91; // Make sure we are set to 26MHz mode (div 2) // CALPLUS |
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299 *((volatile uint16 *) MEM_DPLL_ADDR) = 0x6012 | (8<<7) | (1<<5); // multiplyer=8, divider=2 (-1) 52MHz!!! // CALPLUS |
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300 // Wait that DPLL is locked |
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301 while (((* (volatile unsigned short *) MEM_DPLL_ADDR) & 1) != 1) ; // CALPLUS |
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302 |
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303 #endif |
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304 |
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305 |
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306 #endif // ifdef FLUID_BOOT_STAND_ALONE |
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307 } |
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308 |
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309 void uart_init(uint8 my_dlh, uint8 my_dll) |
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310 { |
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311 uint8 ch; |
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312 |
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313 /* |
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314 * Transition from the DSP Rhea bus to the MCU Rhea bus. |
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315 */ |
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316 BIT_SET (UART_UIR, UART_MASK_IT); |
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317 BIT_CLR (UART_UIR, UART_ACCESS); |
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318 BIT_CLR (UART_UIR, UART_MASK_IT); |
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319 |
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320 /* |
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321 * Set the UART in reset mode. |
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322 */ |
318
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323 REGISTER_8_WRITE(uart_base + UART_MDR1, CMD_UART_RESET); |
315
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324 |
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325 /* |
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326 * FIFO configuration |
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327 */ |
318
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328 REGISTER_8_WRITE(uart_base + UART_LCR, CMD_EFR_EN); |
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329 BIT_SET (uart_base + UART_EFR, ENHANCED_EN); |
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330 REGISTER_8_WRITE(uart_base + UART_LCR, CMD_FCR_MCR_EN); |
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331 REGISTER_8_WRITE(uart_base + UART_FCR, CMD_FIFO_EN); |
315
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332 |
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333 /* |
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334 * Speed configuration |
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335 */ |
318
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336 REGISTER_8_WRITE(uart_base + UART_LCR, CMD_EFR_EN); |
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337 REGISTER_8_WRITE(uart_base + UART_DLL, my_dll); |
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338 REGISTER_8_WRITE(uart_base + UART_DLH, my_dlh); |
315
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339 |
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340 /* |
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341 * Character format configuration |
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342 */ |
318
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343 REGISTER_8_WRITE(uart_base + UART_LCR, CMD_CHAR8_STOP1_NOPAR); |
315
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344 |
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345 /* |
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346 * Modem configuration |
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347 */ |
318
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348 REGISTER_8_WRITE(uart_base + UART_MDR1, CMD_UART_MODE); |
315
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349 |
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350 /* |
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351 * Flush Rx buffer |
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352 */ |
318
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353 while ((REGISTER_8_READ(uart_base + UART_LSR) & STAT_RXRDY)) |
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354 ch = (REGISTER_8_READ(uart_base + UART_RHR)); |
315
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355 } |
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356 |
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357 |
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358 /****************************************************************************** |
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359 * Debug |
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360 ******************************************************************************/ |
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361 |
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362 #if (DEBUG_TRACE == 1) |
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363 #include "debug.c" |
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364 #endif |
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365 |