FreeCalypso > hg > freecalypso-reveng

annotate frbl/reconst/inc/target.h @ 312:6cba849e3332

Find changesets by keywords (author, files, the commit message), revision number or hash, or revset expression.
frbl/reconst/inc: import from TCS211 surviving source
author Mychaela Falconia <falcon@freecalypso.org>
date Wed, 04 Mar 2020 23:06:07 +0000
parents
children
Ignore whitespace changes - Everywhere: Within whitespace: At end of lines:
rev   line source
312
6cba849e3332 frbl/reconst/inc: import from TCS211 surviving source
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1 /******************************************************************************
6cba849e3332 frbl/reconst/inc: import from TCS211 surviving source
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
2 * FLUID (Flash Loader Utility Independent of Device)
6cba849e3332 frbl/reconst/inc: import from TCS211 surviving source
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
3 *
6cba849e3332 frbl/reconst/inc: import from TCS211 surviving source
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
4 * (C) Delta Technologies 2001.
6cba849e3332 frbl/reconst/inc: import from TCS211 surviving source
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
5 * Cleanup, modifications and extensions by Mads Meisner-Jensen, mmj@ti.com.
6cba849e3332 frbl/reconst/inc: import from TCS211 surviving source
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
6 *
6cba849e3332 frbl/reconst/inc: import from TCS211 surviving source
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
7 * Target common definitions
6cba849e3332 frbl/reconst/inc: import from TCS211 surviving source
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
8 *
6cba849e3332 frbl/reconst/inc: import from TCS211 surviving source
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
9 * $Id: target.h,v 1.3 2003/07/10 17:50:21 rlendenmann Exp $
6cba849e3332 frbl/reconst/inc: import from TCS211 surviving source
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
10 *
6cba849e3332 frbl/reconst/inc: import from TCS211 surviving source
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
11 ******************************************************************************/
6cba849e3332 frbl/reconst/inc: import from TCS211 surviving source
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
12 #ifndef __TARGET_H__
6cba849e3332 frbl/reconst/inc: import from TCS211 surviving source
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
13 #define __TARGET_H__
6cba849e3332 frbl/reconst/inc: import from TCS211 surviving source
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
14 #include "protocol.h"
6cba849e3332 frbl/reconst/inc: import from TCS211 surviving source
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
15
6cba849e3332 frbl/reconst/inc: import from TCS211 surviving source
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
16
6cba849e3332 frbl/reconst/inc: import from TCS211 surviving source
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
17 /******************************************************************************
6cba849e3332 frbl/reconst/inc: import from TCS211 surviving source
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
18 * Typedefs and Prototypes
6cba849e3332 frbl/reconst/inc: import from TCS211 surviving source
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
19 ******************************************************************************/
6cba849e3332 frbl/reconst/inc: import from TCS211 surviving source
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
20
6cba849e3332 frbl/reconst/inc: import from TCS211 surviving source
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
21 #ifndef RIVIERA_INCLUDED
6cba849e3332 frbl/reconst/inc: import from TCS211 surviving source
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
22 typedef unsigned char UBYTE;
6cba849e3332 frbl/reconst/inc: import from TCS211 surviving source
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
23 typedef unsigned short UINT16;
6cba849e3332 frbl/reconst/inc: import from TCS211 surviving source
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
24 typedef unsigned long UINT32;
6cba849e3332 frbl/reconst/inc: import from TCS211 surviving source
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
25 typedef signed char INT8;
6cba849e3332 frbl/reconst/inc: import from TCS211 surviving source
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
26 typedef signed short INT16;
6cba849e3332 frbl/reconst/inc: import from TCS211 surviving source
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
27 typedef signed long INT32;
6cba849e3332 frbl/reconst/inc: import from TCS211 surviving source
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
28 #endif
6cba849e3332 frbl/reconst/inc: import from TCS211 surviving source
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
29
6cba849e3332 frbl/reconst/inc: import from TCS211 surviving source
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
30 typedef unsigned char uint8;
6cba849e3332 frbl/reconst/inc: import from TCS211 surviving source
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
31 typedef unsigned short uint16;
6cba849e3332 frbl/reconst/inc: import from TCS211 surviving source
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
32 typedef unsigned long uint32;
6cba849e3332 frbl/reconst/inc: import from TCS211 surviving source
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
33 typedef signed char int8;
6cba849e3332 frbl/reconst/inc: import from TCS211 surviving source
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
34 typedef signed short int16;
6cba849e3332 frbl/reconst/inc: import from TCS211 surviving source
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
35 typedef signed long int32;
6cba849e3332 frbl/reconst/inc: import from TCS211 surviving source
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
36
6cba849e3332 frbl/reconst/inc: import from TCS211 surviving source
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
37 typedef union {
6cba849e3332 frbl/reconst/inc: import from TCS211 surviving source
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
38 UINT32 i; // integer value
6cba849e3332 frbl/reconst/inc: import from TCS211 surviving source
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
39 UBYTE b[4]; // byte array
6cba849e3332 frbl/reconst/inc: import from TCS211 surviving source
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
40 } union32_t;
6cba849e3332 frbl/reconst/inc: import from TCS211 surviving source
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
41
6cba849e3332 frbl/reconst/inc: import from TCS211 surviving source
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
42 typedef union {
6cba849e3332 frbl/reconst/inc: import from TCS211 surviving source
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
43 UINT16 i; // integer value
6cba849e3332 frbl/reconst/inc: import from TCS211 surviving source
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
44 UBYTE b[2]; // byte array
6cba849e3332 frbl/reconst/inc: import from TCS211 surviving source
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
45 } union16_t;
6cba849e3332 frbl/reconst/inc: import from TCS211 surviving source
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
46
6cba849e3332 frbl/reconst/inc: import from TCS211 surviving source
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
47 typedef struct {
6cba849e3332 frbl/reconst/inc: import from TCS211 surviving source
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
48 char (*init)(uint32 addr);
6cba849e3332 frbl/reconst/inc: import from TCS211 surviving source
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
49 char (*erase)(uint32 *addr, int size);
6cba849e3332 frbl/reconst/inc: import from TCS211 surviving source
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
50 char (*program)(uint32 addr, uint16 *buf, int size);
6cba849e3332 frbl/reconst/inc: import from TCS211 surviving source
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
51 uint8 (*getchar)(void);
6cba849e3332 frbl/reconst/inc: import from TCS211 surviving source
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
52 void (*putchar)(uint8 ch);
6cba849e3332 frbl/reconst/inc: import from TCS211 surviving source
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
53 void (*debug_putstr)(uint32 uart, char *string);
6cba849e3332 frbl/reconst/inc: import from TCS211 surviving source
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
54 void (*debug_putnum)(uint32 uart, unsigned int number);
6cba849e3332 frbl/reconst/inc: import from TCS211 surviving source
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
55 uint32 uart_base;
6cba849e3332 frbl/reconst/inc: import from TCS211 surviving source
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
56 } method_table_t;
6cba849e3332 frbl/reconst/inc: import from TCS211 surviving source
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
57
6cba849e3332 frbl/reconst/inc: import from TCS211 surviving source
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
58 // Prototypes for functions in debug.c
6cba849e3332 frbl/reconst/inc: import from TCS211 surviving source
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
59 void debug_putstr(uint32 uart, char *string);
6cba849e3332 frbl/reconst/inc: import from TCS211 surviving source
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
60 void debug_putnum(uint32 uart, unsigned int number);
6cba849e3332 frbl/reconst/inc: import from TCS211 surviving source
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
61
6cba849e3332 frbl/reconst/inc: import from TCS211 surviving source
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
62
6cba849e3332 frbl/reconst/inc: import from TCS211 surviving source
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
63 /******************************************************************************
6cba849e3332 frbl/reconst/inc: import from TCS211 surviving source
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
64 * Macros
6cba849e3332 frbl/reconst/inc: import from TCS211 surviving source
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
65 ******************************************************************************/
6cba849e3332 frbl/reconst/inc: import from TCS211 surviving source
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
66
6cba849e3332 frbl/reconst/inc: import from TCS211 surviving source
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
67 #define REGISTER_8_READ(addr) (*((volatile uint8 *) (addr)))
6cba849e3332 frbl/reconst/inc: import from TCS211 surviving source
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
68 #define REGISTER_8_WRITE(addr, data) (*((volatile uint8 *) (addr)) = data)
6cba849e3332 frbl/reconst/inc: import from TCS211 surviving source
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
69 #define REGISTER_16_READ(addr) (*((volatile uint16 *) (addr)))
6cba849e3332 frbl/reconst/inc: import from TCS211 surviving source
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
70 #define REGISTER_16_WRITE(addr, data) (*((volatile uint16 *) (addr)) = data)
6cba849e3332 frbl/reconst/inc: import from TCS211 surviving source
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
71
6cba849e3332 frbl/reconst/inc: import from TCS211 surviving source
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
72 #define BIT_SET(reg, bit) (*((volatile UINT16 *) (reg)) |= (1 << (bit)))
6cba849e3332 frbl/reconst/inc: import from TCS211 surviving source
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
73 #define BIT_CLR(reg, bit) (*((volatile UINT16 *) (reg)) &= ~(1 << (bit)))
6cba849e3332 frbl/reconst/inc: import from TCS211 surviving source
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
74
6cba849e3332 frbl/reconst/inc: import from TCS211 surviving source
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
75 #define FLASH_READ(addr) (*(volatile uint16 *) (addr))
6cba849e3332 frbl/reconst/inc: import from TCS211 surviving source
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
76 #define FLASH_WRITE(addr, data) (*(volatile uint16 *) (addr)) = data
6cba849e3332 frbl/reconst/inc: import from TCS211 surviving source
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
77
6cba849e3332 frbl/reconst/inc: import from TCS211 surviving source
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
78 #define PUTCHAR_FUNCTION_CODE(uart) \
6cba849e3332 frbl/reconst/inc: import from TCS211 surviving source
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
79 while (!(REGISTER_8_READ(uart + UART_LSR) & STAT_TXRDY)) ; \
6cba849e3332 frbl/reconst/inc: import from TCS211 surviving source
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
80 REGISTER_8_WRITE(uart + UART_THR, ch);
6cba849e3332 frbl/reconst/inc: import from TCS211 surviving source
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
81
6cba849e3332 frbl/reconst/inc: import from TCS211 surviving source
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
82 #define GETCHAR_FUNCTION_CODE(uart) \
6cba849e3332 frbl/reconst/inc: import from TCS211 surviving source
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
83 while (!(REGISTER_8_READ(uart + UART_LSR) & STAT_RXRDY)) ; \
6cba849e3332 frbl/reconst/inc: import from TCS211 surviving source
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
84 return (uint8) REGISTER_8_READ(uart + UART_RHR);
6cba849e3332 frbl/reconst/inc: import from TCS211 surviving source
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
85
6cba849e3332 frbl/reconst/inc: import from TCS211 surviving source
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
86
6cba849e3332 frbl/reconst/inc: import from TCS211 surviving source
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
87 /******************************************************************************
6cba849e3332 frbl/reconst/inc: import from TCS211 surviving source
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
88 * Debug Macros
6cba849e3332 frbl/reconst/inc: import from TCS211 surviving source
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
89 ******************************************************************************/
6cba849e3332 frbl/reconst/inc: import from TCS211 surviving source
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
90
6cba849e3332 frbl/reconst/inc: import from TCS211 surviving source
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
91 #define DEBUG_PUTSTR(uart, text) ((method_table_t *)(my_addr))->debug_putstr(uart, text);
6cba849e3332 frbl/reconst/inc: import from TCS211 surviving source
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
92 #define DEBUG_PUTNUM(uart, num) ((method_table_t *)(my_addr))->debug_putnum(uart, num);
6cba849e3332 frbl/reconst/inc: import from TCS211 surviving source
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
93
6cba849e3332 frbl/reconst/inc: import from TCS211 surviving source
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
94
6cba849e3332 frbl/reconst/inc: import from TCS211 surviving source
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
95 /******************************************************************************
6cba849e3332 frbl/reconst/inc: import from TCS211 surviving source
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
96 * Hardware Definitions
6cba849e3332 frbl/reconst/inc: import from TCS211 surviving source
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
97 ******************************************************************************/
6cba849e3332 frbl/reconst/inc: import from TCS211 surviving source
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
98
6cba849e3332 frbl/reconst/inc: import from TCS211 surviving source
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
99 #define UART_BASE_MODEM (0xFFFF5800)
6cba849e3332 frbl/reconst/inc: import from TCS211 surviving source
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
100 #define UART_BASE_IRDA (0xFFFF5000)
6cba849e3332 frbl/reconst/inc: import from TCS211 surviving source
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
101
6cba849e3332 frbl/reconst/inc: import from TCS211 surviving source
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
102 // ROM/Flash Config register
6cba849e3332 frbl/reconst/inc: import from TCS211 surviving source
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
103 #define WS_REG_ROM 0x400000
6cba849e3332 frbl/reconst/inc: import from TCS211 surviving source
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
104
6cba849e3332 frbl/reconst/inc: import from TCS211 surviving source
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
105 // UART register definitions.
6cba849e3332 frbl/reconst/inc: import from TCS211 surviving source
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
106 #define UART_RHR (0x00) /* Receive Holding Register */
6cba849e3332 frbl/reconst/inc: import from TCS211 surviving source
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
107 #define UART_THR (0x00) /* Transmit Holding Register */
6cba849e3332 frbl/reconst/inc: import from TCS211 surviving source
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
108 #define UART_FCR (0x02) /* FIFO Control Register */
6cba849e3332 frbl/reconst/inc: import from TCS211 surviving source
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
109 #define UART_LCR (0x03) /* Line Control Register */
6cba849e3332 frbl/reconst/inc: import from TCS211 surviving source
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
110 #define UART_LSR (0x05) /* Line Status Register */
6cba849e3332 frbl/reconst/inc: import from TCS211 surviving source
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
111 #define UART_MDR1 (0x08) /* Mode Definition Register 1 */
6cba849e3332 frbl/reconst/inc: import from TCS211 surviving source
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
112 #define UART_EFR (0x02) /* Enhanced Feature Register */
6cba849e3332 frbl/reconst/inc: import from TCS211 surviving source
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
113 #define UART_DLL (0x00) /* Divisor Latches */
6cba849e3332 frbl/reconst/inc: import from TCS211 surviving source
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
114 #define UART_DLH (0x01) /* Divisor Latches */
6cba849e3332 frbl/reconst/inc: import from TCS211 surviving source
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
115 #define UART_UIR (0xFFFF6000) /* UART Interface Register */
6cba849e3332 frbl/reconst/inc: import from TCS211 surviving source
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
116
6cba849e3332 frbl/reconst/inc: import from TCS211 surviving source
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
117 // UART status bit definitions.
6cba849e3332 frbl/reconst/inc: import from TCS211 surviving source
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
118 #define STAT_RXRDY (0x01)
6cba849e3332 frbl/reconst/inc: import from TCS211 surviving source
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
119 #define STAT_TXRDY (0x20)
6cba849e3332 frbl/reconst/inc: import from TCS211 surviving source
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
120 #define STAT_TX_E (0x40)
6cba849e3332 frbl/reconst/inc: import from TCS211 surviving source
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
121
6cba849e3332 frbl/reconst/inc: import from TCS211 surviving source
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
122 // UART_UIR bit definitions.
6cba849e3332 frbl/reconst/inc: import from TCS211 surviving source
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
123 #define UART_ACCESS (0)
6cba849e3332 frbl/reconst/inc: import from TCS211 surviving source
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
124 #define UART_MASK_IT (1)
6cba849e3332 frbl/reconst/inc: import from TCS211 surviving source
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
125
6cba849e3332 frbl/reconst/inc: import from TCS211 surviving source
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
126 // UART_EFR bit definitions.
6cba849e3332 frbl/reconst/inc: import from TCS211 surviving source
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
127 #define ENHANCED_EN (4)
6cba849e3332 frbl/reconst/inc: import from TCS211 surviving source
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
128
6cba849e3332 frbl/reconst/inc: import from TCS211 surviving source
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
129 // UART command bit definitions.
6cba849e3332 frbl/reconst/inc: import from TCS211 surviving source
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
130 #define CMD_UART_RESET (0x07)
6cba849e3332 frbl/reconst/inc: import from TCS211 surviving source
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
131 #define CMD_EFR_EN (0xBF)
6cba849e3332 frbl/reconst/inc: import from TCS211 surviving source
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
132 #define CMD_FCR_MCR_EN (0x80)
6cba849e3332 frbl/reconst/inc: import from TCS211 surviving source
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
133 #define CMD_FIFO_EN (0x07)
6cba849e3332 frbl/reconst/inc: import from TCS211 surviving source
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
134 #define CMD_UART_MODE (0x00)
6cba849e3332 frbl/reconst/inc: import from TCS211 surviving source
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
135 #define CMD_CHAR8_STOP1_NOPAR (0x03)
6cba849e3332 frbl/reconst/inc: import from TCS211 surviving source
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
136
6cba849e3332 frbl/reconst/inc: import from TCS211 surviving source
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
137 // UART ???
6cba849e3332 frbl/reconst/inc: import from TCS211 surviving source
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
138 #define BAUD_38400 (0x15)
6cba849e3332 frbl/reconst/inc: import from TCS211 surviving source
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
139 #define BAUD_115200 (0x07)
6cba849e3332 frbl/reconst/inc: import from TCS211 surviving source
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
140 #define BAUD_406250 (0x02)
6cba849e3332 frbl/reconst/inc: import from TCS211 surviving source
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
141 #define BAUD_812500 (0x01)
6cba849e3332 frbl/reconst/inc: import from TCS211 surviving source
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
142
6cba849e3332 frbl/reconst/inc: import from TCS211 surviving source
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
143
6cba849e3332 frbl/reconst/inc: import from TCS211 surviving source
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
144 // Enable/Disable ROM/Flash write strobe
6cba849e3332 frbl/reconst/inc: import from TCS211 surviving source
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
145 #define ROM_WRITE_ENABLE() *((volatile uint16*) WS_REG_ROM) |= 0x80;
6cba849e3332 frbl/reconst/inc: import from TCS211 surviving source
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
146 #define ROM_WRITE_DISABLE() *((volatile uint16*) WS_REG_ROM) &= ~0x80;
6cba849e3332 frbl/reconst/inc: import from TCS211 surviving source
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
147
6cba849e3332 frbl/reconst/inc: import from TCS211 surviving source
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
148 #endif /* __TARGET_H__ */