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annotate arm7dis/atcommon.c @ 308:f8344bc4fd61

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dspanal: char2coff utility written, compiles
author Mychaela Falconia <falcon@freecalypso.org>
date Mon, 28 Oct 2019 05:20:50 +0000
parents c883e60df239
children
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c883e60df239 arm7dis: README and header comments added
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 97
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1 /*
c883e60df239 arm7dis: README and header comments added
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 97
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2 * Lean and mean ARM7TDMI disassembler
c883e60df239 arm7dis: README and header comments added
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 97
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3 * Written by Spacefalcon the Outlaw
c883e60df239 arm7dis: README and header comments added
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 97
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4 */
c883e60df239 arm7dis: README and header comments added
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 97
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5
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f7fba8518fa2 armdis: skeleton compiles
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
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6 /* a few disassembly bits common between ARM and Thumb */
f7fba8518fa2 armdis: skeleton compiles
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
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7
f7fba8518fa2 armdis: skeleton compiles
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
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8 char *regnames[16] = {"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
f7fba8518fa2 armdis: skeleton compiles
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
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9 "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc"};
f7fba8518fa2 armdis: skeleton compiles
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
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10
f7fba8518fa2 armdis: skeleton compiles
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
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11 char *condition_decode[16] = {"eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc",
f7fba8518fa2 armdis: skeleton compiles
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
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12 "hi", "ls", "ge", "lt", "gt", "le", "", "INV"};
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fb5ea2758482 thumbdis written, compiles
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 87
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13
fb5ea2758482 thumbdis written, compiles
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents: 87
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14 char *shift_types[4] = {"lsl", "lsr", "asr", "ror"};