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comparison frbl/reconst/boot.c @ 316:2ceb1f263e19

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frbl/reconst: first attempt to compile boot.c
author Mychaela Falconia <falcon@freecalypso.org>
date Wed, 04 Mar 2020 23:41:51 +0000
parents bc3391aa3d35
children c71e3156170a
comparison
equal deleted inserted replaced
315:bc3391aa3d35 316:2ceb1f263e19
43 // this, no matter if we were laoded with JTAG or if we were compiled-in. 43 // this, no matter if we were laoded with JTAG or if we were compiled-in.
44 44
45 #if (CHIPSET == 3) 45 #if (CHIPSET == 3)
46 asm("STACK_INIT .equ 03000000h"); 46 asm("STACK_INIT .equ 03000000h");
47 asm("STACK_ADD .equ 00020000h ; 128kB"); 47 asm("STACK_ADD .equ 00020000h ; 128kB");
48 #elif (CHIPSET == 7) 48 #elif (CHIPSET == 7 || CHIPSET == 8 || CHIPSET == 10 || CHIPSET == 11)
49 asm("STACK_INIT .equ 00800000h"); 49 asm("STACK_INIT .equ 00800000h");
50 asm("STACK_ADD .equ 00020000h ; 128kB"); 50 asm("STACK_ADD .equ 00020000h ; 128kB");
51 #elif (CHIPSET == 12) 51 #elif (CHIPSET == 12)
52 asm("STACK_INIT .equ 08000000h"); 52 asm("STACK_INIT .equ 08000000h");
53 asm("STACK_ADD .equ 00020000h ; 128kB"); 53 asm("STACK_ADD .equ 00020000h ; 128kB");
201 /****************************************************************************** 201 /******************************************************************************
202 * Initialization 202 * Initialization
203 ******************************************************************************/ 203 ******************************************************************************/
204 #if (CHIPSET == 3) 204 #if (CHIPSET == 3)
205 #define IQ_MASK (0xFFFFFA02) /* Mask Interrupt Register */ 205 #define IQ_MASK (0xFFFFFA02) /* Mask Interrupt Register */
206 #elif (CHIPSET == 7) || (CHIPSET == 12) 206 #elif (CHIPSET == 7 || CHIPSET == 8 || CHIPSET == 10 || CHIPSET == 11) \
207 || (CHIPSET == 12)
207 #define IQ_MASK1 (0xFFFFFA08) /* Mask Interrupt Register 1 */ 208 #define IQ_MASK1 (0xFFFFFA08) /* Mask Interrupt Register 1 */
208 #define IQ_MASK2 (0xFFFFFA0A) /* Mask Interrupt Register 2 */ 209 #define IQ_MASK2 (0xFFFFFA0A) /* Mask Interrupt Register 2 */
209 #else 210 #else
210 #error Unknown target hardware selected 211 #error Unknown target hardware selected
211 #endif 212 #endif
230 // detected? 231 // detected?
231 232
232 // Mask all interrupts 233 // Mask all interrupts
233 #if (CHIPSET == 3) 234 #if (CHIPSET == 3)
234 *((volatile uint16 *) IQ_MASK) = 0xFFFF; 235 *((volatile uint16 *) IQ_MASK) = 0xFFFF;
235 #elif (CHIPSET == 7) 236 #elif (CHIPSET == 7 || CHIPSET == 8 || CHIPSET == 10 || CHIPSET == 11)
236 *((volatile uint16 *) IQ_MASK1) = 0xFFFF; 237 *((volatile uint16 *) IQ_MASK1) = 0xFFFF;
237 *((volatile uint16 *) IQ_MASK2) = 0x001F; 238 *((volatile uint16 *) IQ_MASK2) = 0x001F;
238 #elif (CHIPSET == 12) 239 #elif (CHIPSET == 12)
239 *((volatile uint16 *) IQ_MASK1) = 0xFFFF; 240 *((volatile uint16 *) IQ_MASK1) = 0xFFFF;
240 *((volatile uint16 *) IQ_MASK2) = 0xFFFF; //BJO Check IRQ_29_MSK - should it be 0 ? 241 *((volatile uint16 *) IQ_MASK2) = 0xFFFF; //BJO Check IRQ_29_MSK - should it be 0 ?
247 *((volatile uint16 *) WATCHDOG_TIM_MODE+80) = 0xF5; // Secure watchdog CALPLUS 248 *((volatile uint16 *) WATCHDOG_TIM_MODE+80) = 0xF5; // Secure watchdog CALPLUS
248 *((volatile uint16 *) WATCHDOG_TIM_MODE+80) = 0xA0; // Secure watchdog CALPLUS 249 *((volatile uint16 *) WATCHDOG_TIM_MODE+80) = 0xA0; // Secure watchdog CALPLUS
249 #endif 250 #endif
250 251
251 252
252 #if (CHIPSET == 3) || (CHIPSET == 7) 253 #if (CHIPSET == 3) || (CHIPSET == 7 || CHIPSET == 8 || CHIPSET == 10 || CHIPSET == 11)
253 // FIXME: Describe exactly how the CSs are initialized 254 // FIXME: Describe exactly how the CSs are initialized
254 *((volatile uint16 *) CS0_MEM_REG) = 0x2A1; 255 *((volatile uint16 *) CS0_MEM_REG) = 0x2A1;
255 *((volatile uint16 *) CS1_MEM_REG) = 0x2A1; 256 *((volatile uint16 *) CS1_MEM_REG) = 0x2A1;
256 *((volatile uint16 *) CS2_MEM_REG) = 0x2A1; 257 *((volatile uint16 *) CS2_MEM_REG) = 0x2A1;
257 *((volatile uint16 *) CS3_MEM_REG) = 0x283; 258 *((volatile uint16 *) CS3_MEM_REG) = 0x283;
271 clk = *(volatile uint16 *) CLKM_CNTL_ARM_CLK; 272 clk = *(volatile uint16 *) CLKM_CNTL_ARM_CLK;
272 clk &= ~(0x0C | 0x30); 273 clk &= ~(0x0C | 0x30);
273 clk |= (2 << 4); 274 clk |= (2 << 4);
274 *(volatile uint16 *) CLKM_CNTL_ARM_CLK = clk; 275 *(volatile uint16 *) CLKM_CNTL_ARM_CLK = clk;
275 276
276 #elif (CHIPSET == 7) 277 #elif (CHIPSET == 7 || CHIPSET == 8 || CHIPSET == 10 || CHIPSET == 11)
277 278
278 // Reset DPLL register 279 // Reset DPLL register
279 * (volatile uint16 *) MEM_DPLL_ADDR = DPLL_RESET_VALUE; 280 * (volatile uint16 *) MEM_DPLL_ADDR = DPLL_RESET_VALUE;
280 281
281 // Wait that DPLL is in BYPASS mode 282 // Wait that DPLL is in BYPASS mode