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comparison pirelli/fw-disasm @ 242:5eca9fccd706

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pirelli/fw-disasm: pwr_env code located
author Mychaela Falconia <falcon@freecalypso.org>
date Sat, 23 Dec 2017 03:56:02 +0000
parents cead37b6ff74
children 83715e0c65de
comparison
equal deleted inserted replaced
241:cead37b6ff74 242:5eca9fccd706
964 $spi_kill: 964 $spi_kill:
965 3cd88a: 2000 mov r0, #0 965 3cd88a: 2000 mov r0, #0
966 3cd88c: 4770 bx lr 966 3cd88c: 4770 bx lr
967 3cd88e: 46c0 nop (mov r8, r8) 967 3cd88e: 46c0 nop (mov r8, r8)
968 968
969 $pwr_get_info:
970 ; perfect match to TI's original
971 3cd954: b530 push {r4, r5, lr}
972 3cd956: 1c04 add r4, r0, #0
973 3cd958: 2000 mov r0, #0
974 3cd95a: 6020 str r0, [r4, #0]
975 3cd95c: 487a ldr r0, =0xa0020 ; via 0x3cdb48
976 3cd95e: 6120 str r0, [r4, #16] ; 0x10
977 3cd960: 2004 mov r0, #4
978 3cd962: 1900 add r0, r0, r4
979 3cd964: a14f add r1, pc, #316 ; 0x13c
980 3cd966: 2204 mov r2, #4
981 3cd968: f029 fc68 bl 0x3f723c ; memcpy()
982 3cd96c: 2188 mov r1, #136 ; 0x88
983 3cd96e: 2000 mov r0, #0
984 3cd970: 5108 str r0, [r1, r4]
985 3cd972: 2084 mov r0, #132 ; 0x84
986 3cd974: 2100 mov r1, #0
987 3cd976: 5501 strb r1, [r0, r4]
988 3cd978: 2501 mov r5, #1
989 3cd97a: 7625 strb r5, [r4, #24] ; 0x18
990 3cd97c: 201c mov r0, #28 ; 0x1c
991 3cd97e: 1900 add r0, r0, r4
992 3cd980: a149 add r1, pc, #292 ; 0x124
993 3cd982: 2209 mov r2, #9
994 3cd984: f029 fc5a bl 0x3f723c ; memcpy()
995 3cd988: 207d mov r0, #125 ; 0x7d
996 3cd98a: 00c0 lsl r0, r0, #3
997 3cd98c: 62a0 str r0, [r4, #40] ; 0x28
998 3cd98e: 2019 mov r0, #25 ; 0x19
999 3cd990: 0140 lsl r0, r0, #5
1000 3cd992: 62e0 str r0, [r4, #44] ; 0x2c
1001 3cd994: 2058 mov r0, #88 ; 0x58
1002 3cd996: 5505 strb r5, [r0, r4]
1003 3cd998: 486c ldr r0, =0xa0010 ; via 0x3cdb4c
1004 3cd99a: 65e0 str r0, [r4, #92] ; 0x5c
1005 3cd99c: 208c mov r0, #140 ; 0x8c
1006 3cd99e: 496c ldr r1, =0x3cd9bf ; via 0x3cdb50
1007 3cd9a0: 5101 str r1, [r0, r4]
1008 3cd9a2: 2090 mov r0, #144 ; 0x90
1009 3cd9a4: 496b ldr r1, =0x3cda8b ; via 0x3cdb54
1010 3cd9a6: 5101 str r1, [r0, r4]
1011 3cd9a8: 2094 mov r0, #148 ; 0x94
1012 3cd9aa: 496b ldr r1, =0x3cda8f ; via 0x3cdb58
1013 3cd9ac: 5101 str r1, [r0, r4]
1014 3cd9ae: 2098 mov r0, #152 ; 0x98
1015 3cd9b0: 496a ldr r1, =0x3cda93 ; via 0x3cdb5c
1016 3cd9b2: 5101 str r1, [r0, r4]
1017 3cd9b4: 219c mov r1, #156 ; 0x9c
1018 3cd9b6: 486a ldr r0, =0x3cda97 ; via 0x3cdb60
1019 3cd9b8: 5108 str r0, [r1, r4]
1020 3cd9ba: 2000 mov r0, #0
1021 3cd9bc: bd30 pop {r4, r5, pc}
1022
1023 $pwr_set_info:
1024 3cd9be: b570 push {r4, r5, r6, lr}
1025 3cd9c0: b082 sub sp, #8
1026 3cd9c2: 1c1d add r5, r3, #0
1027 3cd9c4: 1c14 add r4, r2, #0
1028 3cd9c6: 4860 ldr r0, =0xa0020 ; via 0x3cdb48
1029 3cd9c8: 9000 str r0, [sp, #0]
1030 3cd9ca: a03a add r0, pc, #232 ; 0xe8
1031 3cd9cc: 213c mov r1, #60 ; 0x3c
1032 3cd9ce: 2200 mov r2, #0
1033 3cd9d0: 43d2 mvn r2, r2
1034 3cd9d2: 2303 mov r3, #3
1035 3cd9d4: f00d f92e bl 0x3dac34
1036 3cd9d8: 8820 ldrh r0, [r4, #0]
1037 ; struct allocation size differs from original
1038 3cd9da: 214c mov r1, #76 ; 0x4c
1039 3cd9dc: 4a61 ldr r2, =0x1774e70 ; via 0x3cdb64
1040 3cd9de: f5f6 fff3 bl 0x1c49c8
1041 3cd9e2: 2802 cmp r0, #2
1042 3cd9e4: d10b bne 0x3cd9fe
1043 3cd9e6: 4858 ldr r0, =0xa0020 ; via 0x3cdb48
1044 3cd9e8: 9000 str r0, [sp, #0]
1045 3cd9ea: a042 add r0, pc, #264 ; 0x108
1046 3cd9ec: 2156 mov r1, #86 ; 0x56
1047 3cd9ee: 2200 mov r2, #0
1048 3cd9f0: 43d2 mvn r2, r2
1049 3cd9f2: 2301 mov r3, #1
1050 3cd9f4: f00d f91e bl 0x3dac34
1051 3cd9f8: 2004 mov r0, #4
1052 3cd9fa: 43c0 mvn r0, r0
1053 3cd9fc: e043 b 0x3cda86
1054 3cd9fe: 485a ldr r0, =0x1774e74 ; via 0x3cdb68
1055 3cda00: 6005 str r5, [r0, #0]
1056 3cda02: 4b58 ldr r3, =0x1774e70 ; via 0x3cdb64
1057 3cda04: 6819 ldr r1, [r3, #0]
1058 3cda06: 4859 ldr r0, =0x1774e38 ; via 0x3cdb6c
1059 3cda08: 6800 ldr r0, [r0, #0]
1060 3cda0a: 7880 ldrb r0, [r0, #2]
1061 3cda0c: 7088 strb r0, [r1, #2]
1062 3cda0e: 6818 ldr r0, [r3, #0]
1063 3cda10: 8821 ldrh r1, [r4, #0]
1064 3cda12: 8001 strh r1, [r0, #0]
1065 3cda14: 2200 mov r2, #0
1066 3cda16: 6818 ldr r0, [r3, #0]
1067 3cda18: 6042 str r2, [r0, #4]
1068 3cda1a: 6819 ldr r1, [r3, #0]
1069 ; end of charge current
1070 3cda1c: 207a mov r0, #122 ; 0x7a
1071 3cda1e: 8148 strh r0, [r1, #10] ; 0xa
1072 ; pwr_env_ctrl_blk->max_voltage_code is set to:
1073 ; (0x426800 - adccal_b*1024) / adccal_a
1074 ; 0x426800 >> 10 = 0x109A = 4250
1075 3cda20: 4c53 ldr r4, =0x426800 ; via 0x3cdb70
1076 3cda22: 4954 ldr r1, =0x801746 ; via 0x3cdb74
1077 3cda24: 2000 mov r0, #0
1078 3cda26: 5e08 ldrsh r0, [r1, r0]
1079 3cda28: 0280 lsl r0, r0, #10
1080 3cda2a: 1a20 sub r0, r4, r0
1081 3cda2c: 4952 ldr r1, =0x801734 ; via 0x3cdb78
1082 3cda2e: 8809 ldrh r1, [r1, #0]
1083 3cda30: f029 fbe4 bl 0x3f71fc ; U$DIV
1084 ; MV100-matching logic continues
1085 3cda34: 6818 ldr r0, [r3, #0]
1086 3cda36: 8181 strh r1, [r0, #12] ; 0xc
1087 3cda38: 0610 lsl r0, r2, #24
1088 3cda3a: 0e01 lsr r1, r0, #24
1089 3cda3c: 6818 ldr r0, [r3, #0]
1090 3cda3e: 7401 strb r1, [r0, #16] ; 0x10
1091 3cda40: 24ff mov r4, #255 ; 0xff
1092 3cda42: 6818 ldr r0, [r3, #0]
1093 3cda44: 7504 strb r4, [r0, #20] ; 0x14
1094 3cda46: 2000 mov r0, #0
1095 3cda48: 681d ldr r5, [r3, #0]
1096 3cda4a: 61a8 str r0, [r5, #24] ; 0x18
1097 3cda4c: 681e ldr r6, [r3, #0]
1098 3cda4e: 2505 mov r5, #5
1099 3cda50: 7735 strb r5, [r6, #28] ; 0x1c
1100 3cda52: 2620 mov r6, #32 ; 0x20
1101 3cda54: 681d ldr r5, [r3, #0]
1102 3cda56: 5574 strb r4, [r6, r5]
1103 3cda58: 681d ldr r5, [r3, #0]
1104 3cda5a: 6268 str r0, [r5, #36] ; 0x24
1105 3cda5c: 2628 mov r6, #40 ; 0x28
1106 3cda5e: 681d ldr r5, [r3, #0]
1107 3cda60: 5574 strb r4, [r6, r5]
1108 3cda62: 681c ldr r4, [r3, #0]
1109 3cda64: 62e0 str r0, [r4, #44] ; 0x2c
1110 3cda66: 6818 ldr r0, [r3, #0]
1111 3cda68: 8702 strh r2, [r0, #56] ; 0x38
1112 3cda6a: 2001 mov r0, #1
1113 3cda6c: 681c ldr r4, [r3, #0]
1114 3cda6e: 6320 str r0, [r4, #48] ; 0x30
1115 ; new since original: pwr_env_ctrl_blk->i2v_madc_offset = 0
1116 3cda70: 681c ldr r4, [r3, #0]
1117 3cda72: 8122 strh r2, [r4, #8]
1118 ; new stuff:
1119 ; halfword at 0x40 = 1
1120 ; word at 0x44 = 0
1121 ; byte at 0x48 = 0
1122 3cda74: 2540 mov r5, #64 ; 0x40
1123 3cda76: 681c ldr r4, [r3, #0]
1124 3cda78: 5328 strh r0, [r5, r4]
1125 3cda7a: 6818 ldr r0, [r3, #0]
1126 3cda7c: 6442 str r2, [r0, #68] ; 0x44
1127 3cda7e: 2248 mov r2, #72 ; 0x48
1128 3cda80: 6818 ldr r0, [r3, #0]
1129 3cda82: 5411 strb r1, [r2, r0]
1130 3cda84: 2000 mov r0, #0
1131 3cda86: b002 add sp, #8
1132 3cda88: bd70 pop {r4, r5, r6, pc}
1133
1134 $pwr_init:
1135 3cda8a: 2000 mov r0, #0
1136 3cda8c: 4770 bx lr
1137
1138 $pwr_start:
1139 3cda8e: 2000 mov r0, #0
1140 3cda90: 4770 bx lr
1141
1142 $pwr_stop:
1143 3cda92: 2000 mov r0, #0
1144 3cda94: 4770 bx lr
1145
1146 $pwr_kill:
1147 3cda96: b500 push {lr}
1148 3cda98: 4832 ldr r0, =0x1774e70 ; via 0x3cdb64
1149 3cda9a: 6800 ldr r0, [r0, #0]
1150 3cda9c: f5f7 f92c bl 0x1c4cf8
1151 3cdaa0: 2000 mov r0, #0
1152 3cdaa2: bd00 pop {pc}
1153
969 _f_checksum: 1154 _f_checksum:
970 3e6990: e1a0c000 mov r12, r0 1155 3e6990: e1a0c000 mov r12, r0
971 3e6994: e3a00000 mov r0, #0 1156 3e6994: e3a00000 mov r0, #0
972 3e6998: e3510000 cmp r1, #0 1157 3e6998: e3510000 cmp r1, #0
973 3e699c: 012fff1e bxeq lr 1158 3e699c: 012fff1e bxeq lr
1456 1641
1457 XRAM data: 1642 XRAM data:
1458 1643
1459 0x1774e38: SPI_GBL_INFO_PTR 1644 0x1774e38: SPI_GBL_INFO_PTR
1460 0x1774e3c: spi_error_ft 1645 0x1774e3c: spi_error_ft
1646
1647 0x1774e70: pwr_env_ctrl_blk
1648 0x1774e74: pwr_error_ft