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comparison pirelli/fw-disasm @ 245:9cd7fa86da47

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pirelli/fw-disasm: l1_initialize() located
author Mychaela Falconia <falcon@freecalypso.org>
date Sat, 23 Dec 2017 23:26:06 +0000
parents f40f069b0d06
children b2002dcbad3d
comparison
equal deleted inserted replaced
244:f40f069b0d06 245:9cd7fa86da47
478 406c4: e4d13001 ldrb r3, [r1], #1 478 406c4: e4d13001 ldrb r3, [r1], #1
479 406c8: e4c03001 strb r3, [r0], #1 479 406c8: e4c03001 strb r3, [r0], #1
480 406cc: e2522001 subs r2, r2, #1 480 406cc: e2522001 subs r2, r2, #1
481 406d0: 1afffffb bne 0x406c4 481 406d0: 1afffffb bne 0x406c4
482 406d4: e8bd8001 ldmia sp!, {r0, pc} 482 406d4: e8bd8001 ldmia sp!, {r0, pc}
483
484 $l1_initialize:
485 31c6e4: b530 push {r4, r5, lr}
486 31c6e6: 1c04 add r4, r0, #0
487 31c6e8: 483f ldr r0, =0x803f48 ; via 0x31c7e8
488 31c6ea: 7800 ldrb r0, [r0, #0]
489 31c6ec: 2800 cmp r0, #0
490 31c6ee: d101 bne 0x31c6f4
491 31c6f0: f59f fdd1 bl 0xbc296
492 31c6f4: 4968 ldr r1, =0x8029a4 ; via 0x31c898
493 31c6f6: 4865 ldr r0, =0x15a4 ; via 0x31c88c
494 31c6f8: 2500 mov r5, #0
495 31c6fa: 5445 strb r5, [r0, r1]
496 31c6fc: f0c6 fbf6 bl 0x3e2eec
497 31c700: 481c ldr r0, =0x802868 ; via 0x31c774
498 31c702: 7821 ldrb r1, [r4, #0]
499 31c704: 7001 strb r1, [r0, #0]
500 31c706: 213d mov r1, #61 ; 0x3d
501 31c708: 7922 ldrb r2, [r4, #4]
502 31c70a: 540a strb r2, [r1, r0]
503 31c70c: 88e1 ldrh r1, [r4, #6]
504 31c70e: 87c1 strh r1, [r0, #62] ; 0x3e
505 31c710: 21c0 mov r1, #192 ; 0xc0
506 31c712: 540d strb r5, [r1, r0]
507 31c714: 22c1 mov r2, #193 ; 0xc1
508 31c716: 2101 mov r1, #1
509 31c718: 5411 strb r1, [r2, r0]
510 31c71a: 22c2 mov r2, #194 ; 0xc2
511 31c71c: 5411 strb r1, [r2, r0]
512 31c71e: 22c3 mov r2, #195 ; 0xc3
513 31c720: 5411 strb r1, [r2, r0]
514 31c722: 495e ldr r1, =0x802228 ; via 0x31c89c
515 31c724: 7a22 ldrb r2, [r4, #8]
516 31c726: 700a strb r2, [r1, #0]
517 31c728: 68e2 ldr r2, [r4, #12] ; 0xc
518 31c72a: 604a str r2, [r1, #4]
519 31c72c: 213c mov r1, #60 ; 0x3c
520 31c72e: 78e2 ldrb r2, [r4, #3]
521 31c730: 540a strb r2, [r1, r0]
522 31c732: f0dd fce3 bl 0x3fa0fc ; $Cust_init_std
523 31c736: f0dd fce9 bl 0x3fa10c ; $Cust_init_params
524 31c73a: f7ff ffb2 bl 0x31c6a2 ; $l1_dpll_init_var
525 31c73e: f0dc fd8d bl 0x3f925c ; $dsp_power_on
526 31c742: f7ff fc78 bl 0x31c036 ; $l1_abb_power_on
527 31c746: f7ff fc68 bl 0x31c01a ; $l1_tpu_init
528 31c74a: f7ff fb47 bl 0x31bddc ; $l1_dsp_init
529 31c74e: f7ff fdf9 bl 0x31c344 ; $l1_initialize_var
530 31c752: f0dc fccb bl 0x3f90ec ; $initialize_l1pvar
531 31c756: bd30 pop {r4, r5, pc}
483 532
484 $ABB_Sem_Create: 533 $ABB_Sem_Create:
485 3491ee: b500 push {lr} 534 3491ee: b500 push {lr}
486 3491f0: 48f2 ldr r0, =0x17741e0 ; via 0x3495bc 535 3491f0: 48f2 ldr r0, =0x17741e0 ; via 0x3495bc
487 3491f2: a1f0 add r1, pc, #960 ; 0x3c0 536 3491f2: a1f0 add r1, pc, #960 ; 0x3c0
2061 83cb90: bd30 pop {r4, r5, pc} 2110 83cb90: bd30 pop {r4, r5, pc}
2062 83cb92: 2000 mov r0, #0 2111 83cb92: 2000 mov r0, #0
2063 83cb94: 4770 bx lr 2112 83cb94: 4770 bx lr
2064 83cb96: 46c0 nop (mov r8, r8) 2113 83cb96: 46c0 nop (mov r8, r8)
2065 2114
2115 $l1_initialize call trampoline
2116 848a7c: b082 sub sp, #8
2117 848a7e: 9400 str r4, [sp, #0]
2118 848a80: 4c01 ldr r4, =0x31c6e4 ; via 0x848a88
2119 848a82: 9401 str r4, [sp, #4]
2120 848a84: bd10 pop {r4, pc}
2121 848a86: 0000
2122 848a88: 0031c6e4
2123
2066 XRAM data: 2124 XRAM data:
2067 2125
2068 0x17741e0: abb_sem 2126 0x17741e0: abb_sem
2069 2127
2070 0x1774e38: SPI_GBL_INFO_PTR 2128 0x1774e38: SPI_GBL_INFO_PTR