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comparison pirelli/calypso @ 10:b0f7481efc8b

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Pirelli PCB rev eng: finally have something worthy to report: traced out the 3 chip selects for the RAM/flash MCP.
author Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
date Sat, 20 Apr 2013 00:56:45 +0000
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children 8e4dac492552
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9:7a84f9e42a84 10:b0f7481efc8b
1 Calypso pin I thought was nIBOOT (N1), but actually seems to be A13 (RFEN):
2 the trace from the ball goes straight down to a via, L1 image coords
3 (3676,1174). On L2 trace goes to another via at (3234,1074). On L5 it goes
4 to yet another via at (2950,535). On L4 it goes to (1941,457). On L2 it goes
5 to a surface via at (1957,484). Back on L1 it goes to Rita pin 2 (XEN).
6 This arrangement matches what the Rita spec describes as the "external VCTCXO"
7 configuration. In contrast, the Leonardo schematics depict the "internal
8 VCTCXO" configuration.
9
10 Double-checking: in the "external VCTCXO" configuration Rita pin 1 (XSEL) is
11 supposed to be grounded. On L1 the pad appears to go nowhere (isolated).
12 The central coordinates of the pad on L1 are (1956,638). On L2 there is
13 solid copper fill in that area. Perhaps there is an invisible micro-via?
14
15 The real nIBOOT pin (N1): stays on L1, a trace takes it to one pad of a
16 2-pad SMT component, the other pad's connection is unclear (appears isolated,
17 must be an invisible micro-via). Must be a pull-up/down resistor, hopefully
18 pull-down.
19
20 nCS0 (C2): L1 trace to (4262,1016). On L2 it goes to two via points:
21 (4852,1016), an obvious larger via, and (4802,1000), a spot where a micro-via
22 back to L1 could hide. The micro-via back to L1 appears to be there indeed,
23 feeding an unmasked test point on the surface. Back to the main trace at
24 (4852,1016): there's something on L4 (might be a trace to another nearby via),
25 but maybe it's nothing, just a poor picture. Most likely nothing there, as
26 the same arrangement appears on L5 and L6, but clearly with no connection
27 between the two nearby vias. L7 is probably where the interesting connection
28 is, but the trace appears to have been scraped off in that spot in steve-m's
29 layer-grinding process.
30
31 Taking a different approach: let's start with the RAM/flash MCP on L8. Flash
32 CE1# goes to (4911,987); flash CE2# goes to (4954,660) and to an L8 test pad;
33 OE# goes to (4885,982); RAM CE1# goes to (4860,978). Of the two L2-L7 vias,
34 the upper one appears to be RAM, and the lower one appears to be flash.
35
36 Mistake found: I had earlier messed up trying to trace nCS0 on L2. Now it's
37 all clear: nCS0 goes to flash CE1#.
38
39 Now let's trace the RAM CS. From the upper L2-L7 via it goes on L2 to
40 (4800,1002) - already known to be a test point - and to (4212,978).
41 On L1 it goes to Calypso pin C3 - nCS1, just like on Leonardo.
42
43 Now let's trace flash CE2#. L7-L8 via at (4954,660); L2-L7 via at (4965,927);
44 on L2 it goes to (4210,930), on L1 it goes to Calypso ball D3.
45 That's nCS3.