view gtm900/interface-signals @ 375:6057c98d11a9

pirelli/audio-modes capture
author Mychaela Falconia <falcon@freecalypso.org>
date Sat, 31 Jul 2021 10:18:34 +0000
parents c06cac606af3
children
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UART interfaces
===============

Both Calypso UARTs are brought out on the GTM900 module interface as follows:

Pin	Name in manual	Connected Calypso ball
11	RXD2		TX_IRDA
12	TXD2		RX_IRDA
-------------------------------
16	UART_DSR	GPIO1
17	UART_RI		GPIO0
18	UART_RXD	TX_MODEM
19	UART_TXD	RX_MODEM
20	UART_CTS	RTS_MODEM
21	UART_RTS	CTS_MODEM
22	UART_DTR	GPIO3
23	UART_DCD	GPIO2

The interface signal names in Huawei's manual are given from the host's
perspective (classic DTE-to-DCE paradigm), thus they are the opposite of the
connected Calypso signal names.  For the MODEM UART a complete 8-signal
interface with full modem control is defined, but the Calypso only provides
TxD & RxD, RTS & CTS, thus the other 4 modem control signals are GPIOs.  The
signals which are defined as DTR and DCD from the host's perspective are
connected to GPIOs 3 and 2, respectively, just like on TI's C-Sample and
D-Sample boards, whereas the choices of GPIOs for DSR and RI are Huawei's own
arbitrary picks, as TI's development boards did not provide these signals.

Power control signals
=====================

Interface pin 13 (called VDD in the manual) appears to be connected to the V-IO
rail inside.

Interface pin 15 (PWON) is connected directly to Iota PWON as expected.

Interface pin 31 (called RST in the manual) appears to be connected to Iota
nTESTRESET through the same transistor circuit as on TI's development boards,
i.e., the signal brought out on the module interface is not raw nTESTRESET, but
what we call XDS_RESET, originally meant to be driven by TI's XDS510 and XDS560
"emulator" pods.

Other signals
=============

Interface pin 14 (called ADC in the manual) is connected to Iota ADIN1.

Interface pin 32 (called LPG in the manual) is indeed connected to Calypso ball
DSR_MODEM/LPG, which Huawei's firmware configures to be the LPG output.