FreeCalypso > hg > freecalypso-reveng
changeset 247:1e1191fbdf90
pirelli/fw-disasm: abb_core_inth located
| author | Mychaela Falconia <falcon@freecalypso.org> |
|---|---|
| date | Sun, 24 Dec 2017 01:19:25 +0000 |
| parents | b2002dcbad3d |
| children | 73039e3416c7 |
| files | pirelli/fw-disasm |
| diffstat | 1 files changed, 97 insertions(+), 0 deletions(-) [+] |
line wrap: on
line diff
--- a/pirelli/fw-disasm Sun Dec 24 00:03:49 2017 +0000 +++ b/pirelli/fw-disasm Sun Dec 24 01:19:25 2017 +0000 @@ -1732,6 +1732,100 @@ 3cdaa0: 2000 mov r0, #0 3cdaa2: bd00 pop {pc} +$Create_ABB_HISR: + 3dc928: b500 push {lr} + 3dc92a: b083 sub sp, #12 ; 0xc + 3dc92c: 485d ldr r0, =0x1764a10 ; via 0x3dcaa4 + 3dc92e: 21fe mov r1, #254 ; 0xfe + 3dc930: 2201 mov r2, #1 + 3dc932: 0252 lsl r2, r2, #9 + 3dc934: f01b fc12 bl 0x3f815c ; memset() + 3dc938: 485a ldr r0, =0x1764a10 ; via 0x3dcaa4 + 3dc93a: 9000 str r0, [sp, #0] + 3dc93c: 2001 mov r0, #1 + 3dc93e: 0240 lsl r0, r0, #9 + 3dc940: 9001 str r0, [sp, #4] + 3dc942: 4859 ldr r0, =0x17649b8 ; via 0x3dcaa8 + 3dc944: a127 add r1, pc, #156 ; 0x9c + 3dc946: 4a59 ldr r2, =0x3dc967 ; via 0x3dcaac + 3dc948: 2302 mov r3, #2 + 3dc94a: f01c ff3f bl 0x3f97cc ; $TCCE_Create_HISR + 3dc94e: b003 add sp, #12 ; 0xc + 3dc950: bd00 pop {pc} + +$Activate_ABB_HISR: + 3dc952: b500 push {lr} + 3dc954: 4854 ldr r0, =0x17649b8 ; via 0x3dcaa8 + 3dc956: f01c ff41 bl 0x3f97dc ; $TCCE_Activate_HISR + 3dc95a: 2800 cmp r0, #0 + 3dc95c: d001 beq 0x3dc962 + 3dc95e: 2001 mov r0, #1 + 3dc960: bd00 pop {pc} + 3dc962: 2000 mov r0, #0 + 3dc964: bd00 pop {pc} + +$EXT_HisrEntry: + 3dc966: b500 push {lr} + 3dc968: b083 sub sp, #12 ; 0xc + 3dc96a: 4851 ldr r0, =0x1774e38 ; via 0x3dcab0 + 3dc96c: 6800 ldr r0, [r0, #0] + 3dc96e: 2800 cmp r0, #0 + 3dc970: d02a beq 0x3dc9c8 + 3dc972: 2134 mov r1, #52 ; 0x34 + 3dc974: 484e ldr r0, =0x1774e38 ; via 0x3dcab0 + 3dc976: 6800 ldr r0, [r0, #0] + 3dc978: 5c08 ldrb r0, [r1, r0] + 3dc97a: 2800 cmp r0, #0 + 3dc97c: d01f beq 0x3dc9be + 3dc97e: 484c ldr r0, =0x1774e38 ; via 0x3dcab0 + 3dc980: 6800 ldr r0, [r0, #0] + 3dc982: 8800 ldrh r0, [r0, #0] + 3dc984: 210c mov r1, #12 ; 0xc + 3dc986: aa02 add r2, sp, #8 + 3dc988: f5e8 f81e bl 0x1c49c8 ; rvf_get_buf() + 3dc98c: 2802 cmp r0, #2 + 3dc98e: d104 bne 0x3dc99a + 3dc990: 4848 ldr r0, =0xa0010 ; via 0x3dcab4 + 3dc992: 9000 str r0, [sp, #0] + 3dc994: a016 add r0, pc, #88 ; 0x58 + 3dc996: 2142 mov r1, #66 ; 0x42 + 3dc998: e01a b 0x3dc9d0 + 3dc99a: 9902 ldr r1, [sp, #8] + 3dc99c: 2005 mov r0, #5 + 3dc99e: 6008 str r0, [r1, #0] + 3dc9a0: 9902 ldr r1, [sp, #8] + 3dc9a2: 4843 ldr r0, =0x1774e38 ; via 0x3dcab0 + 3dc9a4: 6800 ldr r0, [r0, #0] + 3dc9a6: 7880 ldrb r0, [r0, #2] + 3dc9a8: 7248 strb r0, [r1, #9] + 3dc9aa: 9802 ldr r0, [sp, #8] +; $spi_abb_read_int_reg_callback = 0x39efc4 + 3dc9ac: 4942 ldr r1, =0x39efc5 ; via 0x3dcab8 + 3dc9ae: 6041 str r1, [r0, #4] + 3dc9b0: 483f ldr r0, =0x1774e38 ; via 0x3dcab0 + 3dc9b2: 6800 ldr r0, [r0, #0] + 3dc9b4: 7880 ldrb r0, [r0, #2] + 3dc9b6: 9902 ldr r1, [sp, #8] + 3dc9b8: f7dc faf2 bl 0x3b8fa0 ; $rvf_send_msg + 3dc9bc: e010 b 0x3dc9e0 + 3dc9be: 483d ldr r0, =0xa0010 ; via 0x3dcab4 + 3dc9c0: 9000 str r0, [sp, #0] + 3dc9c2: a01c add r0, pc, #112 ; 0x70 + 3dc9c4: 2138 mov r1, #56 ; 0x38 + 3dc9c6: e003 b 0x3dc9d0 + 3dc9c8: 483a ldr r0, =0xa0010 ; via 0x3dcab4 + 3dc9ca: 9000 str r0, [sp, #0] + 3dc9cc: a028 add r0, pc, #160 ; 0xa0 + 3dc9ce: 2133 mov r1, #51 ; 0x33 + 3dc9d0: 2200 mov r2, #0 + 3dc9d2: 43d2 mvn r2, r2 + 3dc9d4: 2301 mov r3, #1 + 3dc9d6: f7fe f92d bl 0x3dac34 + 3dc9da: 200c mov r0, #12 ; 0xc + 3dc9dc: f003 f967 bl 0x3dfcae + 3dc9e0: b003 add sp, #12 ; 0xc + 3dc9e2: bd00 pop {pc} + _f_checksum: 3e6990: e1a0c000 mov r12, r0 3e6994: e3a00000 mov r0, #0 @@ -2231,6 +2325,9 @@ XRAM data: +0x17649b8: ABB_Hisr +0x1764a10: ABB_HisrStack + 0x17741e0: abb_sem 0x1774e38: SPI_GBL_INFO_PTR