FreeCalypso > hg > freecalypso-reveng
changeset 242:5eca9fccd706
pirelli/fw-disasm: pwr_env code located
author | Mychaela Falconia <falcon@freecalypso.org> |
---|---|
date | Sat, 23 Dec 2017 03:56:02 +0000 |
parents | cead37b6ff74 |
children | 83715e0c65de |
files | pirelli/fw-disasm |
diffstat | 1 files changed, 188 insertions(+), 0 deletions(-) [+] |
line wrap: on
line diff
--- a/pirelli/fw-disasm Sat Dec 23 01:46:05 2017 +0000 +++ b/pirelli/fw-disasm Sat Dec 23 03:56:02 2017 +0000 @@ -966,6 +966,191 @@ 3cd88c: 4770 bx lr 3cd88e: 46c0 nop (mov r8, r8) +$pwr_get_info: +; perfect match to TI's original + 3cd954: b530 push {r4, r5, lr} + 3cd956: 1c04 add r4, r0, #0 + 3cd958: 2000 mov r0, #0 + 3cd95a: 6020 str r0, [r4, #0] + 3cd95c: 487a ldr r0, =0xa0020 ; via 0x3cdb48 + 3cd95e: 6120 str r0, [r4, #16] ; 0x10 + 3cd960: 2004 mov r0, #4 + 3cd962: 1900 add r0, r0, r4 + 3cd964: a14f add r1, pc, #316 ; 0x13c + 3cd966: 2204 mov r2, #4 + 3cd968: f029 fc68 bl 0x3f723c ; memcpy() + 3cd96c: 2188 mov r1, #136 ; 0x88 + 3cd96e: 2000 mov r0, #0 + 3cd970: 5108 str r0, [r1, r4] + 3cd972: 2084 mov r0, #132 ; 0x84 + 3cd974: 2100 mov r1, #0 + 3cd976: 5501 strb r1, [r0, r4] + 3cd978: 2501 mov r5, #1 + 3cd97a: 7625 strb r5, [r4, #24] ; 0x18 + 3cd97c: 201c mov r0, #28 ; 0x1c + 3cd97e: 1900 add r0, r0, r4 + 3cd980: a149 add r1, pc, #292 ; 0x124 + 3cd982: 2209 mov r2, #9 + 3cd984: f029 fc5a bl 0x3f723c ; memcpy() + 3cd988: 207d mov r0, #125 ; 0x7d + 3cd98a: 00c0 lsl r0, r0, #3 + 3cd98c: 62a0 str r0, [r4, #40] ; 0x28 + 3cd98e: 2019 mov r0, #25 ; 0x19 + 3cd990: 0140 lsl r0, r0, #5 + 3cd992: 62e0 str r0, [r4, #44] ; 0x2c + 3cd994: 2058 mov r0, #88 ; 0x58 + 3cd996: 5505 strb r5, [r0, r4] + 3cd998: 486c ldr r0, =0xa0010 ; via 0x3cdb4c + 3cd99a: 65e0 str r0, [r4, #92] ; 0x5c + 3cd99c: 208c mov r0, #140 ; 0x8c + 3cd99e: 496c ldr r1, =0x3cd9bf ; via 0x3cdb50 + 3cd9a0: 5101 str r1, [r0, r4] + 3cd9a2: 2090 mov r0, #144 ; 0x90 + 3cd9a4: 496b ldr r1, =0x3cda8b ; via 0x3cdb54 + 3cd9a6: 5101 str r1, [r0, r4] + 3cd9a8: 2094 mov r0, #148 ; 0x94 + 3cd9aa: 496b ldr r1, =0x3cda8f ; via 0x3cdb58 + 3cd9ac: 5101 str r1, [r0, r4] + 3cd9ae: 2098 mov r0, #152 ; 0x98 + 3cd9b0: 496a ldr r1, =0x3cda93 ; via 0x3cdb5c + 3cd9b2: 5101 str r1, [r0, r4] + 3cd9b4: 219c mov r1, #156 ; 0x9c + 3cd9b6: 486a ldr r0, =0x3cda97 ; via 0x3cdb60 + 3cd9b8: 5108 str r0, [r1, r4] + 3cd9ba: 2000 mov r0, #0 + 3cd9bc: bd30 pop {r4, r5, pc} + +$pwr_set_info: + 3cd9be: b570 push {r4, r5, r6, lr} + 3cd9c0: b082 sub sp, #8 + 3cd9c2: 1c1d add r5, r3, #0 + 3cd9c4: 1c14 add r4, r2, #0 + 3cd9c6: 4860 ldr r0, =0xa0020 ; via 0x3cdb48 + 3cd9c8: 9000 str r0, [sp, #0] + 3cd9ca: a03a add r0, pc, #232 ; 0xe8 + 3cd9cc: 213c mov r1, #60 ; 0x3c + 3cd9ce: 2200 mov r2, #0 + 3cd9d0: 43d2 mvn r2, r2 + 3cd9d2: 2303 mov r3, #3 + 3cd9d4: f00d f92e bl 0x3dac34 + 3cd9d8: 8820 ldrh r0, [r4, #0] +; struct allocation size differs from original + 3cd9da: 214c mov r1, #76 ; 0x4c + 3cd9dc: 4a61 ldr r2, =0x1774e70 ; via 0x3cdb64 + 3cd9de: f5f6 fff3 bl 0x1c49c8 + 3cd9e2: 2802 cmp r0, #2 + 3cd9e4: d10b bne 0x3cd9fe + 3cd9e6: 4858 ldr r0, =0xa0020 ; via 0x3cdb48 + 3cd9e8: 9000 str r0, [sp, #0] + 3cd9ea: a042 add r0, pc, #264 ; 0x108 + 3cd9ec: 2156 mov r1, #86 ; 0x56 + 3cd9ee: 2200 mov r2, #0 + 3cd9f0: 43d2 mvn r2, r2 + 3cd9f2: 2301 mov r3, #1 + 3cd9f4: f00d f91e bl 0x3dac34 + 3cd9f8: 2004 mov r0, #4 + 3cd9fa: 43c0 mvn r0, r0 + 3cd9fc: e043 b 0x3cda86 + 3cd9fe: 485a ldr r0, =0x1774e74 ; via 0x3cdb68 + 3cda00: 6005 str r5, [r0, #0] + 3cda02: 4b58 ldr r3, =0x1774e70 ; via 0x3cdb64 + 3cda04: 6819 ldr r1, [r3, #0] + 3cda06: 4859 ldr r0, =0x1774e38 ; via 0x3cdb6c + 3cda08: 6800 ldr r0, [r0, #0] + 3cda0a: 7880 ldrb r0, [r0, #2] + 3cda0c: 7088 strb r0, [r1, #2] + 3cda0e: 6818 ldr r0, [r3, #0] + 3cda10: 8821 ldrh r1, [r4, #0] + 3cda12: 8001 strh r1, [r0, #0] + 3cda14: 2200 mov r2, #0 + 3cda16: 6818 ldr r0, [r3, #0] + 3cda18: 6042 str r2, [r0, #4] + 3cda1a: 6819 ldr r1, [r3, #0] +; end of charge current + 3cda1c: 207a mov r0, #122 ; 0x7a + 3cda1e: 8148 strh r0, [r1, #10] ; 0xa +; pwr_env_ctrl_blk->max_voltage_code is set to: +; (0x426800 - adccal_b*1024) / adccal_a +; 0x426800 >> 10 = 0x109A = 4250 + 3cda20: 4c53 ldr r4, =0x426800 ; via 0x3cdb70 + 3cda22: 4954 ldr r1, =0x801746 ; via 0x3cdb74 + 3cda24: 2000 mov r0, #0 + 3cda26: 5e08 ldrsh r0, [r1, r0] + 3cda28: 0280 lsl r0, r0, #10 + 3cda2a: 1a20 sub r0, r4, r0 + 3cda2c: 4952 ldr r1, =0x801734 ; via 0x3cdb78 + 3cda2e: 8809 ldrh r1, [r1, #0] + 3cda30: f029 fbe4 bl 0x3f71fc ; U$DIV +; MV100-matching logic continues + 3cda34: 6818 ldr r0, [r3, #0] + 3cda36: 8181 strh r1, [r0, #12] ; 0xc + 3cda38: 0610 lsl r0, r2, #24 + 3cda3a: 0e01 lsr r1, r0, #24 + 3cda3c: 6818 ldr r0, [r3, #0] + 3cda3e: 7401 strb r1, [r0, #16] ; 0x10 + 3cda40: 24ff mov r4, #255 ; 0xff + 3cda42: 6818 ldr r0, [r3, #0] + 3cda44: 7504 strb r4, [r0, #20] ; 0x14 + 3cda46: 2000 mov r0, #0 + 3cda48: 681d ldr r5, [r3, #0] + 3cda4a: 61a8 str r0, [r5, #24] ; 0x18 + 3cda4c: 681e ldr r6, [r3, #0] + 3cda4e: 2505 mov r5, #5 + 3cda50: 7735 strb r5, [r6, #28] ; 0x1c + 3cda52: 2620 mov r6, #32 ; 0x20 + 3cda54: 681d ldr r5, [r3, #0] + 3cda56: 5574 strb r4, [r6, r5] + 3cda58: 681d ldr r5, [r3, #0] + 3cda5a: 6268 str r0, [r5, #36] ; 0x24 + 3cda5c: 2628 mov r6, #40 ; 0x28 + 3cda5e: 681d ldr r5, [r3, #0] + 3cda60: 5574 strb r4, [r6, r5] + 3cda62: 681c ldr r4, [r3, #0] + 3cda64: 62e0 str r0, [r4, #44] ; 0x2c + 3cda66: 6818 ldr r0, [r3, #0] + 3cda68: 8702 strh r2, [r0, #56] ; 0x38 + 3cda6a: 2001 mov r0, #1 + 3cda6c: 681c ldr r4, [r3, #0] + 3cda6e: 6320 str r0, [r4, #48] ; 0x30 +; new since original: pwr_env_ctrl_blk->i2v_madc_offset = 0 + 3cda70: 681c ldr r4, [r3, #0] + 3cda72: 8122 strh r2, [r4, #8] +; new stuff: +; halfword at 0x40 = 1 +; word at 0x44 = 0 +; byte at 0x48 = 0 + 3cda74: 2540 mov r5, #64 ; 0x40 + 3cda76: 681c ldr r4, [r3, #0] + 3cda78: 5328 strh r0, [r5, r4] + 3cda7a: 6818 ldr r0, [r3, #0] + 3cda7c: 6442 str r2, [r0, #68] ; 0x44 + 3cda7e: 2248 mov r2, #72 ; 0x48 + 3cda80: 6818 ldr r0, [r3, #0] + 3cda82: 5411 strb r1, [r2, r0] + 3cda84: 2000 mov r0, #0 + 3cda86: b002 add sp, #8 + 3cda88: bd70 pop {r4, r5, r6, pc} + +$pwr_init: + 3cda8a: 2000 mov r0, #0 + 3cda8c: 4770 bx lr + +$pwr_start: + 3cda8e: 2000 mov r0, #0 + 3cda90: 4770 bx lr + +$pwr_stop: + 3cda92: 2000 mov r0, #0 + 3cda94: 4770 bx lr + +$pwr_kill: + 3cda96: b500 push {lr} + 3cda98: 4832 ldr r0, =0x1774e70 ; via 0x3cdb64 + 3cda9a: 6800 ldr r0, [r0, #0] + 3cda9c: f5f7 f92c bl 0x1c4cf8 + 3cdaa0: 2000 mov r0, #0 + 3cdaa2: bd00 pop {pc} + _f_checksum: 3e6990: e1a0c000 mov r12, r0 3e6994: e3a00000 mov r0, #0 @@ -1458,3 +1643,6 @@ 0x1774e38: SPI_GBL_INFO_PTR 0x1774e3c: spi_error_ft + +0x1774e70: pwr_env_ctrl_blk +0x1774e74: pwr_error_ft