--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/pirelli/calypso	Sat Apr 20 00:56:45 2013 +0000
@@ -0,0 +1,45 @@
+Calypso pin I thought was nIBOOT (N1), but actually seems to be A13 (RFEN):
+the trace from the ball goes straight down to a via, L1 image coords
+(3676,1174).  On L2 trace goes to another via at (3234,1074).  On L5 it goes
+to yet another via at (2950,535).  On L4 it goes to (1941,457).  On L2 it goes
+to a surface via at (1957,484).  Back on L1 it goes to Rita pin 2 (XEN).
+This arrangement matches what the Rita spec describes as the "external VCTCXO"
+configuration.  In contrast, the Leonardo schematics depict the "internal
+VCTCXO" configuration.
+
+Double-checking: in the "external VCTCXO" configuration Rita pin 1 (XSEL) is
+supposed to be grounded.  On L1 the pad appears to go nowhere (isolated).
+The central coordinates of the pad on L1 are (1956,638).  On L2 there is
+solid copper fill in that area.  Perhaps there is an invisible micro-via?
+
+The real nIBOOT pin (N1): stays on L1, a trace takes it to one pad of a
+2-pad SMT component, the other pad's connection is unclear (appears isolated,
+must be an invisible micro-via).  Must be a pull-up/down resistor, hopefully
+pull-down.
+
+nCS0 (C2): L1 trace to (4262,1016).  On L2 it goes to two via points:
+(4852,1016), an obvious larger via, and (4802,1000), a spot where a micro-via
+back to L1 could hide.  The micro-via back to L1 appears to be there indeed,
+feeding an unmasked test point on the surface.  Back to the main trace at
+(4852,1016): there's something on L4 (might be a trace to another nearby via),
+but maybe it's nothing, just a poor picture.  Most likely nothing there, as
+the same arrangement appears on L5 and L6, but clearly with no connection
+between the two nearby vias.  L7 is probably where the interesting connection
+is, but the trace appears to have been scraped off in that spot in steve-m's
+layer-grinding process.
+
+Taking a different approach: let's start with the RAM/flash MCP on L8.  Flash
+CE1# goes to (4911,987); flash CE2# goes to (4954,660) and to an L8 test pad;
+OE# goes to (4885,982); RAM CE1# goes to (4860,978).  Of the two L2-L7 vias,
+the upper one appears to be RAM, and the lower one appears to be flash.
+
+Mistake found: I had earlier messed up trying to trace nCS0 on L2.  Now it's
+all clear: nCS0 goes to flash CE1#.
+
+Now let's trace the RAM CS.  From the upper L2-L7 via it goes on L2 to
+(4800,1002) - already known to be a test point - and to (4212,978).
+On L1 it goes to Calypso pin C3 - nCS1, just like on Leonardo.
+
+Now let's trace flash CE2#.  L7-L8 via at (4954,660); L2-L7 via at (4965,927);
+on L2 it goes to (4210,930), on L1 it goes to Calypso ball D3.
+That's nCS3.

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/pirelli/pcb	Sat Apr 20 00:56:45 2013 +0000
@@ -0,0 +1,13 @@
+The Pirelli DP-L10 PCB appears to have 8 layers.  Following the good old DEC
+convention, I shall refer to them as L1 through L8.  Not knowing the original
+designers' intended identification, I have arbitrarily assigned L1 to be the
+battery/SIM side and L8 to be the display/keypad side.  This numbering direction
+makes it easier to work with steve-m's grind-down pictures.
+
+Via structure: there don't seem to be too many all-the-way-through vias, if
+any at all, other than maybe the grounding ones around the edges of the board.
+Instead most/all internal vias are blind, spanning from L2 through L7.
+At both surfaces there are micro-vias (with many/most of them one can't even
+see the hope in steve-m's pictures, only a copper circle which one has to
+infer is an "annulus" for a micro-via), and these micro-vias only go one layer
+deep: from L1 to L2, and from L8 to L7.