FreeCalypso > hg > freecalypso-reveng
changeset 195:ed7318a03e0c
pirelli/vctcxo: VCTCXO connections traced out
author | Michael Spacefalcon <falcon@ivan.Harhan.ORG> |
---|---|
date | Sun, 11 Jan 2015 04:33:48 +0000 |
parents | 805e99848aea |
children | 3147e960aeff |
files | pirelli/vctcxo |
diffstat | 1 files changed, 32 insertions(+), 0 deletions(-) [+] |
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--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/pirelli/vctcxo Sun Jan 11 04:33:48 2015 +0000 @@ -0,0 +1,32 @@ +Let's trace the TCXOEN signal from the Calypso. Calypso ball A12, no trace +visible, guessing a micro-via right under the ball. L1 coord (3739,1053). +Guess appears right: on L2 there is a connection from a micro-via to an inner +via, the latter is at (3712,1055). Found it on L4: the via is in the middle of +a trace going both ways! Right branch goes to (4548,1028); left branch goes to +(1699,1349). + +Following the branch at (4548,1028): found it on L2, microvia back to L1 at +(4518,1048). Found it on L1, goes to some 2-pad footprint, can't tell if it's +unpopulated or a faint black resistor. The other end goes to a via at +(4676,919). Found it on L2, goes to inner via at (5135,684). Found it on L7, +goes to surface via at (5132,716). Found it on L8 - goes to flash RY/BY# ball +- WTF? + +Following the branch at (1699,1349): found it on L2, immediately goes back to +L1 at (1673,1353). Found it on L1, go to UL pad of the VCTCXO, passing by a +cap to GND. The cap is populated. + +Let's trace the signal from the VCTCXO to the Rita. VCTCXO pin is unknown, but +the input to Rita corresponds to a surface via at (2161,488) - at this point on +L1 there is an unpopulated cap(?) to GND and a series component (cap?) to the +actual Rita input. Found it on L2, goes back to L1 at (2123,1284). On L1 it +falls right into the UR pad of the VCTCXO! Conclusion: the signal from VCTCXO +to Rita passes through a single series component, just like in Rita datasheet. + +The LR pad of the VCTCXO is GND. Thus the control input must be the LL pad. +The input signal to here passes first through a series component, then passes +by a comp to ground, and then goes into the VCTCXO input. The entry point to +the whole arrangement is a surface via at (1669,1488). Found it on L2, inner +via at (1655,1467). Found it on L4, goes to (2932,855). Found it on L2, +surface via to L1 at (2950,837). That's Iota ball J4 (AFC), and there is also +a branch from there that goes to an unpopulated cap(?) footprint to GND.