FreeCalypso > hg > freecalypso-schem2

annotate venus/src/top/board.v @ 44:04abc82f8280

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MCL and primitives: LCD and MAX1916 from lunalcd2
author Mychaela Falconia <falcon@freecalypso.org>
date Sat, 27 Nov 2021 01:09:05 +0000
parents 4baae6215619
children 541b55e6bf47
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1 /*
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2 * This structural Verilog module is the top level for FC Venus board.
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3 * It interconnects the two principal domains: mobile and USB.
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4 */
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5
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6 module board ();
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7
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8 wire GND, VBUS, VCHG;
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9
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10 wire Host_TxD, Host_RxD, Host_RTS, Host_CTS;
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11 wire Host_DTR, Host_DCD, Host_RI, Host_TxD2, Host_RxD2;
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12
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13 wire RPWON, nTESTRESET;
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15 /* mobile and USB domains */
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17 mobile mob (.GND(GND),
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18 .VCHG(VCHG),
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19 .Host_TxD(Host_TxD),
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20 .Host_RxD(Host_RxD),
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21 .Host_RTS(Host_RTS),
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22 .Host_CTS(Host_CTS),
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23 .Host_DTR(Host_DTR),
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24 .Host_DCD(Host_DCD),
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25 .Host_RI(Host_RI),
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26 .Host_TxD2(Host_TxD2),
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27 .Host_RxD2(Host_RxD2),
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28 .RPWON(RPWON),
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29 .nTESTRESET(nTESTRESET)
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30 );
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31
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32 usb_domain usb (.GND(GND),
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33 .VBUS(VBUS),
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34 .Host_TxD(Host_TxD),
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35 .Host_RxD(Host_RxD),
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36 .Host_RTS(Host_RTS),
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37 .Host_CTS(Host_CTS),
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38 .Host_DTR(Host_DTR),
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39 .Host_DCD(Host_DCD),
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40 .Host_RI(Host_RI),
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41 .Host_TxD2(Host_TxD2),
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42 .Host_RxD2(Host_RxD2),
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43 .RPWON(RPWON),
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44 .nTESTRESET(nTESTRESET)
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45 );
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46
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47 /* charging control switch */
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48
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49 switch_2pin chg_switch (VBUS, VCHG);
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51 /* pull-down resistors before and after the switch */
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52
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53 resistor VBUS_pulldown (VBUS, GND);
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54 resistor VCHG_pulldown (VCHG, GND);
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56 endmodule