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annotate venus/doc/Flash+RAM @ 88:09cda55086b1

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venus/doc/Flash+RAM written
author Mychaela Falconia <falcon@freecalypso.org>
date Fri, 10 Dec 2021 20:26:05 +0000
parents
children e8ce3b688723
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09cda55086b1 venus/doc/Flash+RAM written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1 All historical Calypso phone or modem designs which we (FreeCalypso) consider
09cda55086b1 venus/doc/Flash+RAM written
Mychaela Falconia <falcon@freecalypso.org>
parents:
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2 interesting enough to copy use a combined MCP (multi-chip package) for their
09cda55086b1 venus/doc/Flash+RAM written
Mychaela Falconia <falcon@freecalypso.org>
parents:
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3 flash and XRAM, the latter being our term for board-level RAM, as opposed to the
09cda55086b1 venus/doc/Flash+RAM written
Mychaela Falconia <falcon@freecalypso.org>
parents:
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4 relatively small IRAM inside the Calypso chip itself. The following Spansion
09cda55086b1 venus/doc/Flash+RAM written
Mychaela Falconia <falcon@freecalypso.org>
parents:
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5 MCPs (all of them no longer made and available only from surplus, sadly) are
09cda55086b1 venus/doc/Flash+RAM written
Mychaela Falconia <falcon@freecalypso.org>
parents:
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6 most interesting to us:
09cda55086b1 venus/doc/Flash+RAM written
Mychaela Falconia <falcon@freecalypso.org>
parents:
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7
09cda55086b1 venus/doc/Flash+RAM written
Mychaela Falconia <falcon@freecalypso.org>
parents:
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8 * S71PL032J (4 MiB flash, various RAM options) would be fine for an AT-command-
09cda55086b1 venus/doc/Flash+RAM written
Mychaela Falconia <falcon@freecalypso.org>
parents:
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9 controlled modem like Openmoko - however, we are not building any such product
09cda55086b1 venus/doc/Flash+RAM written
Mychaela Falconia <falcon@freecalypso.org>
parents:
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10 at the present, and this flash capacity is too small for the functionality
09cda55086b1 venus/doc/Flash+RAM written
Mychaela Falconia <falcon@freecalypso.org>
parents:
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11 that must be supported on FC Venus.
09cda55086b1 venus/doc/Flash+RAM written
Mychaela Falconia <falcon@freecalypso.org>
parents:
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12
09cda55086b1 venus/doc/Flash+RAM written
Mychaela Falconia <falcon@freecalypso.org>
parents:
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13 * S71PL064J is 8 MiB flash with various RAM options; S71PL064JA0 is the version
09cda55086b1 venus/doc/Flash+RAM written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
14 with 2 MiB RAM. The latter part is used inside mass-produced iWOW TR-800
09cda55086b1 venus/doc/Flash+RAM written
Mychaela Falconia <falcon@freecalypso.org>
parents:
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15 modules - there is a rumor that they may have used S71PL064JB0 initially,
09cda55086b1 venus/doc/Flash+RAM written
Mychaela Falconia <falcon@freecalypso.org>
parents:
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16 with 4 MiB RAM, but then went down to 2 MiB - but S71PL064JA0 is the chip
09cda55086b1 venus/doc/Flash+RAM written
Mychaela Falconia <falcon@freecalypso.org>
parents:
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17 inside those TR-800 modules which are presently available as a large surplus.
09cda55086b1 venus/doc/Flash+RAM written
Mychaela Falconia <falcon@freecalypso.org>
parents:
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18 This chip seems ideal: 8 MiB flash + 2 MiB XRAM is sufficient memory capacity
09cda55086b1 venus/doc/Flash+RAM written
Mychaela Falconia <falcon@freecalypso.org>
parents:
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19 for all TCS211 firmware configurations, and the physical footprint of 7x9 mm
09cda55086b1 venus/doc/Flash+RAM written
Mychaela Falconia <falcon@freecalypso.org>
parents:
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20 is the smallest we've ever seen for such MCPs.
09cda55086b1 venus/doc/Flash+RAM written
Mychaela Falconia <falcon@freecalypso.org>
parents:
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21
09cda55086b1 venus/doc/Flash+RAM written
Mychaela Falconia <falcon@freecalypso.org>
parents:
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22 * S71PL129J and S71PL129N are 16 MiB flash families, presented as two flash chip
09cda55086b1 venus/doc/Flash+RAM written
Mychaela Falconia <falcon@freecalypso.org>
parents:
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23 select banks of 8 MiB each, specifically made for use with processors like
09cda55086b1 venus/doc/Flash+RAM written
Mychaela Falconia <falcon@freecalypso.org>
parents:
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24 Calypso that have a limit of 8 MiB per chip select. RAM options are
09cda55086b1 venus/doc/Flash+RAM written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
25 correspondingly large; the chip used on FCDEV3B (copied from Pirelli DP-L10)
09cda55086b1 venus/doc/Flash+RAM written
Mychaela Falconia <falcon@freecalypso.org>
parents:
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26 is S71PL129NC0HFW4B, and the XRAM capacity is 8 MiB. Compared to S71PL-J
09cda55086b1 venus/doc/Flash+RAM written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
27 chips, S71PL129N has more stringent reset timing requirements; the impact on
09cda55086b1 venus/doc/Flash+RAM written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
28 Calypso-based designs is that Calypso FDP output cannot be used as the flash
09cda55086b1 venus/doc/Flash+RAM written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
29 reset signal, and a different circuit based on ON_nOFF signal is needed - and
09cda55086b1 venus/doc/Flash+RAM written
Mychaela Falconia <falcon@freecalypso.org>
parents:
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30 the latter circuit requires adding one more little IC, Nexperia 74AXP1T34, a
09cda55086b1 venus/doc/Flash+RAM written
Mychaela Falconia <falcon@freecalypso.org>
parents:
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31 dual supply translating buffer. The latter design with 74AXP1T34 has been
09cda55086b1 venus/doc/Flash+RAM written
Mychaela Falconia <falcon@freecalypso.org>
parents:
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32 proven on FCDEV3B V2.
09cda55086b1 venus/doc/Flash+RAM written
Mychaela Falconia <falcon@freecalypso.org>
parents:
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33
09cda55086b1 venus/doc/Flash+RAM written
Mychaela Falconia <falcon@freecalypso.org>
parents:
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34 As far as FC Venus PCB design goes, meaning flash+RAM MCP footprint and the
09cda55086b1 venus/doc/Flash+RAM written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
35 flash reset circuit, the following options are up for consideration:
09cda55086b1 venus/doc/Flash+RAM written
Mychaela Falconia <falcon@freecalypso.org>
parents:
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36
09cda55086b1 venus/doc/Flash+RAM written
Mychaela Falconia <falcon@freecalypso.org>
parents:
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37 Option 1: copy the 7x9 mm MCP footprint from iWOW TR-800. This footprint
09cda55086b1 venus/doc/Flash+RAM written
Mychaela Falconia <falcon@freecalypso.org>
parents:
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38 accommodates S71PL064J but not S71PL129J or N; because populating S71PL129N is
09cda55086b1 venus/doc/Flash+RAM written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
39 not possible on this footprint, flash reset can be sourced from Calypso FDP
09cda55086b1 venus/doc/Flash+RAM written
Mychaela Falconia <falcon@freecalypso.org>
parents:
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40 output as was done in TI's original design.
09cda55086b1 venus/doc/Flash+RAM written
Mychaela Falconia <falcon@freecalypso.org>
parents:
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41
09cda55086b1 venus/doc/Flash+RAM written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
42 Option 2: enlarge the MCP footprint to 8x11.6 mm with 8 extra mechanical-only
09cda55086b1 venus/doc/Flash+RAM written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
43 balls, but keep the old and simple reset circuit. This option will allow
09cda55086b1 venus/doc/Flash+RAM written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
44 populating either S71PL064J or S71PL129J, but not S71PL129N - the latter would
09cda55086b1 venus/doc/Flash+RAM written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
45 cause sleep mode problems and sometimes even boot problems as seen on FCDEV3B V1
09cda55086b1 venus/doc/Flash+RAM written
Mychaela Falconia <falcon@freecalypso.org>
parents:
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46 where we made this mistake.
09cda55086b1 venus/doc/Flash+RAM written
Mychaela Falconia <falcon@freecalypso.org>
parents:
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47
09cda55086b1 venus/doc/Flash+RAM written
Mychaela Falconia <falcon@freecalypso.org>
parents:
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48 Option 3: use the larger MCP footprint for 16 MiB flash and also incorporate the
09cda55086b1 venus/doc/Flash+RAM written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
49 74AXP1T34 flash reset circuit from FCDEV3B V2. This option will allow any of
09cda55086b1 venus/doc/Flash+RAM written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
50 S71PL064J, S71PL129J or S71PL129N to be populated and work correctly.
09cda55086b1 venus/doc/Flash+RAM written
Mychaela Falconia <falcon@freecalypso.org>
parents:
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51
09cda55086b1 venus/doc/Flash+RAM written
Mychaela Falconia <falcon@freecalypso.org>
parents:
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52 The Mother's original plan for FC Venus was to do Option 1, but this plan is now
09cda55086b1 venus/doc/Flash+RAM written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
53 being changed to Option 3. The reasons for this change are:
09cda55086b1 venus/doc/Flash+RAM written
Mychaela Falconia <falcon@freecalypso.org>
parents:
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54
09cda55086b1 venus/doc/Flash+RAM written
Mychaela Falconia <falcon@freecalypso.org>
parents:
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55 * S71PL129NC0HFW4B parts are already on hand at FreeCalypso HQ, and have been
09cda55086b1 venus/doc/Flash+RAM written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
56 used successfully in FCDEV3B board builds. With Option 1 we would need to go
09cda55086b1 venus/doc/Flash+RAM written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
57 back to our Chinese grey market supplier and procure S71PL064J chips, and then
09cda55086b1 venus/doc/Flash+RAM written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
58 take the risk of possibly bad parts.
09cda55086b1 venus/doc/Flash+RAM written
Mychaela Falconia <falcon@freecalypso.org>
parents:
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59
09cda55086b1 venus/doc/Flash+RAM written
Mychaela Falconia <falcon@freecalypso.org>
parents:
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60 * For psychological reasons it is important for FC Venus to be a no-worse
09cda55086b1 venus/doc/Flash+RAM written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
61 successor to FCDEV3B. Even though 8 MiB flash + 2 MiB XRAM is perfectly
09cda55086b1 venus/doc/Flash+RAM written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
62 sufficient memory capacity for all of our fw configurations (and according to
09cda55086b1 venus/doc/Flash+RAM written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
63 TI's docs, it would be sufficient even for their pdt_2272 config with MMS
09cda55086b1 venus/doc/Flash+RAM written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
64 functionality, which we don't have), a reduction from FCDEV3B's 16 MiB flash +
09cda55086b1 venus/doc/Flash+RAM written
Mychaela Falconia <falcon@freecalypso.org>
parents:
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65 8 MiB XRAM will undoubtedly be seen by some community members as a downgrade.
09cda55086b1 venus/doc/Flash+RAM written
Mychaela Falconia <falcon@freecalypso.org>
parents:
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66 There is also potential value in being able to load and run non-flashed
09cda55086b1 venus/doc/Flash+RAM written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
67 fc-xram firmware builds, which is only possible with gigantic 8 MiB XRAM.
09cda55086b1 venus/doc/Flash+RAM written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
68
09cda55086b1 venus/doc/Flash+RAM written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
69 * Because *all* of our suitable Spansion MCP options are no-longer-made
09cda55086b1 venus/doc/Flash+RAM written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
70 surplus-only parts (much like the core Calypso chipset itself), it makes good
09cda55086b1 venus/doc/Flash+RAM written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
71 sense to design our PCB in such a way as to allow as many options as possible,
09cda55086b1 venus/doc/Flash+RAM written
Mychaela Falconia <falcon@freecalypso.org>
parents:
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72 not excluding any otherwise suitable (and known) option through our PCB
09cda55086b1 venus/doc/Flash+RAM written
Mychaela Falconia <falcon@freecalypso.org>
parents:
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73 design choices.
09cda55086b1 venus/doc/Flash+RAM written
Mychaela Falconia <falcon@freecalypso.org>
parents:
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74
09cda55086b1 venus/doc/Flash+RAM written
Mychaela Falconia <falcon@freecalypso.org>
parents:
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75 The downside of this chosen approach (compared to our original approach of
09cda55086b1 venus/doc/Flash+RAM written
Mychaela Falconia <falcon@freecalypso.org>
parents:
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76 Option 1) is the increase in MCP BGA footprint, plus the little bit of extra
09cda55086b1 venus/doc/Flash+RAM written
Mychaela Falconia <falcon@freecalypso.org>
parents:
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77 room needed for the 74AXP1T34 IC. The Leonardo core layout inside TR-800 is
09cda55086b1 venus/doc/Flash+RAM written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
78 very tight with no room for any extras, thus if we were seeking to clone or
09cda55086b1 venus/doc/Flash+RAM written
Mychaela Falconia <falcon@freecalypso.org>
parents:
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79 semi-clone a Tango module, this increase in PCB real estate for the flash+RAM
09cda55086b1 venus/doc/Flash+RAM written
Mychaela Falconia <falcon@freecalypso.org>
parents:
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80 MCP would not be acceptable. However, in the case of FC Venus, our core
09cda55086b1 venus/doc/Flash+RAM written
Mychaela Falconia <falcon@freecalypso.org>
parents:
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81 shieldcan section already includes many additions beyond Leonardo/TR-800:
09cda55086b1 venus/doc/Flash+RAM written
Mychaela Falconia <falcon@freecalypso.org>
parents:
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82 consider U401 through U404, all of which need to go into this expanded core
09cda55086b1 venus/doc/Flash+RAM written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
83 section. Thus if we are already expanding the core for other reasons, we should
09cda55086b1 venus/doc/Flash+RAM written
Mychaela Falconia <falcon@freecalypso.org>
parents:
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84 be able to throw in this flash+RAM MCP expansion as well.