annotate venus/src/periph/bl_current_select.v @ 92:148fab6e07e3

add RTC domain test points
author Mychaela Falconia <falcon@freecalypso.org>
date Sat, 11 Dec 2021 04:48:30 +0000
parents 9f5a3567d699
children
Ignore whitespace changes - Everywhere: Within whitespace: At end of lines:
rev   line source
47
9f5a3567d699 progress toward LCD integration
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1 module bl_current_select (GND, Vio, BL_GPIO11, BL_GPIO12, SET);
9f5a3567d699 progress toward LCD integration
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
2
9f5a3567d699 progress toward LCD integration
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
3 input GND, Vio;
9f5a3567d699 progress toward LCD integration
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
4 input BL_GPIO11, BL_GPIO12;
9f5a3567d699 progress toward LCD integration
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
5 output SET;
9f5a3567d699 progress toward LCD integration
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
6
9f5a3567d699 progress toward LCD integration
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
7 wire buf_out_GPIO11, buf_out_GPIO12;
9f5a3567d699 progress toward LCD integration
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
8
9f5a3567d699 progress toward LCD integration
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
9 /* U403 buffer common part */
9f5a3567d699 progress toward LCD integration
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
10 logic_ic_common U403_common (.Vcc(Vio), .GND(GND));
9f5a3567d699 progress toward LCD integration
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
11
9f5a3567d699 progress toward LCD integration
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
12 /* bypass capacitor */
9f5a3567d699 progress toward LCD integration
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
13 capacitor U403_bypass (Vio, GND);
9f5a3567d699 progress toward LCD integration
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
14
9f5a3567d699 progress toward LCD integration
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
15 /* buffer slots */
9f5a3567d699 progress toward LCD integration
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
16 buffer_slot_3state buf_GPIO11 (.A(Vio), .nOE(BL_GPIO11), .Y(buf_out_GPIO11));
9f5a3567d699 progress toward LCD integration
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
17 buffer_slot_3state buf_GPIO12 (.A(Vio), .nOE(BL_GPIO12), .Y(buf_out_GPIO12));
9f5a3567d699 progress toward LCD integration
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
18
9f5a3567d699 progress toward LCD integration
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
19 /* MAX1916 current control resistors */
9f5a3567d699 progress toward LCD integration
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
20 resistor R_fixed (Vio, SET);
9f5a3567d699 progress toward LCD integration
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
21 resistor R_GPIO11 (buf_out_GPIO11, SET);
9f5a3567d699 progress toward LCD integration
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
22 resistor R_GPIO12 (buf_out_GPIO12, SET);
9f5a3567d699 progress toward LCD integration
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
23
9f5a3567d699 progress toward LCD integration
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
24 endmodule