FreeCalypso > hg > freecalypso-schem2

annotate venus/src/primitives @ 18:2f344ca2c1e4

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Venus src: jtag_if.v adapted from FCDEV3B
author Mychaela Falconia <falcon@freecalypso.org>
date Sat, 20 Nov 2021 04:32:50 +0000
parents 3d5c40988a6b
children 22ac331aa0f8
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1 /*
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2 * This file defines the primitives to be instantiated from the structural
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3 * Verilog source for the board: IC package types, basic components and
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4 * subpackages to be mapped later in the MCL binding step.
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5 */
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6
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7 resistor numpins 2;
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8 capacitor numpins 2;
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9 inductor numpins 2;
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10 rlc_generic numpins 2; /* "any" RLC for matching network topologies */
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11 starpoint numpins 2;
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12
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13 resistor_slot mapped_pins (side1, side2);
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14 transistor_slot mapped_pins (E, B, C);
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15 mosfet mapped_pins (G, S, D);
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16
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17 /* TI packages */
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18 pkg_179GHH grid "pkg_179GHH.bgadef";
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19 pkg_100GGM grid "pkg_100GGM.bgadef";
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20 pkg_Rita_RF numpins 49;
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21 pkg_TPA6203A1 mapped_pins (BYPASS, GND, In_neg, In_pos, SHUTDOWN, VDD,
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22 Out_pos, Out_neg);
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23
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24 /* non-TI RF components */
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25 pkg_RF3166 numpins 31;
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26 pkg_M034F numpins 19;
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27
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28 /* Flash+RAM MCP (two possibilities) */
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29 pkg_TLA064 grid "pkg_TLA064.bgadef";
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30 pkg_TLC056 grid "pkg_TLC056.bgadef";
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31
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32 /* misc IC packages */
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33 pkg_XSON6 numpins 6;
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35 /* logic IC subpackages */
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36 buffer_slot_basic mapped_pins (A, Y);
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37 buffer_slot_3state mapped_pins (A, nOE, Y);
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38 logic_ic_common mapped_pins (Vcc, GND);
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39 x541_common mapped_pins (Vcc, GND, nOE1, nOE2);
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40
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41 /* crystal oscillator components */
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42 xtal_2pin_pkg numpins 2;
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43 xtal_4pin_pkg numpins 4;
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44 varactor_diode mapped_pins (Anode, Cathode);
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45
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46 /*
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47 * The reference design we are copying calls for a couple of RF chip
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48 * attenuators. They are symmetrical in that pins 1 and 2 are equally
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49 * suitable as either the input or the output, but the package shape is
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50 * asymmetrical, thus it is a PCB layout decision which pin will be the
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51 * input and which will be the output.
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52 *
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53 * We shall use a mapped_pins primitive and two different pinout mappings
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54 * at the MCL binding stage, to be selected at layout time.
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55 */
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56
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57 chip_attenuator mapped_pins (In, Out, GND1, GND2);
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58
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59 /* connectors */
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60 header_2pin numpins 2;
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61 conn_3pin numpins 3;
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62 header_14pin numpins 14;
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63 pkg_SMA_F numpins 5;
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64 pkg_TRRS_jack numpins 6;
6
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65
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66 /* misc peripherals */
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67 pkg_SIM_socket numpins 8;
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68 basic_LED mapped_pins (Anode, Cathode);