FreeCalypso > hg > freecalypso-schem2
annotate venus/src/top/mobile.v @ 38:32b848a081a3
venus/doc/USB-and-mobile-domains treatise written
author | Mychaela Falconia <falcon@freecalypso.org> |
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date | Fri, 26 Nov 2021 23:02:19 +0000 |
parents | dfa0d08d8f2b |
children | df16d0eabf8a |
rev | line source |
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19
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Mychaela Falconia <falcon@freecalypso.org>
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1 /* |
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2 * This Verilog module is the top level for the mobile domain of FC Venus, |
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3 * i.e., everything that isn't in the USB domain. |
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4 */ |
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5 |
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6 module mobile (GND, VCHG, Host_TxD, Host_RxD, Host_RTS, Host_CTS, |
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7 Host_DTR, Host_DCD, Host_RI, Host_TxD2, Host_RxD2, |
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8 RPWON, nTESTRESET); |
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9 |
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10 input GND, VCHG; |
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11 input Host_TxD, Host_RTS, Host_DTR, Host_TxD2; |
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12 output Host_RxD, Host_CTS, Host_DCD, Host_RI, Host_RxD2; |
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13 input RPWON, nTESTRESET; |
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14 |
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15 /* all wires for the top level of the mobile domain */ |
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16 |
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17 wire VBAT, VSIM, Vio; |
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18 |
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19 wire PWON, ON_nOFF; |
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20 |
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21 wire TDI, TCK, TMS, TDO; |
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22 |
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23 wire [22:0] MCU_A; |
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24 wire [15:0] MCU_D; |
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25 wire MCU_RnW, MCU_nFWE, MCU_nFOE; |
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26 wire LCD_CS, LCD_RESET; |
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27 |
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28 wire GPIO1_SPKR, GPIO3_DTR, GPIO6_headset; |
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29 wire BL_GPIO9, BL_GPIO10, BL_GPIO11, BL_GPIO12; |
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30 |
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31 wire RX_IRDA, RX_MODEM, CTS_MODEM; |
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32 |
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33 wire [4:0] KBC, KBR; |
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34 wire DSR_LPG, BU_PWT, LT_PWL; |
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35 |
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36 wire ADIN1, ADIN2, ADIN3; |
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37 |
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38 wire AUXI, AUXON, AUXOP; |
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39 wire EARN, EARP; |
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40 wire HSMICBIAS, HSO, HSMICP; |
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41 wire MICBIAS, MICIN, MICIP; |
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42 |
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43 wire LED_B; /* ueda blemish */ |
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44 wire LED_C; /* actually used */ |
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45 |
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46 wire ICTL, PCHG, VBATS, VCCS; |
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47 |
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48 wire SIM_CLK, SIM_RST, SIM_IO, SIM_CD; |
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49 wire ANTENNA; |
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50 |
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51 /* instantiate the core */ |
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52 |
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53 core core (.GND(GND), |
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54 .VBAT1(VBAT), |
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55 .VBAT2(VBAT), |
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56 .VBAT3(VBAT), |
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57 .VSIM(VSIM), |
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58 .Vio(Vio), |
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59 .PWON(PWON), |
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60 .RPWON(RPWON), |
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61 .nTESTRESET(nTESTRESET), |
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62 .ON_nOFF(ON_nOFF), |
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63 .TDI(TDI), |
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64 .TDO(TDO), |
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65 .TCK(TCK), |
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66 .TMS(TMS), |
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67 .MCU_A(MCU_A), |
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68 .MCU_D(MCU_D), |
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69 .MCU_RnW(MCU_RnW), |
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70 .MCU_nFWE(MCU_nFWE), |
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71 .MCU_nFOE(MCU_nFOE), |
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72 .EXT_nCS3(LCD_CS), |
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73 .EXT_nCS4(), /* not used on FC Venus */ |
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74 /* uWire/I2C interface unused */ |
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75 .SCLK(), |
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76 .SDO(), |
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77 .SDI_SDA(), |
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78 .nSCS0_SCL(), |
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79 .nSCS1(), |
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80 /* Calypso UARTs */ |
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81 .TX_IRDA(Host_RxD2), |
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82 .RX_IRDA(RX_IRDA), |
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83 .TXIR_IRDA(), |
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84 .RXIR_IRDA(GND), |
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85 .SD_IRDA(), |
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86 .TX_MODEM(Host_RxD), |
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87 .RX_MODEM(RX_MODEM), |
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88 .RTS_MODEM(Host_CTS), |
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89 .CTS_MODEM(CTS_MODEM), |
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90 .DSR_LPG(DSR_LPG), |
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91 /* MCSI pins are GPIOs on this board, backlight control */ |
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92 .MCSI_TXD(BL_GPIO9), |
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93 .MCSI_RXD(BL_GPIO10), |
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94 .MCSI_CLK(BL_GPIO11), |
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95 .MCSI_FSYNCH(BL_GPIO12), |
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96 .KBC(KBC), |
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97 .KBR(KBR), |
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98 .BU_PWT(BU_PWT), |
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99 .LT_PWL(LT_PWL), |
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100 .GPIO0(), |
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101 .GPIO1(GPIO1_SPKR), |
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102 .GPIO2(Host_DCD), |
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103 .GPIO3(GPIO3_DTR), |
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104 .GPIO4(), |
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105 .GPIO6(GPIO6_headset), |
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106 .GPIO7_RESETOUT(LCD_RESET), |
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107 .GPIO8(Host_RI), |
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108 .GPIO13(), |
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109 .ADIN1(ADIN1), |
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110 .ADIN2(ADIN2), |
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111 .ADIN3(ADIN3), |
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112 .DAC(), |
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113 .AUXI(AUXI), |
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114 .AUXON(AUXON), |
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115 .AUXOP(AUXOP), |
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116 .EARN(EARN), |
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117 .EARP(EARP), |
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118 .HSMICBIAS(HSMICBIAS), |
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parents:
diff
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119 .HSMICP(HSMICP), |
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venus/src/top/mobile.v written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
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120 .HSO(HSO), |
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parents:
diff
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121 .MICBIAS(MICBIAS), |
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parents:
diff
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122 .MICIN(MICIN), |
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parents:
diff
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123 .MICIP(MICIP), |
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
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124 .LED_A(), |
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parents:
diff
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125 .LED_B(LED_B), |
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parents:
diff
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126 .LED_C(LED_C), |
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Mychaela Falconia <falcon@freecalypso.org>
parents:
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127 .ICTL(ICTL), |
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
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128 .PCHG(PCHG), |
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parents:
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129 .VBATS(VBATS), |
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parents:
diff
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130 .VCCS(VCCS), |
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parents:
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131 .VCHG(VCHG), |
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parents:
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132 .SIM_IO(SIM_IO), |
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133 .SIM_CLK(SIM_CLK), |
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
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134 .SIM_RST(SIM_RST), |
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Mychaela Falconia <falcon@freecalypso.org>
parents:
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135 .SIM_CD(SIM_CD), |
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Mychaela Falconia <falcon@freecalypso.org>
parents:
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136 .ANTENNA(ANTENNA) |
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parents:
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|
137 ); |
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parents:
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138 |
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parents:
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139 /* battery or lab bench power input */ |
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140 battery batt (.VBAT(VBAT), |
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Mychaela Falconia <falcon@freecalypso.org>
parents:
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141 .GND(GND), |
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parents:
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142 .Third_pin(ADIN2) |
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parents:
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|
143 ); |
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parents:
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144 |
32
85fbd582af88
Venus src: charging circuit captured
Mychaela Falconia <falcon@freecalypso.org>
parents:
19
diff
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|
145 /* charging circuit */ |
85fbd582af88
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parents:
19
diff
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146 charging_circuit chg ( .GND(GND), |
85fbd582af88
Venus src: charging circuit captured
Mychaela Falconia <falcon@freecalypso.org>
parents:
19
diff
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|
147 .VCHG(VCHG), |
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Mychaela Falconia <falcon@freecalypso.org>
parents:
19
diff
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|
148 .VBAT(VBAT), |
85fbd582af88
Venus src: charging circuit captured
Mychaela Falconia <falcon@freecalypso.org>
parents:
19
diff
changeset
|
149 .ICTL(ICTL), |
85fbd582af88
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Mychaela Falconia <falcon@freecalypso.org>
parents:
19
diff
changeset
|
150 .PCHG(PCHG), |
85fbd582af88
Venus src: charging circuit captured
Mychaela Falconia <falcon@freecalypso.org>
parents:
19
diff
changeset
|
151 .VCCS(VCCS), |
85fbd582af88
Venus src: charging circuit captured
Mychaela Falconia <falcon@freecalypso.org>
parents:
19
diff
changeset
|
152 .VBATS(VBATS) |
85fbd582af88
Venus src: charging circuit captured
Mychaela Falconia <falcon@freecalypso.org>
parents:
19
diff
changeset
|
153 ); |
34
dfa0d08d8f2b
charging LED circuit captured
Mychaela Falconia <falcon@freecalypso.org>
parents:
32
diff
changeset
|
154 charging_led chg_led (.VCHG(VCHG), .LEDC(LED_C)); |
32
85fbd582af88
Venus src: charging circuit captured
Mychaela Falconia <falcon@freecalypso.org>
parents:
19
diff
changeset
|
155 |
19
ae08caf957d7
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
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156 /* Calypso UART inputs */ |
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parents:
diff
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|
157 calypso_uart_in uart ( .GND(GND), |
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
158 .VBAT(VBAT), |
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
159 .Vio(Vio), |
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
160 .Host_TxD(Host_TxD), |
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
161 .Host_RTS(Host_RTS), |
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
162 .Host_DTR(Host_DTR), |
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
163 .Host_TxD2(Host_TxD2), |
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
164 .RX_MODEM(RX_MODEM), |
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
165 .CTS_MODEM(CTS_MODEM), |
ae08caf957d7
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
166 .GPIO_DTR(GPIO3_DTR), |
ae08caf957d7
venus/src/top/mobile.v written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
167 .RX_IRDA(RX_IRDA) |
ae08caf957d7
venus/src/top/mobile.v written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
168 ); |
ae08caf957d7
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
169 |
ae08caf957d7
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
170 /* JTAG interface */ |
ae08caf957d7
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
171 jtag_if jtag_if (.GND(GND), |
ae08caf957d7
venus/src/top/mobile.v written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
172 .Vio(Vio), |
ae08caf957d7
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
173 .nTESTRESET(nTESTRESET), |
ae08caf957d7
venus/src/top/mobile.v written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
174 .TDI(TDI), |
ae08caf957d7
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
175 .TCK(TCK), |
ae08caf957d7
venus/src/top/mobile.v written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
176 .TMS(TMS), |
ae08caf957d7
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
177 .TDO(TDO) |
ae08caf957d7
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
178 ); |
ae08caf957d7
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
179 |
ae08caf957d7
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
180 /* SIM socket */ |
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
181 sim_socket_block sim (.GND(GND), |
ae08caf957d7
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
182 .Vio(Vio), |
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
183 .VSIM(VSIM), |
ae08caf957d7
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
184 .SIM_CLK(SIM_CLK), |
ae08caf957d7
venus/src/top/mobile.v written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
185 .SIM_RST(SIM_RST), |
ae08caf957d7
venus/src/top/mobile.v written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
186 .SIM_IO(SIM_IO), |
ae08caf957d7
venus/src/top/mobile.v written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
187 .SIM_CD(SIM_CD) |
ae08caf957d7
venus/src/top/mobile.v written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
188 ); |
ae08caf957d7
venus/src/top/mobile.v written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
189 |
ae08caf957d7
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
190 /* antenna interface */ |
ae08caf957d7
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
191 sma_wrap SMA (.Center(ANTENNA), .Shell(GND)); |
ae08caf957d7
venus/src/top/mobile.v written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
192 |
ae08caf957d7
venus/src/top/mobile.v written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
193 endmodule |