FreeCalypso > hg > freecalypso-schem2
annotate venus/src/core/rfmatch_fem2rita_dcs.v @ 16:3d5c40988a6b
Venus src: add 74LVC1G04 inverting buffer for SIM_CD
author | Mychaela Falconia <falcon@freecalypso.org> |
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date | Fri, 19 Nov 2021 20:35:10 +0000 |
parents | 3ed0f7a9c489 |
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rev | line source |
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9
3ed0f7a9c489
Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
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1 /* RF Rx path from quadband FEM to Rita, DCS band, per Leonardo schematics */ |
3ed0f7a9c489
Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2 |
3ed0f7a9c489
Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
3 module rfmatch_fem2rita_dcs (In_neg, In_pos, Out_neg, Out_pos); |
3ed0f7a9c489
Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
4 |
3ed0f7a9c489
Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
5 input In_neg, In_pos; |
3ed0f7a9c489
Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
6 output Out_neg, Out_pos; |
3ed0f7a9c489
Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
7 |
3ed0f7a9c489
Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
8 inductor L607 (In_neg, Out_neg); |
3ed0f7a9c489
Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
9 inductor L608 (In_pos, Out_pos); |
3ed0f7a9c489
Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
10 |
3ed0f7a9c489
Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
11 capacitor C699 (Out_neg, Out_pos); |
3ed0f7a9c489
Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
12 |
3ed0f7a9c489
Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
13 endmodule |