FreeCalypso > hg > freecalypso-schem2
annotate venus/src/usb/usb_xtal_wrap.v @ 94:4502eec1e805
D405: use Nexperia part sourced from Digi-Key direct
The previously selected part was from a Digi-Key marketplace vendor,
and they seem to not actually have that part, as the order has been
in limbo for over a month - so I put in the time and effort to look
around, and found a readily available equivalent part from Nexperia.
author | Mychaela Falconia <falcon@freecalypso.org> |
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date | Tue, 11 Jan 2022 19:11:22 +0000 |
parents | 8f3df7a222f5 |
children |
rev | line source |
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9
3ed0f7a9c489
Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
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1 /* |
67
8f3df7a222f5
change USB 6.0 MHz crystal to a smaller part
Mychaela Falconia <falcon@freecalypso.org>
parents:
9
diff
changeset
|
2 * This Verilog module encapsulates the PCB footprint |
8f3df7a222f5
change USB 6.0 MHz crystal to a smaller part
Mychaela Falconia <falcon@freecalypso.org>
parents:
9
diff
changeset
|
3 * for our 6.0 MHz USB crystal. |
9
3ed0f7a9c489
Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
4 */ |
3ed0f7a9c489
Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
5 |
67
8f3df7a222f5
change USB 6.0 MHz crystal to a smaller part
Mychaela Falconia <falcon@freecalypso.org>
parents:
9
diff
changeset
|
6 module usb_xtal_wrap (electrode1, electrode2, GND); |
9
3ed0f7a9c489
Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
7 |
3ed0f7a9c489
Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
8 input electrode1, electrode2, GND; |
3ed0f7a9c489
Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
9 |
67
8f3df7a222f5
change USB 6.0 MHz crystal to a smaller part
Mychaela Falconia <falcon@freecalypso.org>
parents:
9
diff
changeset
|
10 xtal_4pin_pkg xtal (.pin_1(electrode1), |
8f3df7a222f5
change USB 6.0 MHz crystal to a smaller part
Mychaela Falconia <falcon@freecalypso.org>
parents:
9
diff
changeset
|
11 .pin_2(GND), |
8f3df7a222f5
change USB 6.0 MHz crystal to a smaller part
Mychaela Falconia <falcon@freecalypso.org>
parents:
9
diff
changeset
|
12 .pin_3(electrode2), |
8f3df7a222f5
change USB 6.0 MHz crystal to a smaller part
Mychaela Falconia <falcon@freecalypso.org>
parents:
9
diff
changeset
|
13 .pin_4(GND) |
8f3df7a222f5
change USB 6.0 MHz crystal to a smaller part
Mychaela Falconia <falcon@freecalypso.org>
parents:
9
diff
changeset
|
14 ); |
9
3ed0f7a9c489
Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
15 |
3ed0f7a9c489
Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
16 endmodule |