FreeCalypso > hg > freecalypso-schem2
annotate venus/src/usb/regulator_with_caps.v @ 82:541b55e6bf47
add UART rescue header
author | Mychaela Falconia <falcon@freecalypso.org> |
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date | Wed, 08 Dec 2021 05:00:50 +0000 |
parents | 4722b265cb8c |
children |
rev | line source |
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24
4722b265cb8c
Venus src: USB domain captured
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
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1 module regulator_with_caps (GND, IN, OUT); |
4722b265cb8c
Venus src: USB domain captured
Mychaela Falconia <falcon@freecalypso.org>
parents:
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changeset
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2 |
4722b265cb8c
Venus src: USB domain captured
Mychaela Falconia <falcon@freecalypso.org>
parents:
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changeset
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3 input GND, IN; |
4722b265cb8c
Venus src: USB domain captured
Mychaela Falconia <falcon@freecalypso.org>
parents:
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4 output OUT; |
4722b265cb8c
Venus src: USB domain captured
Mychaela Falconia <falcon@freecalypso.org>
parents:
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changeset
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5 |
4722b265cb8c
Venus src: USB domain captured
Mychaela Falconia <falcon@freecalypso.org>
parents:
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changeset
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6 regulator_ic reg (.IN(IN), |
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Venus src: USB domain captured
Mychaela Falconia <falcon@freecalypso.org>
parents:
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7 .OUT(OUT), |
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Venus src: USB domain captured
Mychaela Falconia <falcon@freecalypso.org>
parents:
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8 .GND(GND), |
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Venus src: USB domain captured
Mychaela Falconia <falcon@freecalypso.org>
parents:
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9 .EN(IN) |
4722b265cb8c
Venus src: USB domain captured
Mychaela Falconia <falcon@freecalypso.org>
parents:
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changeset
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10 ); |
4722b265cb8c
Venus src: USB domain captured
Mychaela Falconia <falcon@freecalypso.org>
parents:
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changeset
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11 |
4722b265cb8c
Venus src: USB domain captured
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
12 capacitor input_cap (IN, GND); |
4722b265cb8c
Venus src: USB domain captured
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
13 capacitor output_cap (OUT, GND); |
4722b265cb8c
Venus src: USB domain captured
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
14 |
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Venus src: USB domain captured
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
15 endmodule |