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annotate venus/src/core/rf_fem_block.v @ 17:5b18183f55bf

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Venus src: SIM socket block captured
author Mychaela Falconia <falcon@freecalypso.org>
date Fri, 19 Nov 2021 20:59:14 +0000
parents 3ed0f7a9c489
children
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9
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
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1 /*
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
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2 * This module encapsulates the RF FEM (quadband M034F) along with the PNP
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
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3 * transistors and R/C footprints to GND for the control lines, and the cap
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
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4 * on the antenna output.
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
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5 */
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
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6
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
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7 module rf_fem_block (GND, VREG3, Ctrl_Tx_Low, Ctrl_Tx_High, Ctrl_Rx_850,
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8 RX_LOW1, RX_LOW2, RX_DCS1, RX_DCS2, RX_PCS1, RX_PCS2,
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
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9 TX_LOW, TX_HIGH, ANT);
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10
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
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11 input GND, VREG3;
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
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12 input Ctrl_Tx_Low, Ctrl_Tx_High, Ctrl_Rx_850;
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
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13
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
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14 output RX_LOW1, RX_LOW2, RX_DCS1, RX_DCS2, RX_PCS1, RX_PCS2;
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
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15 input TX_LOW, TX_HIGH;
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
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16 inout ANT;
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17
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
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18 wire ANT_before_cap;
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
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19 wire V_TX_LOW, V_TX_HIGH, V_RX_850;
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20
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
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21 /* transform control signals through PNP transistors */
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22
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23 transistor_slot PNP_FEM7 (.E(VREG3), .B(Ctrl_Tx_Low), .C(V_TX_LOW));
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24 transistor_slot PNP_FEM8 (.E(VREG3), .B(Ctrl_Tx_High), .C(V_TX_HIGH));
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25 transistor_slot PNP_FEM9 (.E(VREG3), .B(Ctrl_Rx_850), .C(V_RX_850));
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26
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
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27 /* instantiate the M034F */
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28
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
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29 M034F M034F (.ANT(ANT_before_cap),
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30 .GND(GND),
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
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31 .RX_LOW1(RX_LOW1),
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32 .RX_LOW2(RX_LOW2),
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33 .RX_DCS1(RX_DCS1),
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34 .RX_DCS2(RX_DCS2),
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35 .RX_PCS1(RX_PCS1),
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36 .RX_PCS2(RX_PCS2),
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37 .TX_LOW(TX_LOW),
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38 .TX_HIGH(TX_HIGH),
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39 .V_TX_LOW(V_TX_LOW),
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40 .V_TX_HIGH(V_TX_HIGH),
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41 .V_RX_850(V_RX_850)
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42 );
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43
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
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44 capacitor C635 (ANT_before_cap, ANT);
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
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45
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
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46 capacitor C645 (V_TX_LOW, GND);
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47 capacitor C644 (V_TX_HIGH, GND);
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48 capacitor C643 (V_RX_850, GND);
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49
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50 endmodule