FreeCalypso > hg > freecalypso-schem2

annotate venus/src/periph/sim_socket_block.v @ 17:5b18183f55bf

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Venus src: SIM socket block captured
author Mychaela Falconia <falcon@freecalypso.org>
date Fri, 19 Nov 2021 20:59:14 +0000
parents
children d33cb696b335
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5b18183f55bf Venus src: SIM socket block captured
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1 /*
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2 * This module encapsulates the complete SIM socket block:
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3 * the actual socket, the bypass cap and our SIM_CD circuit.
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4 */
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5
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6 module sim_socket_block (GND, Vio, VSIM, SIM_CLK, SIM_RST, SIM_IO, SIM_CD);
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7
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8 input GND, Vio, VSIM;
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9 input SIM_CLK, SIM_RST;
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10 inout SIM_IO;
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11 output SIM_CD;
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13 wire SIM_CD_inverted;
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14
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15 sim_socket_wrap socket (.C1(VSIM),
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16 .C2(SIM_RST),
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17 .C3(SIM_CLK),
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18 .C5(GND),
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19 .C6(VSIM),
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20 .C7(SIM_IO),
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21 .SW1(GND),
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22 .SW2(SIM_CD_inverted)
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23 );
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24
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25 /* cap per Leonardo schematics */
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26 capacitor C306 (VSIM, GND);
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28 /* pull-up on the switch line */
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29 resistor switch_pullup (SIM_CD_inverted, Vio);
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30
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31 /* inverting buffer for SIM_CD */
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32 inv_buffer_74LVC1G04 inv (.GND(GND),
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33 .Vcc(Vio),
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34 .A(SIM_CD_inverted),
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35 .Y(SIM_CD)
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36 );
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37
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38 endmodule