FreeCalypso > hg > freecalypso-schem2
annotate venus/doc/Charging-circuit @ 70:8bc2aa52fd23
manual RESET button new part: 260 g force, shorter actuator
One of the main envisioned use cases for FC Venus is field demonstration:
the board will be carried around, mounted on a sheet of acrylic or somesuch,
it will have a battery and an antenna connected, there will be a test SIM
with active service inserted, and the setup will be ready to demonstrate
as a working phone at a moment's notice. But when a demo is not actively
in progress, the fully assembled setup will be transported around in a big
and loose ESD bag, and it will need to be equivalent to a traditional phone
in its switched-off state: battery present, RTC keeping time, but not
switched on all the time.
Having a RESET button of the same keyswitch type as used for the regular
keypad and PWON would cause a problem for such field transport scenarios:
any spurious press of this button would cause a "misc boot" switch-on.
Short spurious presses of PWON are filtered out by the firmware (automatic
power-off if the button isn't held down long enough), but the same cannot
be done for super-low-level nTESTRESET. However, a button with significantly
greater operating force and a shorter actuator (not sticking out to the same
height as the regular keypad buttons) should be much safer.
author | Mychaela Falconia <falcon@freecalypso.org> |
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date | Thu, 02 Dec 2021 22:40:39 +0000 |
parents | 1d2b57d4f1c9 |
children | cf39d9352394 |
rev | line source |
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intnoconn approach to charging current sense resistor
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1 The battery charging circuit on FC Venus board is the one depicted on page 56 |
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2 of this TI document: |
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3 |
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4 ftp://ftp.freecalypso.org/pub/GSM/Calypso/APN0_120.pdf |
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5 |
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6 Specifically, it is the circuit depicted on the right side of Figure 7-5, the |
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7 circuit with the charging power source at the top and the battery at the bottom. |
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8 Going from net VCHG (output of our charging control switch S701) to net VBAT |
1d2b57d4f1c9
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9 (battery +ve terminal), the charging circuit consists of Q401, D404 and R407 |
1d2b57d4f1c9
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10 strung in series, with R406 adjoining between Q401 and D404. The exact location |
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11 of this circuit on the board will be up to the PCB layout engineer, but we |
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12 expect that all 4 of the just-named components will be placed on the same side |
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13 of the board (either top or bottom), with surface traces (no vias) carrying the |
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14 charging current (500 mA design intent) from each component to the next. It is |
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15 important to note that whichever side of the board this circuit is placed on, |
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16 it will NOT be located inside either of the two shieldcan areas. |
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17 |
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18 Two signal traces VCCS and VBATS will need to run from wherever the charging |
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19 circuit ends up residing on the board to corresponding U202 Iota chip terminals |
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20 inside the baseband core shieldcan. These traces do not carry current, instead |
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21 they are differential inputs to a voltage-measuring ADC, specifically measuring |
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22 the voltage drop across R407 and thus deducing the current that flows through |
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23 the charging circuit at each given moment. |
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24 |
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25 Galvanically VBAT (board-wide battery power distribution) and VBATS (one side |
1d2b57d4f1c9
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26 of the differential pair measuring the voltage across R407) are the same net, |
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27 but we would like them to be seen as two separate nets by our EDA tools, to |
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28 facilitate proper routing. The Mother's idea is to use intnoconn feature of |
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29 pcb-rnd: |
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30 |
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31 http://repo.hu/cgi-bin/pool.cgi?project=pcb-rnd&cmd=show&node=intnoconn |
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32 |
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33 More specifically, the Mother's idea is that the subcircuit representing R407 |
1d2b57d4f1c9
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34 will have 4 terminals rather than 2, with terminal numbers assigned as follows: |
1d2b57d4f1c9
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35 |
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36 Pin 1 = resistor side 1, surface layer |
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37 Pin 2 = resistor side 1, inner layer |
1d2b57d4f1c9
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38 Pin 3 = resistor side 2, surface layer |
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39 Pin 4 = resistor side 2, inner layer |
1d2b57d4f1c9
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40 |
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41 The idea is to include in-pad microvias going one layer down inside the |
1d2b57d4f1c9
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42 subcircuit, and put terminals 2 and 4 on the inner layer. Terminals 1 & 2 will |
1d2b57d4f1c9
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43 form one intnoconn group, and terminals 3 & 4 will form the other intnoconn |
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44 group. Surface traces carrying the charging current will connect to terminals |
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45 1 and 3, whereas sensing nets VCCS and VBATS will connect to terminals 2 and 4 |
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46 on the inner layer. |
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47 |
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48 Our current ueda source implements this idea at the netlist level; creation of |
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49 the corresponding pcb-rnd subcircuit remains TBD. |