FreeCalypso > hg > freecalypso-schem2
annotate venus/src/core/int_vcxo_passive.v @ 70:8bc2aa52fd23
manual RESET button new part: 260 g force, shorter actuator
One of the main envisioned use cases for FC Venus is field demonstration:
the board will be carried around, mounted on a sheet of acrylic or somesuch,
it will have a battery and an antenna connected, there will be a test SIM
with active service inserted, and the setup will be ready to demonstrate
as a working phone at a moment's notice. But when a demo is not actively
in progress, the fully assembled setup will be transported around in a big
and loose ESD bag, and it will need to be equivalent to a traditional phone
in its switched-off state: battery present, RTC keeping time, but not
switched on all the time.
Having a RESET button of the same keyswitch type as used for the regular
keypad and PWON would cause a problem for such field transport scenarios:
any spurious press of this button would cause a "misc boot" switch-on.
Short spurious presses of PWON are filtered out by the firmware (automatic
power-off if the button isn't held down long enough), but the same cannot
be done for super-low-level nTESTRESET. However, a button with significantly
greater operating force and a shorter actuator (not sticking out to the same
height as the regular keypad buttons) should be much safer.
author | Mychaela Falconia <falcon@freecalypso.org> |
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date | Thu, 02 Dec 2021 22:40:39 +0000 |
parents | d0b6c4915397 |
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rev | line source |
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9
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Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
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1 /* |
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Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
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2 * This module captures the mysterious all-passive circuit between Iota's |
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Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
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3 * AFC output and Rita's XIN input as depicted on the Leonardo schematics. |
3ed0f7a9c489
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Mychaela Falconia <falcon@freecalypso.org>
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4 * This circuit defies understanding, but it appears in Openmoko's GSM |
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Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
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5 * modem (unchanged from Leonardo) and that modem works, hence we deem |
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Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
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6 * this voodoo circuit to be suitable for mindless copying w/o understanding... |
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Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
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7 * |
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Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
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8 * Note that C205 is not included here, as it's already been included |
3ed0f7a9c489
Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
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9 * in the abb_block wrapper instead. |
3ed0f7a9c489
Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
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10 */ |
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Mychaela Falconia <falcon@freecalypso.org>
parents:
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11 |
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Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
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12 module int_vcxo_passive (AFC_in, XIN_connection, GND); |
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Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
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13 |
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Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
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14 input AFC_in, GND; |
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Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
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15 inout XIN_connection; |
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Mychaela Falconia <falcon@freecalypso.org>
parents:
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16 |
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Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
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17 wire R217_to_xtal, xtal_to_R211, R211_to_C225; |
3ed0f7a9c489
Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
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18 |
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Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
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19 resistor R217 (AFC_in, R217_to_xtal); |
31
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Venus MCL: use new ipc-diode.pinout, add SS34 for charging
Mychaela Falconia <falcon@freecalypso.org>
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20 varactor_diode D200 (.C(R217_to_xtal), .A(GND)); |
9
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Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
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21 capacitor C226 (R217_to_xtal, GND); |
3ed0f7a9c489
Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
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22 xtal_4pin_pkg xtal (.pin_1(xtal_to_R211), .pin_2(GND), |
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Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
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23 .pin_3(R217_to_xtal), .pin_4(GND)); |
3ed0f7a9c489
Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
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24 resistor R211 (xtal_to_R211, R211_to_C225); |
3ed0f7a9c489
Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
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25 capacitor C224 (R211_to_C225, GND); |
3ed0f7a9c489
Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
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26 capacitor C225 (R211_to_C225, XIN_connection); |
3ed0f7a9c489
Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
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27 |
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Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
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28 endmodule |