FreeCalypso > hg > freecalypso-schem2
annotate venus/src/core/rfmatch_pa2fem_pi.v @ 70:8bc2aa52fd23
manual RESET button new part: 260 g force, shorter actuator
One of the main envisioned use cases for FC Venus is field demonstration:
the board will be carried around, mounted on a sheet of acrylic or somesuch,
it will have a battery and an antenna connected, there will be a test SIM
with active service inserted, and the setup will be ready to demonstrate
as a working phone at a moment's notice. But when a demo is not actively
in progress, the fully assembled setup will be transported around in a big
and loose ESD bag, and it will need to be equivalent to a traditional phone
in its switched-off state: battery present, RTC keeping time, but not
switched on all the time.
Having a RESET button of the same keyswitch type as used for the regular
keypad and PWON would cause a problem for such field transport scenarios:
any spurious press of this button would cause a "misc boot" switch-on.
Short spurious presses of PWON are filtered out by the firmware (automatic
power-off if the button isn't held down long enough), but the same cannot
be done for super-low-level nTESTRESET. However, a button with significantly
greater operating force and a shorter actuator (not sticking out to the same
height as the regular keypad buttons) should be much safer.
author | Mychaela Falconia <falcon@freecalypso.org> |
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date | Thu, 02 Dec 2021 22:40:39 +0000 |
parents | 3ed0f7a9c489 |
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rev | line source |
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9
3ed0f7a9c489
Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
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1 /* RF Tx path from PA to M034F FEM, replicated for high and low bands */ |
3ed0f7a9c489
Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
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2 /* we are going to use a generic pi network topology on FC Venus */ |
3ed0f7a9c489
Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
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3 |
3ed0f7a9c489
Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
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4 module rfmatch_pa2fem_pi (In, Out, GND); |
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Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
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5 |
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Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
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6 input In; |
3ed0f7a9c489
Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
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7 output Out; |
3ed0f7a9c489
Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
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8 input GND; |
3ed0f7a9c489
Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
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9 |
3ed0f7a9c489
Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
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10 rlc_generic series (In, Out); |
3ed0f7a9c489
Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
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11 rlc_generic GND_leg_in (In, GND); |
3ed0f7a9c489
Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
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12 rlc_generic GND_leg_out (Out, GND); |
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Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
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13 |
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Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
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14 endmodule |