FreeCalypso > hg > freecalypso-schem2
annotate venus/src/core/baseband.v @ 23:9f70dc110ad7
venus/src/usb: building blocks from DUART28
author | Mychaela Falconia <falcon@freecalypso.org> |
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date | Sat, 20 Nov 2021 17:48:18 +0000 |
parents | 5ee03a306da3 |
children | ec932276c8e6 |
rev | line source |
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9
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Venus: first version of Verilog for the Calypso core
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1 /* |
3ed0f7a9c489
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2 * This module encapsulates the DBB, the ABB and the connections between |
3ed0f7a9c489
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3 * them. It approximately corresponds to the "200 - Baseband" sheet |
3ed0f7a9c489
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4 * in the original Leonardo schematics. |
3ed0f7a9c489
Venus: first version of Verilog for the Calypso core
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5 */ |
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6 |
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Venus: first version of Verilog for the Calypso core
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7 module baseband (GND, VBAT, VSIM, Vio, Vflash, Vsram, |
3ed0f7a9c489
Venus: first version of Verilog for the Calypso core
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8 PWON, RPWON, nTESTRESET, ON_nOFF, CLKTCXO_IN, |
3ed0f7a9c489
Venus: first version of Verilog for the Calypso core
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9 TDI, TDO, TCK, TMS, |
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Venus: first version of Verilog for the Calypso core
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10 MCU_A, MCU_D, MCU_RnW, MCU_nFWE, MCU_nFOE, MCU_FDP, |
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Venus: first version of Verilog for the Calypso core
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11 MCU_nBLE, MCU_nBHE, MCU_nCS, |
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Venus: first version of Verilog for the Calypso core
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12 SCLK, SDO, SDI_SDA, nSCS0_SCL, nSCS1, |
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Venus: first version of Verilog for the Calypso core
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13 TX_IRDA, RX_IRDA, TXIR_IRDA, RXIR_IRDA, SD_IRDA, |
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Venus: first version of Verilog for the Calypso core
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14 TX_MODEM, RX_MODEM, RTS_MODEM, CTS_MODEM, DSR_LPG, |
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Venus: first version of Verilog for the Calypso core
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15 MCSI_TXD, MCSI_RXD, MCSI_CLK, MCSI_FSYNCH, |
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Venus: first version of Verilog for the Calypso core
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16 KBC, KBR, BU_PWT, LT_PWL, |
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17 GPIO0, GPIO1, GPIO2, GPIO3, GPIO4, GPIO6, GPIO7_RESETOUT, |
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Venus: first version of Verilog for the Calypso core
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18 GPIO8, GPIO13, |
3ed0f7a9c489
Venus: first version of Verilog for the Calypso core
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19 ADIN1, ADIN2, ADIN3, ADIN4, DAC, |
3ed0f7a9c489
Venus: first version of Verilog for the Calypso core
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20 AUXI, AUXON, AUXOP, EARN, EARP, HSMICBIAS, HSMICP, HSO, |
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Venus: first version of Verilog for the Calypso core
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21 MICBIAS, MICIN, MICIP, |
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Venus: first version of Verilog for the Calypso core
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22 LED_A, LED_B, LED_C, |
3ed0f7a9c489
Venus: first version of Verilog for the Calypso core
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23 ICTL, PCHG, VBATS, VCCS, VCHG, |
10
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Venus core: bring out SIM_CD
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9
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24 SIM_IO, SIM_CLK, SIM_RST, SIM_CD, |
9
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25 Analog_IM, Analog_IP, Analog_QM, Analog_QP, AFC, APC, |
3ed0f7a9c489
Venus: first version of Verilog for the Calypso core
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26 TCXOEN, RFEN, TSPCLK, TSPDO, TSPEN_Rita, TSPACT); |
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Venus: first version of Verilog for the Calypso core
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27 |
3ed0f7a9c489
Venus: first version of Verilog for the Calypso core
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28 input GND, VBAT; |
3ed0f7a9c489
Venus: first version of Verilog for the Calypso core
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parents:
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29 output VSIM, Vio, Vflash, Vsram; |
3ed0f7a9c489
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30 |
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Venus: first version of Verilog for the Calypso core
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31 input PWON, RPWON, nTESTRESET; |
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Venus: first version of Verilog for the Calypso core
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32 output ON_nOFF; |
3ed0f7a9c489
Venus: first version of Verilog for the Calypso core
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parents:
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33 |
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Venus: first version of Verilog for the Calypso core
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34 input CLKTCXO_IN; |
3ed0f7a9c489
Venus: first version of Verilog for the Calypso core
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35 |
3ed0f7a9c489
Venus: first version of Verilog for the Calypso core
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36 input TDI, TCK, TMS; |
3ed0f7a9c489
Venus: first version of Verilog for the Calypso core
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37 output TDO; |
3ed0f7a9c489
Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
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38 |
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Venus: first version of Verilog for the Calypso core
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39 output [22:0] MCU_A; |
3ed0f7a9c489
Venus: first version of Verilog for the Calypso core
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40 inout [15:0] MCU_D; |
3ed0f7a9c489
Venus: first version of Verilog for the Calypso core
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41 output MCU_RnW, MCU_nFWE, MCU_nFOE, MCU_FDP, MCU_nBLE, MCU_nBHE; |
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Venus: first version of Verilog for the Calypso core
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42 output [4:0] MCU_nCS; |
3ed0f7a9c489
Venus: first version of Verilog for the Calypso core
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43 |
3ed0f7a9c489
Venus: first version of Verilog for the Calypso core
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44 output SCLK, SDO, nSCS1; |
3ed0f7a9c489
Venus: first version of Verilog for the Calypso core
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45 inout SDI_SDA, nSCS0_SCL; |
3ed0f7a9c489
Venus: first version of Verilog for the Calypso core
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46 |
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Venus: first version of Verilog for the Calypso core
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47 output TX_IRDA, TXIR_IRDA, SD_IRDA, TX_MODEM, RTS_MODEM; |
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Venus: first version of Verilog for the Calypso core
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48 input RX_IRDA, RXIR_IRDA, RX_MODEM, CTS_MODEM; |
3ed0f7a9c489
Venus: first version of Verilog for the Calypso core
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49 inout DSR_LPG; |
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Venus: first version of Verilog for the Calypso core
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50 |
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parents:
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51 output MCSI_TXD; |
3ed0f7a9c489
Venus: first version of Verilog for the Calypso core
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52 input MCSI_RXD; |
3ed0f7a9c489
Venus: first version of Verilog for the Calypso core
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53 inout MCSI_CLK, MCSI_FSYNCH; |
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Venus: first version of Verilog for the Calypso core
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54 |
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55 output [4:0] KBC; |
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Venus: first version of Verilog for the Calypso core
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56 input [4:0] KBR; |
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Venus: first version of Verilog for the Calypso core
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57 output BU_PWT, LT_PWL; |
3ed0f7a9c489
Venus: first version of Verilog for the Calypso core
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58 |
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59 inout GPIO0, GPIO1, GPIO2, GPIO3, GPIO4, GPIO6, GPIO7_RESETOUT, GPIO8, GPIO13; |
3ed0f7a9c489
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60 |
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61 input ADIN1, ADIN2, ADIN3, ADIN4; |
3ed0f7a9c489
Venus: first version of Verilog for the Calypso core
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62 output DAC; |
3ed0f7a9c489
Venus: first version of Verilog for the Calypso core
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63 |
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64 input AUXI; |
3ed0f7a9c489
Venus: first version of Verilog for the Calypso core
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65 output AUXON, AUXOP; |
3ed0f7a9c489
Venus: first version of Verilog for the Calypso core
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66 output EARN, EARP; |
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Venus: first version of Verilog for the Calypso core
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67 output HSMICBIAS, HSO; |
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Venus: first version of Verilog for the Calypso core
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68 input HSMICP; |
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Venus: first version of Verilog for the Calypso core
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69 output MICBIAS; |
3ed0f7a9c489
Venus: first version of Verilog for the Calypso core
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70 input MICIN, MICIP; |
3ed0f7a9c489
Venus: first version of Verilog for the Calypso core
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71 |
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Venus: first version of Verilog for the Calypso core
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72 output LED_A, LED_B, LED_C; |
3ed0f7a9c489
Venus: first version of Verilog for the Calypso core
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73 |
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74 output ICTL, PCHG; |
3ed0f7a9c489
Venus: first version of Verilog for the Calypso core
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75 input VBATS, VCCS, VCHG; |
3ed0f7a9c489
Venus: first version of Verilog for the Calypso core
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76 |
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Venus: first version of Verilog for the Calypso core
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77 output SIM_CLK, SIM_RST; |
3ed0f7a9c489
Venus: first version of Verilog for the Calypso core
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78 inout SIM_IO; |
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Venus core: bring out SIM_CD
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79 input SIM_CD; |
9
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80 |
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81 inout Analog_IM, Analog_IP, Analog_QM, Analog_QP; |
3ed0f7a9c489
Venus: first version of Verilog for the Calypso core
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parents:
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82 output AFC, APC; |
3ed0f7a9c489
Venus: first version of Verilog for the Calypso core
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parents:
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83 output TCXOEN, RFEN, TSPCLK, TSPDO, TSPEN_Rita; |
3ed0f7a9c489
Venus: first version of Verilog for the Calypso core
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84 output [11:0] TSPACT; |
3ed0f7a9c489
Venus: first version of Verilog for the Calypso core
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85 |
3ed0f7a9c489
Venus: first version of Verilog for the Calypso core
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86 /* nets between DBB and ABB */ |
3ed0f7a9c489
Venus: first version of Verilog for the Calypso core
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parents:
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87 wire Vdbb, Vrtc; |
3ed0f7a9c489
Venus: first version of Verilog for the Calypso core
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parents:
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88 wire CLK13M_OUT, CLK32K_OUT, nRESPWON, IT_WAKEUP; |
3ed0f7a9c489
Venus: first version of Verilog for the Calypso core
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89 wire EXT_FIQ, EXT_IRQ; |
3ed0f7a9c489
Venus: first version of Verilog for the Calypso core
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parents:
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90 wire TSPEN_Iota; |
3ed0f7a9c489
Venus: first version of Verilog for the Calypso core
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91 |
3ed0f7a9c489
Venus: first version of Verilog for the Calypso core
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92 /* Baseband serial port */ |
3ed0f7a9c489
Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
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93 wire BSP_dbb2abb_data, BSP_dbb2abb_sync; |
3ed0f7a9c489
Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
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94 wire BSP_abb2dbb_data, BSP_abb2dbb_sync; |
3ed0f7a9c489
Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
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95 |
3ed0f7a9c489
Venus: first version of Verilog for the Calypso core
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parents:
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96 /* Voiceband serial port */ |
3ed0f7a9c489
Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
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97 wire VSP_DL_data, VSP_UL_data; |
3ed0f7a9c489
Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
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98 wire VSP_clock, VSP_sync; |
3ed0f7a9c489
Venus: first version of Verilog for the Calypso core
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parents:
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99 |
3ed0f7a9c489
Venus: first version of Verilog for the Calypso core
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parents:
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100 /* MCU serial port */ |
3ed0f7a9c489
Venus: first version of Verilog for the Calypso core
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parents:
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101 wire USP_dbb2abb_data, USP_abb2dbb_data, USP_enable; |
3ed0f7a9c489
Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
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102 |
3ed0f7a9c489
Venus: first version of Verilog for the Calypso core
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parents:
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103 /* SIM interface at Vio */ |
3ed0f7a9c489
Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
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104 wire DBBSIO, DBBSCLK, DBBSRST; |
3ed0f7a9c489
Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
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105 |
3ed0f7a9c489
Venus: first version of Verilog for the Calypso core
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parents:
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changeset
|
106 /* instantiate the DBB and ABB blocks! */ |
3ed0f7a9c489
Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
107 |
3ed0f7a9c489
Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
108 dbb_block dbb ( .GND(GND), |
3ed0f7a9c489
Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
109 .Vdbb(Vdbb), |
3ed0f7a9c489
Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
110 .Vio(Vio), |
3ed0f7a9c489
Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
111 .Vflash(Vflash), |
3ed0f7a9c489
Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
112 .Vrtc(Vrtc), |
3ed0f7a9c489
Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
113 .TSPCLKX(TSPCLK), |
3ed0f7a9c489
Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
114 .TSPDO(TSPDO), |
3ed0f7a9c489
Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
115 .TSPDI_IO4(GPIO4), |
3ed0f7a9c489
Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
116 .TSPEN[0](TSPEN_Iota), |
3ed0f7a9c489
Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
117 .TSPEN[1](), /* no connect */ |
3ed0f7a9c489
Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
118 .TSPEN[2](TSPEN_Rita), |
3ed0f7a9c489
Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
119 .TSPEN[3](), /* no connect */ |
3ed0f7a9c489
Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
120 .TSPACT(TSPACT), |
3ed0f7a9c489
Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
121 .DATA(MCU_D), |
3ed0f7a9c489
Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
122 .ADD(MCU_A), |
3ed0f7a9c489
Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
123 .RnW(MCU_RnW), |
3ed0f7a9c489
Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
124 .nFWE(MCU_nFWE), |
3ed0f7a9c489
Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
125 .nFOE(MCU_nFOE), |
3ed0f7a9c489
Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
126 .FDP(MCU_FDP), |
3ed0f7a9c489
Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
127 .nBLE(MCU_nBLE), |
3ed0f7a9c489
Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
128 .nBHE(MCU_nBHE), |
3ed0f7a9c489
Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
129 .nCS(MCU_nCS), |
3ed0f7a9c489
Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
130 .SCLK(SCLK), |
3ed0f7a9c489
Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
131 .SDO(SDO), |
3ed0f7a9c489
Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
132 .SDI_SDA(SDI_SDA), |
3ed0f7a9c489
Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
133 .nSCS0_SCL(nSCS0_SCL), |
3ed0f7a9c489
Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
134 .nSCS1(nSCS1), |
3ed0f7a9c489
Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
135 .TX_IRDA(TX_IRDA), |
3ed0f7a9c489
Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
136 .RX_IRDA(RX_IRDA), |
3ed0f7a9c489
Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
137 .TXIR_IRDA(TXIR_IRDA), |
3ed0f7a9c489
Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
138 .RXIR_IRDA(RXIR_IRDA), |
3ed0f7a9c489
Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
139 .SD_IRDA(SD_IRDA), |
3ed0f7a9c489
Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
140 .TX_MODEM(TX_MODEM), |
3ed0f7a9c489
Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
141 .RX_MODEM(RX_MODEM), |
3ed0f7a9c489
Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
142 .RTS_MODEM(RTS_MODEM), |
3ed0f7a9c489
Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
143 .CTS_MODEM(CTS_MODEM), |
3ed0f7a9c489
Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
144 .DSR_LPG(DSR_LPG), |
3ed0f7a9c489
Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
145 .MCSI_TXD(MCSI_TXD), |
3ed0f7a9c489
Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
146 .MCSI_RXD(MCSI_RXD), |
3ed0f7a9c489
Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
147 .MCSI_CLK(MCSI_CLK), |
3ed0f7a9c489
Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
148 .MCSI_FSYNCH(MCSI_FSYNCH), |
3ed0f7a9c489
Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
149 .KBC(KBC), |
3ed0f7a9c489
Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
150 .KBR(KBR), |
3ed0f7a9c489
Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
151 .BU_PWT(BU_PWT), |
3ed0f7a9c489
Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
152 .LT_PWL(LT_PWL), |
3ed0f7a9c489
Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
153 .GPIO[0](GPIO0), |
3ed0f7a9c489
Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
154 .GPIO[1](GPIO1), |
3ed0f7a9c489
Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
155 .GPIO[2](GPIO2), |
3ed0f7a9c489
Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
156 .GPIO[3](GPIO3), |
3ed0f7a9c489
Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
157 .nRESET_OUT_IO7(GPIO7_RESETOUT), |
3ed0f7a9c489
Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
158 .CLKTCXO(CLKTCXO_IN), |
3ed0f7a9c489
Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
159 .CLK32K_OUT(CLK32K_OUT), |
3ed0f7a9c489
Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
160 .CLK13M_OUT(CLK13M_OUT), |
3ed0f7a9c489
Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
161 .nRESPWON(nRESPWON), |
3ed0f7a9c489
Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
162 .EXT_FIQ(EXT_FIQ), |
3ed0f7a9c489
Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
163 .EXT_IRQ(EXT_IRQ), |
3ed0f7a9c489
Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
164 .TCXOEN(TCXOEN), |
3ed0f7a9c489
Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
165 .RFEN(RFEN), |
3ed0f7a9c489
Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
166 .ON_OFF(ON_nOFF), |
3ed0f7a9c489
Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
167 .IT_WAKEUP(IT_WAKEUP), |
3ed0f7a9c489
Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
168 .TDI(TDI), |
3ed0f7a9c489
Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
169 .TDO(TDO), |
3ed0f7a9c489
Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
170 .TCK(TCK), |
3ed0f7a9c489
Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
171 .TMS(TMS), |
3ed0f7a9c489
Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
172 .BFSR(BSP_abb2dbb_sync), |
3ed0f7a9c489
Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
173 .BDR(BSP_abb2dbb_data), |
3ed0f7a9c489
Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
174 .BFSX(BSP_dbb2abb_sync), |
3ed0f7a9c489
Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
175 .BDX(BSP_dbb2abb_data), |
3ed0f7a9c489
Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
176 .BCLKX_IO6(GPIO6), |
3ed0f7a9c489
Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
177 .BCLKR_ARMCLK(GND), |
3ed0f7a9c489
Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
178 .VDX(VSP_DL_data), |
3ed0f7a9c489
Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
179 .VDR(VSP_UL_data), |
3ed0f7a9c489
Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
180 .VFSRX(VSP_sync), |
3ed0f7a9c489
Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
181 .VCLKRX(VSP_clock), |
3ed0f7a9c489
Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
182 .MCUDI(USP_abb2dbb_data), |
3ed0f7a9c489
Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
183 .MCUDO(USP_dbb2abb_data), |
3ed0f7a9c489
Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
184 .MCUEN0(USP_enable), |
3ed0f7a9c489
Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
185 .MCUEN1_IO8(GPIO8), |
3ed0f7a9c489
Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
186 .MCUEN2_IO13(GPIO13), |
3ed0f7a9c489
Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
187 .SIM_IO(DBBSIO), |
3ed0f7a9c489
Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
188 .SIM_CLK(DBBSCLK), |
10
5ee03a306da3
Venus core: bring out SIM_CD
Mychaela Falconia <falcon@freecalypso.org>
parents:
9
diff
changeset
|
189 .SIM_RST(DBBSRST), |
5ee03a306da3
Venus core: bring out SIM_CD
Mychaela Falconia <falcon@freecalypso.org>
parents:
9
diff
changeset
|
190 .SIM_CD(SIM_CD) |
9
3ed0f7a9c489
Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
191 ); |
3ed0f7a9c489
Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
192 |
3ed0f7a9c489
Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
193 abb_block abb ( .GND(GND), |
3ed0f7a9c489
Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
194 .VBAT(VBAT), |
3ed0f7a9c489
Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
195 .VSIM(VSIM), |
3ed0f7a9c489
Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
196 .Vdbb(Vdbb), |
3ed0f7a9c489
Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
197 .Vio(Vio), |
3ed0f7a9c489
Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
198 .Vflash(Vflash), |
3ed0f7a9c489
Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
199 .Vsram(Vsram), |
3ed0f7a9c489
Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
200 .Vrtc(Vrtc), |
3ed0f7a9c489
Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
201 .nRESPWON(nRESPWON), |
3ed0f7a9c489
Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
202 .nTESTRESET(nTESTRESET), |
3ed0f7a9c489
Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
203 .Analog_IM(Analog_IM), |
3ed0f7a9c489
Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
204 .Analog_IP(Analog_IP), |
3ed0f7a9c489
Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
205 .Analog_QM(Analog_QM), |
3ed0f7a9c489
Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
206 .Analog_QP(Analog_QP), |
3ed0f7a9c489
Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
207 .ADIN1(ADIN1), |
3ed0f7a9c489
Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
208 .ADIN2(ADIN2), |
3ed0f7a9c489
Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
209 .ADIN3(ADIN3), |
3ed0f7a9c489
Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
210 .ADIN4(ADIN4), |
3ed0f7a9c489
Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
211 .AFC(AFC), |
3ed0f7a9c489
Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
212 .APC(APC), |
3ed0f7a9c489
Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
213 .AUXI(AUXI), |
3ed0f7a9c489
Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
214 .AUXON(AUXON), |
3ed0f7a9c489
Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
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215 .AUXOP(AUXOP), |
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Venus: first version of Verilog for the Calypso core
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216 .BDR(BSP_dbb2abb_data), |
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Venus: first version of Verilog for the Calypso core
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217 .BDX(BSP_abb2dbb_data), |
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Venus: first version of Verilog for the Calypso core
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218 .BFSR(BSP_dbb2abb_sync), |
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Venus: first version of Verilog for the Calypso core
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219 .BFSX(BSP_abb2dbb_sync), |
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Venus: first version of Verilog for the Calypso core
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220 .CK13M(CLK13M_OUT), |
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Venus: first version of Verilog for the Calypso core
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221 .CK32K(CLK32K_OUT), |
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Venus: first version of Verilog for the Calypso core
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222 .DAC(DAC), |
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Venus: first version of Verilog for the Calypso core
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223 .DBBSCK(DBBSCLK), |
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Venus: first version of Verilog for the Calypso core
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224 .DBBSIO(DBBSIO), |
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Venus: first version of Verilog for the Calypso core
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225 .DBBSRST(DBBSRST), |
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Venus: first version of Verilog for the Calypso core
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226 .EARN(EARN), |
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Venus: first version of Verilog for the Calypso core
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227 .EARP(EARP), |
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Venus: first version of Verilog for the Calypso core
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228 .HSMICBIAS(HSMICBIAS), |
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Venus: first version of Verilog for the Calypso core
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229 .HSMICP(HSMICP), |
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Venus: first version of Verilog for the Calypso core
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230 .HSO(HSO), |
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Venus: first version of Verilog for the Calypso core
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231 .ICTL(ICTL), |
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Venus: first version of Verilog for the Calypso core
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232 .INT1(EXT_FIQ), |
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Venus: first version of Verilog for the Calypso core
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233 .INT2(EXT_IRQ), |
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Venus: first version of Verilog for the Calypso core
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234 .ITWAKEUP(IT_WAKEUP), |
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Venus: first version of Verilog for the Calypso core
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235 .LED_A(LED_A), |
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Venus: first version of Verilog for the Calypso core
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236 .LED_B(LED_B), |
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Venus: first version of Verilog for the Calypso core
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237 .LED_C(LED_C), |
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Venus: first version of Verilog for the Calypso core
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238 .MICBIAS(MICBIAS), |
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Venus: first version of Verilog for the Calypso core
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239 .MICIN(MICIN), |
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Venus: first version of Verilog for the Calypso core
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240 .MICIP(MICIP), |
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Venus: first version of Verilog for the Calypso core
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parents:
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241 .ON_nOFF(ON_nOFF), |
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Venus: first version of Verilog for the Calypso core
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242 .PCHG(PCHG), |
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Venus: first version of Verilog for the Calypso core
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243 .PWON(PWON), |
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Venus: first version of Verilog for the Calypso core
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244 .RPWON(RPWON), |
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Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
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245 .TCK(), /* no connect */ |
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Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
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246 .TDI(), /* no connect */ |
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Venus: first version of Verilog for the Calypso core
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parents:
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247 .TDO(), /* no connect */ |
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Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
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248 .TDR(TSPDO), |
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Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
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249 .TEN(TSPEN_Iota), |
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Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
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250 .TMS(), /* no connect */ |
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Venus: first version of Verilog for the Calypso core
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parents:
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251 .UDR(USP_dbb2abb_data), |
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Venus: first version of Verilog for the Calypso core
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parents:
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252 .UDX(USP_abb2dbb_data), |
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Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
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253 .UEN(USP_enable), |
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Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
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254 .VBATS(VBATS), |
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Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
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255 .VCCS(VCCS), |
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Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
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|
256 .VCHG(VCHG), |
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Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
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|
257 .VCK(VSP_clock), |
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Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
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|
258 .VDR(VSP_DL_data), |
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Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
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|
259 .VDX(VSP_UL_data), |
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Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
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|
260 .VFS(VSP_sync), |
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Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
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|
261 .SIM_IO(SIM_IO), |
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Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
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|
262 .SIM_CLK(SIM_CLK), |
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Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
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|
263 .SIM_RST(SIM_RST) |
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Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
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|
264 ); |
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Venus: first version of Verilog for the Calypso core
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parents:
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|
265 |
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Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
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|
266 /* there needs to be a pull-down resistor on the MCUDI/UDX net */ |
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Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
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|
267 resistor R216 (USP_abb2dbb_data, GND); |
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Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
268 |
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Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
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|
269 endmodule |