FreeCalypso > hg > freecalypso-schem2
annotate venus/src/core/rf_section.v @ 23:9f70dc110ad7
venus/src/usb: building blocks from DUART28
author | Mychaela Falconia <falcon@freecalypso.org> |
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date | Sat, 20 Nov 2021 17:48:18 +0000 |
parents | 3ed0f7a9c489 |
children |
rev | line source |
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3ed0f7a9c489
Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
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1 module rf_section (GND, VBAT_REG, VBAT_PA, Vio, |
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Venus: first version of Verilog for the Calypso core
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2 Analog_IM, Analog_IP, Analog_QM, Analog_QP, AFC, APC, |
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3 TCXOEN, RFEN, TSPCLK, TSPDO, TSPEN_Rita, TSPACT, |
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4 Clock_out_to_DBB, RTEMP_VTEST, ANTENNA); |
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5 |
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6 input GND, VBAT_REG, VBAT_PA, Vio; |
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7 |
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8 inout Analog_IM, Analog_IP, Analog_QM, Analog_QP; |
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Venus: first version of Verilog for the Calypso core
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9 input AFC, APC; |
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Venus: first version of Verilog for the Calypso core
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10 input TCXOEN, RFEN, TSPCLK, TSPDO, TSPEN_Rita; |
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Venus: first version of Verilog for the Calypso core
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11 input [11:0] TSPACT; |
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12 |
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13 output Clock_out_to_DBB, RTEMP_VTEST; |
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14 inout ANTENNA; |
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15 |
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16 /* wires between subblocks */ |
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Venus: first version of Verilog for the Calypso core
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17 wire VREG3; |
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Venus: first version of Verilog for the Calypso core
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18 wire LNAGSMN, LNAGSMP, LNADCSN, LNADCSP, LNAPCSN, LNAPCSP; |
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Venus: first version of Verilog for the Calypso core
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19 wire Rita_LBTXOUT, Rita_HBTXOUT; |
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Venus: first version of Verilog for the Calypso core
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20 wire PA_LB_in, PA_HB_in, PA_LB_out, PA_HB_out; |
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Venus: first version of Verilog for the Calypso core
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21 wire FEM_TX_LB_in, FEM_TX_HB_in; |
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Venus: first version of Verilog for the Calypso core
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22 wire FEMout_to_LNAGSMN, FEMout_to_LNAGSMP; |
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Venus: first version of Verilog for the Calypso core
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23 wire FEMout_to_LNADCSN, FEMout_to_LNADCSP; |
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24 wire FEMout_to_LNAPCSN, FEMout_to_LNAPCSP; |
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25 |
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26 /* instantiate the main subblocks */ |
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27 |
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28 rita_vcxo_int Rita_vcxo (.GND(GND), |
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29 .VBAT(VBAT_REG), |
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30 .VREG3(VREG3), |
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31 .VRIO(Vio), |
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32 .TCXOEN(TCXOEN), |
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33 .RFEN(RFEN), |
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34 .AFC_in(AFC), |
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35 .Clock_out_to_DBB(Clock_out_to_DBB), |
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36 .Ctrl_CLK(TSPCLK), |
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Venus: first version of Verilog for the Calypso core
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37 .Ctrl_DATA(TSPDO), |
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Venus: first version of Verilog for the Calypso core
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38 .Ctrl_STROBE(TSPEN_Rita), |
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Venus: first version of Verilog for the Calypso core
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39 .Ctrl_RESETZ(TSPACT[0]), |
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40 .IN(Analog_IM), |
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41 .IP(Analog_IP), |
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42 .QN(Analog_QM), |
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43 .QP(Analog_QP), |
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44 .LNAGSMN(LNAGSMN), |
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45 .LNAGSMP(LNAGSMP), |
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46 .LNADCSN(LNADCSN), |
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47 .LNADCSP(LNADCSP), |
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48 .LNAPCSN(LNAPCSN), |
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49 .LNAPCSP(LNAPCSP), |
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50 .LBTXOUT(Rita_LBTXOUT), |
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51 .HBTXOUT(Rita_HBTXOUT), |
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52 .DAC(GND), |
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53 .DET1(GND), |
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54 .DET2(GND), |
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55 .APC(), /* no connect */ |
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56 .RTEMP_VTEST(RTEMP_VTEST) |
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57 ); |
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58 |
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59 rf_pa_block PA (.GND(GND), |
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60 .VBAT(VBAT_PA), |
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61 .Band_Select(TSPACT[3]), |
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62 .Tx_Enable(TSPACT[9]), |
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63 .APC_in(APC), |
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64 .LB_RF_in(PA_LB_in), |
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65 .HB_RF_in(PA_HB_in), |
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66 .LB_RF_out(PA_LB_out), |
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67 .HB_RF_out(PA_HB_out) |
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68 ); |
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69 |
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70 rf_fem_block FEM (.GND(GND), |
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71 .VREG3(VREG3), |
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72 .Ctrl_Tx_Low(TSPACT[2]), |
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Venus: first version of Verilog for the Calypso core
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73 .Ctrl_Tx_High(TSPACT[1]), |
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Venus: first version of Verilog for the Calypso core
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74 .Ctrl_Rx_850(TSPACT[4]), |
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Venus: first version of Verilog for the Calypso core
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75 .RX_LOW1(FEMout_to_LNAGSMP), |
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Venus: first version of Verilog for the Calypso core
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76 .RX_LOW2(FEMout_to_LNAGSMN), |
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77 .RX_DCS1(FEMout_to_LNADCSN), |
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Venus: first version of Verilog for the Calypso core
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78 .RX_DCS2(FEMout_to_LNADCSP), |
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79 .RX_PCS1(FEMout_to_LNAPCSN), |
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80 .RX_PCS2(FEMout_to_LNAPCSP), |
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81 .TX_LOW(FEM_TX_LB_in), |
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82 .TX_HIGH(FEM_TX_HB_in), |
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83 .ANT(ANTENNA) |
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84 ); |
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85 |
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86 /* RF magic glue connecting the blocks */ |
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87 |
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88 /* Tx: Rita to PA */ |
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89 rfmatch_rita2pa_lb rita2pa_lb (.In(Rita_LBTXOUT), .Out(PA_LB_in), .GND(GND)); |
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Venus: first version of Verilog for the Calypso core
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90 rfmatch_rita2pa_hb rita2pa_hb (.In(Rita_HBTXOUT), .Out(PA_HB_in), .GND(GND), |
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Venus: first version of Verilog for the Calypso core
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91 .VREG3(VREG3)); |
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92 |
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93 /* Tx: PA to FEM */ |
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94 rfmatch_pa2fem_pi pa2fem_lb (.In(PA_LB_out), .Out(FEM_TX_LB_in), .GND(GND)); |
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Venus: first version of Verilog for the Calypso core
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95 rfmatch_pa2fem_pi pa2fem_hb (.In(PA_HB_out), .Out(FEM_TX_HB_in), .GND(GND)); |
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96 |
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97 /* Rx paths (3) from the FEM to Rita LNA inputs */ |
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98 |
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99 rfmatch_fem2rita_low fem2rita_low (.In_neg(FEMout_to_LNAGSMN), |
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100 .In_pos(FEMout_to_LNAGSMP), |
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101 .Out_neg(LNAGSMN), |
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102 .Out_pos(LNAGSMP) |
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103 ); |
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Venus: first version of Verilog for the Calypso core
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104 rfmatch_fem2rita_dcs fem2rita_dcs (.In_neg(FEMout_to_LNADCSN), |
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105 .In_pos(FEMout_to_LNADCSP), |
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106 .Out_neg(LNADCSN), |
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107 .Out_pos(LNADCSP) |
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108 ); |
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109 rfmatch_fem2rita_pcs fem2rita_pcs (.In_neg(FEMout_to_LNAPCSN), |
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110 .In_pos(FEMout_to_LNAPCSP), |
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111 .Out_neg(LNAPCSN), |
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112 .Out_pos(LNAPCSP) |
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113 ); |
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114 |
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115 endmodule |