FreeCalypso > hg > freecalypso-schem2
annotate venus/doc/USB-and-mobile-domains @ 73:a730e72d4bec
new 3.3V USB LDO regulator part, direct replacement
author | Mychaela Falconia <falcon@freecalypso.org> |
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date | Fri, 03 Dec 2021 07:56:26 +0000 |
parents | 32b848a081a3 |
children | beb6519a3be5 |
rev | line source |
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1 1. Introduction |
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2 |
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3 FC Venus board will consist of two principal circuit domains: the mobile domain |
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4 corresponding to a battery-powered mobile phone and a USB computer interface |
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5 block which becomes the USB domain. The USB domain will be based around FT2232D |
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6 USB to dual UART chip, it will be strictly bus-powered (never taking any power |
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7 from the battery), and its sole purpose is to provide a host computer interface |
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8 to the mobile, i.e., make the two Calypso UARTs accessible via USB. The USB |
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9 domain will get powered only when a host computer (or a USB charger) is |
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10 connected, and will be totally unpowered at all other times, i.e., when the |
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11 board is untethered and runs on battery power like a true mobile phone. |
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12 |
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13 At the top level of circuit hierarchy (see src/top/board.v), our board consists |
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14 of the two principal domains (mobile and USB) interconnected with just a few |
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15 wires: common ground, the set of UART signals going between the two domains, a |
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16 charging power supply rail (user-switched, so charging won't always happen when |
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17 a USB host is connected) and a couple of boot control signals. |
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18 |
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19 2. UART signals between domains |
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20 |
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21 The connection of UART interface signals between USB and mobile domains is |
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22 arguably the most challenging and the most complicated part of our entire |
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23 built-in USB-serial arrangement. The challenges and the circuit complexity |
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24 which we came up with in response to these challenges stem from the need to |
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25 avoid bad things happening in partial power-down scenarios. Most of the |
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26 background information is provided in section 1.12.2 of our FreeCalypso Handset |
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27 Specification (FC-handset-spec in freecalypso-docs), and this document provides |
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28 further details that were elucidated only in the process of capturing the actual |
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29 circuit design for FC Venus. |
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30 |
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31 2.1. Set of signals |
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32 |
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33 The set of UART interface signals implemented on FC Venus will be the same as |
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34 listed in FC Handset Specification section 1.12.1. We have a total of 5 signals |
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35 running from Calypso outputs to FT2232D, and a total of 4 signals running from |
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36 FT2232D to Calypso inputs. |
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37 |
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38 2.2. Buffer ICs |
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39 |
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40 Two Nexperia LVC family buffer ICs will be used on FC Venus for the purpose of |
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41 ferrying our set of UART interface signals between the two domains. These two |
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42 ICs are U401 (74LVC125A) in the mobile domain and U705 (74LVC541A) in the USB |
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43 domain. |
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44 |
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45 U401 is powered from the mobile domain's Vio rail, and it serves only the 4 |
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46 signals running from FT2232D to Calypso inputs, neatly using all 4 slots of |
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47 74LVC125A. This LVC buffer serves as a barrier, preventing feeding of power |
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48 from USB domain outputs into the Calypso+Iota chipset's Vio rail in the PPD |
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49 scenario where a USB host is connected, but the charging switch is off or the |
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50 battery is critically low and undergoing precharge, with the chipset switched |
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51 off. |
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52 |
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53 No corresponding mobile domain buffers will be used for Calypso outputs: these |
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54 5 signals will be connected directly between Calypso pads and the interdomain |
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55 interface, where they will go to U705. |
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56 |
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57 On the USB side, U705 will be powered from a USB domain 3.3V rail, i.e., the |
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58 output of a 3.3V regulator powered from USB. (This USB domain supply will be |
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59 the only part of FC Venus board using 3.3V - there are no regulated voltages |
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60 higher than 2.8V in the mobile domain.) The 8 slots of this 74LVC541A buffer |
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61 are split between 5 serving the Calypso to FT2232D signal direction and the |
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62 other 3 serving FT2232D to Calypso signals. |
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63 |
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64 The purpose of the 5 U705 buffer slots serving the Calypso to FT2232D signal |
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65 direction is to stop the flow of current out of Calypso UART and GPIO outputs |
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66 in the "normal mobile usage" PPD scenario when there is no USB host connected. |
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67 With this buffer present, Calypso UART outputs will "see" a high impedance and |
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68 won't source any battery-drawn current (beyond leakage of about 0.1 uA typical |
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69 per pin, according to Nexperia datasheet), no matter whether the USB domain is |
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70 powered or not. OTOH, if this buffer were omitted and Calypso outputs were |
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71 connected directly to FT2232D inputs, the latter inputs would appear as shorts |
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72 to ground when USB power is absent, putting an unacceptable load on Calypso |
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73 outputs. |
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74 |
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75 The other 3 slots of U705 serve FT2232D-to-Calypso signals TxD, DTR and TxD2. |
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76 On these 3 signals there are pull-up resistors to VBAT in front of U401 inputs |
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77 (see section 2.4), and the U705 buffer's Ioff feature will allow those pull-up |
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78 resistors to work as intended. If these pulled-up-to-VBAT nets going to U401 |
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79 inputs were sourced directly from FT2232D outputs without going through U705, |
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80 the powered-off FT2232D chip's I/O pins would present a lower resistance to GND |
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81 than the pull-up to VBAT, drawing excessive current from the battery and making |
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82 the pull-up ineffective. |
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83 |
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84 There is just one FT2232D-to-Calypso UART interface signal that does not go |
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85 through U705, and it is RTS. It has a pull-down resistor to GND instead of a |
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86 pull-up to VBAT in front of its U401 input. With only 8 signals rather than |
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87 all 9 needing to go through a USB domain LVC buffer, the 8 slots of a single |
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88 74LVC541A IC become sufficient. |
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89 |
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90 2.3. UART signals from Calypso to FT2232D |
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91 |
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92 In the case of these 5 signals running from Calypso outputs to U705 inputs, one |
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93 very noteworthy detail is that there are _no_ pull-up or pull-down resistors on |
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94 these nets. When the Calypso+Iota chipset is switched on, all 5 Calypso outputs |
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95 will be actively driving and there are no problem issues. However, in the PPD |
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96 scenario where a USB host is connected, but the Calypso+Iota chipset is switched |
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97 off (the charging switch is off or the battery is precharging), the absence of |
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98 pull resistors suggests that U705 inputs will be floating, which certainly looks |
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99 bad at first glance. |
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100 |
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101 However, a more detailed analysis shows that floating CMOS inputs aren't bad |
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102 "in principle", but instead they are bad when they can float around the input |
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103 switching threshold, causing potential oscillations and high current draw from |
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104 the buffer's Vcc supply. And in the present case, the Mother's analysis |
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105 suggests that the signals in question won't float around the switching threshold |
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106 - instead we expect them to be sensed as a consistent logic low in the PPD |
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107 scenario in which they appear to float. |
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108 |
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109 In this PPD scenario, the Iota chip's VRIO regulator is off, thus the Vio rail |
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110 will be at 0 V unless something feeds wayward power into it. Calypso chip |
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111 outputs connected to the signal nets under consideration have clamping diodes |
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112 to this Vio rail. Therefore, if a stray voltage somehow accumulates on those |
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113 nets that is high enough to approach the LVC buffer's input switching threshold, |
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114 it will also be high enough to drain to Vio through Calypso I/O pad clamping |
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115 diodes, and ultimately to GND. |
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116 |
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117 What is our reason for not adding pull-up or pull-down resistors to these nets? |
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118 Besides the obvious reason of not wanting to throw even more PCB real estate at |
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119 this already way overcomplicated USB-serial interface arrangement, each of the |
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120 two options (pull-up or pull-down) would introduce its own problems. |
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121 |
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122 The pull-up resistor option has already proven to be problematic on the |
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123 DUART28+Caramel2 combo, particularly in the Luna configuration in which both PPD |
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124 scenarios become real. When the Calypso+Iota chipset is on but there is no USB |
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125 power present, current from Calypso outputs flows backwards through these |
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126 pull-up resistors and feeds into the USB domain's power rail to which these |
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127 resistors are connected. The USB domain output buffer then powers up |
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128 erratically, feeding garbage to Calypso inputs and preventing Calypso from |
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129 entering sleep modes. And in the opposite PPD scenario (USB power present, |
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130 chipset switched off), enough power can flow through these resistors into |
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131 Calypso I/O pad clamping diodes to feed into Vio and cause erratic LED |
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132 behaviour! And on FC Venus we would have the additional problem of not having |
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133 a USB-powered 2.8V regulator, as we don't need it for anything else. |
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134 |
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135 Pull-down resistors to GND would be much less problematic. However, if we use |
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136 a resistor value that is low enough to be better than floating, such as the |
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137 "canonical" 100 kOhm, we would be introducing a *continuous* drain on the |
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138 battery in normal operation. Calypso outputs corresponding to host RxD, RxD2, |
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139 DCD and RI will normally be high, thus each of those would be a 28 uA drain. |
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140 All 4 combine into a 112 uA continuous drain for no good justification, always |
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141 present whether or not there is a USB host connected, unlike the other similar |
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142 drain discussed in section 2.4. Therefore, the Mother's decision is to do away |
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143 with pull resistors in either direction, and hope that my reasoning is correct |
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144 in that we won't get prolonged floating voltages around the input switching |
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145 threshold. |
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146 |
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147 Because these seemingly-floating nets are expected to be sensed as logic low, |
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148 the same logic low will be propagated to FT2232D inputs, which means a break |
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149 condition on RxD and asserted state on all control signals. For this reason |
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150 the Mother's earlier software recommendation still holds: when operating in this |
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151 scenario, only operate on the second UART channel (the data leads only one that |
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152 also has boot controls), and don't open the AT command UART channel except when |
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153 the mobile is switched on and regular operational firmware runs normally. |
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154 |
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155 2.4. Pull-up resistors to VBAT |
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156 |
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157 Experience with Caramel2 boards shows that Calypso UARTs don't like seeing a |
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158 break condition presented to them for extended lengths of time, thus we need to |
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159 design our FC Venus USB-serial interface in such a way that when there is no USB |
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160 host present, Calypso inputs RX_MODEM and RX_IRDA will receive high levels |
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161 (meaning RS-232 idle) rather than low (meaning RS-232 break). Having an |
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162 extended break condition presented to UARTs prevents entry into Calypso sleep |
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163 modes, which is obviously bad. The practical implication is that U401 inputs |
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164 which this buffer propagates to Calypso RX_MODEM and RX_IRDA need to be have |
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165 some kind of mobile domain pull-ups on them, as opposed to floating or pulled |
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166 down. Less critically, we do the same for the DTR signal running from the USB |
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167 domain to the mobile domain - thus DTR will be seen as negated when there is no |
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168 USB host connected. |
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169 |
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170 However, if we were to implement pull-ups to the Calypso+Iota chipset's Vio rail |
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171 on these nets, we would have a problem in the PPD scenario of USB power present, |
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172 chipset switched off: U705 high outputs would feed power into Vio through these |
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173 resistors, potentially causing Calypso peripherals to turn on erratically as |
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174 has been observed on Caramel2 boards. Therefore, we are making a more unusual |
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175 innovation: instead of pull-ups to Vio, we are implementing pull-ups to VBAT, |
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176 i.e., to the unregulated raw positive battery terminal. The resistor value |
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177 chosen by the Mother is 22 kOhm, and the rest of this section explores the |
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178 implications of this unusual design under all expected conditions. |
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179 |
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180 First let us examine what happens in the case of "normal" mobile usage: the |
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181 device is untethered and mobile, powered by the battery, and there is no USB |
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182 host or charger connected. In this case the input voltage seen by U401 will be |
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183 raw VBAT, which will always be higher than its 2.8V supply (but still safely |
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184 below the 5.5 V limit), thus the LVC buffer will sense a good logic high as |
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185 desired. The current drawn from the battery through these pull resistors will |
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186 be the sum of U705 Ioff and U401 Ii, each of which is listed as 0.1 uA typical |
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187 in Nexperia datasheets. The listed worst case specs are 10 uA for Ioff and 5 uA |
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188 for Ii, thus under presumably very rare conditions, we could have a maximum |
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189 current draw of 15 uA per each of the 3 pull-ups. 15 uA times 22 kOhm equals a |
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190 voltage drop of 330 mV, thus U401 inputs will remain at 2.8 V or above (meaning |
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191 no increased Vio supply current draw) with the battery as low as 3.1 V, which |
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192 is below the operational range for the mobile. |
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193 |
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194 Now consider what happens when USB power is plugged in, either a host computer |
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195 or a charger. FT2232D will power up in UART mode and start putting out logic |
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196 high on all of its outputs (the state when no one opens either of the two serial |
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197 ports in host computer software); U705 will also power up and start putting out |
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198 the same logic high on the 3 signal nets going to the mobile domain. At this |
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199 point U705 output pads are no longer in their Ioff state, instead they are in |
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200 the actively driving high state, and Nexperia datasheet says that the voltage |
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201 at these output pins should not exceed Vcc, which is 3.3 V in the present case. |
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202 VBAT can be as high as 4.2 V, thus we are operating the 74LVC541A under somewhat |
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203 adverse conditions. |
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204 |
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205 The undesirable adverse condition is that current will flow through the LVC |
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206 buffer's output p-channel MOSFET (open for driving high) in the wrong direction. |
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207 The maximum magnitude of this current is about 41 uA, computed as |
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208 (4.2-3.3 V) / 22 kOhm. This current magnitude is expected to be far too low to |
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209 damage the 74LVC541A IC (the limiting values Iok spec is 50 mA), thus the only |
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210 remaining concern would be feeding of a higher voltage into the USB domain's |
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211 regulated 3.3V rail. This concern is addressed in the following subsection. |
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212 |
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213 Aside from the issues of reverse current flow through the LVC buffer's output |
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214 p-channel MOSFET, the other concern with this 41 uA current (at maximum VBAT) |
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215 is that this current is drained from the battery. With a total of 3 such |
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216 pull-ups, we expect a total battery drain current of 123 uA at maximum battery |
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217 charge - but this current only turns on when USB power is applied, and the |
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218 current into U705 output pins goes up from 0.1 uA to 41 uA per pin. However, |
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219 when USB power is applied for extended periods of time, it is usually done for |
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220 the purpose of charging the battery, and the charging current of 500 mA far |
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221 exceeds the drain current of 123 uA. In order for the battery to not be |
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222 charging when USB power is present, the system would have to be in one of two |
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223 other states: either the user connected USB for computer interface purposes and |
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224 not for charging (the charging switch is off), or the charge cycle finished but |
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225 the user hasn't unplugged the charger yet. Both of these conditions are not |
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226 expected to persist for unreasonably long time spans, hence the Mother deems it |
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227 acceptable to impose this 123 uA battery drain during times of active computer |
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228 interfacing. |
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229 |
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230 In the case when the charging switch is on and the charging cycle has finished, |
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231 it is also important to consider that Iota ABB sleep is prevented for as long as |
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232 VCHG remains applied to the chipset, which holds whenever USB power is present |
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233 and the charging switch is on. In this state (charging cycle finished, but VCHG |
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234 not removed yet) Calypso can enter deep sleep (the main VCXO is stopped), but |
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235 Iota ABB sleep is prevented. According to TI's APN2_110.pdf document, the |
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236 difference in battery power draw between deep and "superdeep" sleep modes is |
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237 about 600 uA - thus leaving the charger plugged in after charge cycle completion |
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238 causes even more battery drain through this other mechanism than through our |
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239 VBAT pull-up resistors in the USB-serial interface. |
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240 |
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241 Finally, whenever any of the 3 USB domain outputs in question (TxD, DTR or TxD2) |
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242 drives low, the current drawn from VBAT on that net increases from 41 uA to |
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243 about 190 uA at maximum VBAT, computed as 4.2 V / 22 kOhm. However, this |
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244 condition only occurs when the operator does active host computer interfacing |
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245 with software (the main AT command UART needs to be opened in order for DTR to |
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246 go low, and each of the two TxD lines goes low only when the host computer |
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247 actively transmits bytes), thus this increased battery current draw corresponds |
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248 to explicit user activity, rather than something that happens on its own. In |
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249 contrast, typical user activity on an untethered phone involves the LCD and its |
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250 backlight turning on, consuming tens of mA instead of hundreds of uA. |
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251 |
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252 It also needs to be noted that all of these currents are drawn directly from the |
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253 battery without going through Iota LDO regulators, thus none of these uA numbers |
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254 come out of the 1 mA sleep mode Vio current budget. |
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255 |
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256 2.4.1. USB domain 3.3V load resistor |
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257 |
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258 One concern raised in the analysis of VBAT pull-ups is that when current flows |
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259 from the battery into the USB domain's P_3V3 rail through U705 outputs in |
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260 reverse, the effect may be to raise that rail above 3.3 V. To prevent this |
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261 effect, the Mother's idea is to add a load resistor to the USB domain, a |
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262 3.3 kOhm load permanently placed between P_3V3 and GND, producing a permanent |
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263 1 mA draw from USB, going through our 3.3V regulator. For comparison, FT2232D |
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264 is said to draw about 30 mA of supply current, although the datasheet does not |
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265 specify how it breaks down between Vcc and Vccio supply currents, hence most of |
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266 this 30 mA is probably drawn directly from USB 5V, without going through our |
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267 3.3V regulator. The addition of 1 mA to the overall USB current draw can be |
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268 considered insignificant (especially for 500 mA charging, but even for 30 mA |
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269 host computer interfacing), but with a guaranteed load of at least 1 mA on |
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270 P_3V3, any wayward current coming from the battery (123 uA maximum) will always |
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271 be absorbed into this load without raising P_3V3 above its intended 3.3 V. |
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272 |
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273 2.5. Pull-down to GND on Host_RTS |
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274 |
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275 The effect of Host_RTS being sensed as low instead of high when there is no USB |
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276 host connected is that any unsolicited output on the AT command channel will be |
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277 flushed in this no-host-connected state, instead of being buffered in the |
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278 mobile. Given that an end user mobile phone (as opposed to a dedicated cellular |
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279 modem) is expected to be untethered most of the time, having buffered output |
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280 accumulate while waiting for a host computer to be connected "some day" does not |
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281 sound like a good idea, hence having it flushed by unblocked flow control state |
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282 soundly appears to be the better option. And with only 3 out of the 4 FT2232D |
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283 to Calypso signals needing pull-ups to VBAT, only 3 need U705 buffer slots, |
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284 making a single 74LVC541A buffer IC sufficient for both directions in the USB |
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285 domain. |
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286 |
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287 The value of the pull-down resistor on the Host_RTS net (running from FT2232D |
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288 ADBUS2 output to U401 input) will be 47 kOhm. When USB power is applied but no |
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289 one opens the AT command UART channel, FT2232D will drive its RTS output high, |
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290 sourcing about 70 uA of current from its USB 3.3V supply into the pull-down |
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291 resistor - well within FT2232D output current sourcing budget. |
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292 |
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293 3. Boot control signals |
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294 |
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295 The two boot control signals RPWON and nTESTRESET properly belong in the mobile |
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296 domain. They are pulled up to VBAT inside the mobile domain (RPWON is pulled up |
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297 to VBAT inside the Iota chip, nTESTRESET is pulled up to UPR with R208 per |
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298 Leonardo schematics), many other designs don't provide any way at all for these |
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299 signals to be pulled down, but on FC Venus we have a dual OD buffer (74LVC2G07) |
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300 in the USB domain that can pull either signal down on host command. This dual |
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301 OD buffer is little different from a pair of dry contact pushbutton switches |
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302 shorting to GND, thus the two boot control signals don't bring on any of the |
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303 difficulties like those associated with the UART interface. |