FreeCalypso > hg > freecalypso-schem2

annotate venus/src/periph/calypso_uart_in.v @ 73:a730e72d4bec

Find changesets by keywords (author, files, the commit message), revision number or hash, or revset expression.
new 3.3V USB LDO regulator part, direct replacement
author Mychaela Falconia <falcon@freecalypso.org>
date Fri, 03 Dec 2021 07:56:26 +0000
parents d33cb696b335
children
Ignore whitespace changes - Everywhere: Within whitespace: At end of lines:
rev   line source
15
42a02257d457 venus/src/periph/calypso_uart_in.v written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1 /*
42a02257d457 venus/src/periph/calypso_uart_in.v written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
2 * This module encapsulates the mobile power domain buffers
42a02257d457 venus/src/periph/calypso_uart_in.v written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
3 * in front of Calypso UART inputs.
42a02257d457 venus/src/periph/calypso_uart_in.v written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
4 */
42a02257d457 venus/src/periph/calypso_uart_in.v written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
5
42a02257d457 venus/src/periph/calypso_uart_in.v written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
6 module calypso_uart_in (GND, VBAT, Vio,
42a02257d457 venus/src/periph/calypso_uart_in.v written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
7 Host_TxD, Host_RTS, Host_DTR, Host_TxD2,
42a02257d457 venus/src/periph/calypso_uart_in.v written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
8 RX_MODEM, CTS_MODEM, GPIO_DTR, RX_IRDA);
42a02257d457 venus/src/periph/calypso_uart_in.v written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
9
42a02257d457 venus/src/periph/calypso_uart_in.v written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
10 input GND, VBAT, Vio;
42a02257d457 venus/src/periph/calypso_uart_in.v written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
11 input Host_TxD, Host_RTS, Host_DTR, Host_TxD2;
42a02257d457 venus/src/periph/calypso_uart_in.v written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
12 output RX_MODEM, CTS_MODEM, GPIO_DTR, RX_IRDA;
42a02257d457 venus/src/periph/calypso_uart_in.v written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
13
42a02257d457 venus/src/periph/calypso_uart_in.v written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
14 /* U401 buffer common part */
42a02257d457 venus/src/periph/calypso_uart_in.v written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
15 logic_ic_common U401_common (.Vcc(Vio), .GND(GND));
42a02257d457 venus/src/periph/calypso_uart_in.v written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
16
42
d33cb696b335 add missing bypass caps for mobile domain peripherals
Mychaela Falconia <falcon@freecalypso.org>
parents: 26
diff changeset
17 /* bypass capacitor */
d33cb696b335 add missing bypass caps for mobile domain peripherals
Mychaela Falconia <falcon@freecalypso.org>
parents: 26
diff changeset
18 capacitor U401_bypass (Vio, GND);
d33cb696b335 add missing bypass caps for mobile domain peripherals
Mychaela Falconia <falcon@freecalypso.org>
parents: 26
diff changeset
19
15
42a02257d457 venus/src/periph/calypso_uart_in.v written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
20 /* buffer slots */
26
4baae6215619 Venus: reached the point of compiling sverp.unet
Mychaela Falconia <falcon@freecalypso.org>
parents: 15
diff changeset
21 buffer_slot_3state Host_TxD_buffer (.A(Host_TxD), .nOE(GND), .Y(RX_MODEM));
4baae6215619 Venus: reached the point of compiling sverp.unet
Mychaela Falconia <falcon@freecalypso.org>
parents: 15
diff changeset
22 buffer_slot_3state Host_RTS_buffer (.A(Host_RTS), .nOE(GND), .Y(CTS_MODEM));
4baae6215619 Venus: reached the point of compiling sverp.unet
Mychaela Falconia <falcon@freecalypso.org>
parents: 15
diff changeset
23 buffer_slot_3state Host_DTR_buffer (.A(Host_DTR), .nOE(GND), .Y(GPIO_DTR));
4baae6215619 Venus: reached the point of compiling sverp.unet
Mychaela Falconia <falcon@freecalypso.org>
parents: 15
diff changeset
24 buffer_slot_3state Host_TxD2_buffer (.A(Host_TxD2), .nOE(GND), .Y(RX_IRDA));
15
42a02257d457 venus/src/periph/calypso_uart_in.v written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
25
42a02257d457 venus/src/periph/calypso_uart_in.v written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
26 /* pull-ups to VBAT */
42a02257d457 venus/src/periph/calypso_uart_in.v written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
27 resistor Host_TxD_pullup (Host_TxD, VBAT);
42a02257d457 venus/src/periph/calypso_uart_in.v written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
28 resistor Host_DTR_pullup (Host_DTR, VBAT);
42a02257d457 venus/src/periph/calypso_uart_in.v written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
29 resistor Host_TxD2_pullup (Host_TxD2, VBAT);
42a02257d457 venus/src/periph/calypso_uart_in.v written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
30
42a02257d457 venus/src/periph/calypso_uart_in.v written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
31 /* pull-down to GND */
42a02257d457 venus/src/periph/calypso_uart_in.v written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
32 resistor Host_RTS_pulldown (Host_RTS, GND);
42a02257d457 venus/src/periph/calypso_uart_in.v written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
33
42a02257d457 venus/src/periph/calypso_uart_in.v written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
34 endmodule