FreeCalypso > hg > freecalypso-schem2

annotate venus/src/core/abb_block.v @ 27:bd28df303f7b

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Venus MCL: first steps toward binding, data pulled from FCDEV3B and Tango MCLs
author Mychaela Falconia <falcon@freecalypso.org>
date Sun, 21 Nov 2021 02:14:49 +0000
parents 3ed0f7a9c489
children c1256c8757c3
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9
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1 /*
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
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2 * This module encapsulates the Iota ABB chip plus the following:
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
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3 *
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
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4 * - bypass capacitors on the VBAT input and the regulator outputs
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
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5 * - all GND connections
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
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6 * - IBIAS and VREF external components
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
7 * - UPR, VLMEM, VLRTC and everything connected to them
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
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8 * - pull-up of SIM_IO to VSIM
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
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9 * - cap on the AFC output
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
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10 * - RC network joining BDL[IQ][MP] and BUL[IQ][MP]
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
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11 * - VBACKUP resistor to GND in this FC Venus version
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
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12 *
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
13 * All other Iota signals are passed through untouched.
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
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14 */
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
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15
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
16 module abb_block (GND, VBAT, VSIM, Vdbb, Vio, Vflash, Vsram, Vrtc,
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
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17 nRESPWON, nTESTRESET,
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
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18 Analog_IM, Analog_IP, Analog_QM, Analog_QP,
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
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19 ADIN1, ADIN2, ADIN3, ADIN4, AFC, APC, AUXI, AUXON, AUXOP,
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
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20 BDR, BDX, BFSR, BFSX, CK13M, CK32K, DAC, DBBSCK, DBBSIO,
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
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21 DBBSRST, EARN, EARP,
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
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22 HSMICBIAS, HSMICP, HSO, ICTL, INT1, INT2, ITWAKEUP,
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
23 LED_A, LED_B, LED_C, MICBIAS, MICIN, MICIP, ON_nOFF,
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
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24 PCHG, PWON, RPWON,
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
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25 TCK, TDI, TDO, TDR, TEN, TMS, UDR, UDX, UEN,
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
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26 VBATS, VCCS, VCHG, VCK, VDR, VDX, VFS,
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
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27 SIM_IO, SIM_CLK, SIM_RST);
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
28
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
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29 input GND, VBAT;
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
30 output VSIM, Vdbb, Vio, Vflash, Vsram, Vrtc;
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
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31
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
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32 output nRESPWON;
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
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33 input nTESTRESET;
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
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34
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
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35 inout Analog_IM, Analog_IP, Analog_QM, Analog_QP;
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
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36
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
37 input ADIN1, ADIN2, ADIN3, ADIN4;
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
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38 output AFC, APC, DAC;
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
39
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
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40 input AUXI;
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
41 output AUXON, AUXOP;
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
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42 output EARN, EARP;
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
43 output HSMICBIAS, HSO;
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
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44 input HSMICP;
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
45 output MICBIAS;
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
46 input MICIN, MICIP;
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
47
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
48 input BDR, BFSR;
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
49 output BDX, BFSX;
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
50 input TDR, TEN;
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
51 input UDR, UEN;
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
52 output UDX;
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
53 output VCK, VDX, VFS;
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
54 input VDR;
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
55
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
56 input CK13M, CK32K, ITWAKEUP;
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
57 output INT1, INT2;
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
58 output ON_nOFF;
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
59
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
60 input DBBSCK, DBBSRST;
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
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61 inout DBBSIO;
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
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62
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
63 input PWON, RPWON;
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
64 output ICTL, PCHG;
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
65
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
66 output LED_A, LED_B, LED_C;
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
67
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
68 output SIM_CLK, SIM_RST;
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
69 inout SIM_IO;
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
70
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
71 input TCK, TDI, TMS;
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
72 output TDO;
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
73
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
74 input VBATS, VCCS, VCHG;
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
75
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
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76 /* nets inside this module */
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
77 wire UPR, VLMEM, Vabb;
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
78 wire IBIAS, VREF;
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
79 wire BULIM, BULIP, BULQM, BULQP;
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
80 wire VBACKUP;
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
81
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
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82 /* instantiate the Iota! */
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
83
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
84 iota_100ggm iota (.ADIN1(ADIN1),
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
85 .ADIN2(ADIN2),
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
86 .ADIN3(ADIN3),
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
87 .ADIN4(ADIN4),
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
88 .AFC(AFC),
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
89 .APC(APC),
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
90 .AUXI(AUXI),
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
91 .AUXON(AUXON),
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
92 .AUXOP(AUXOP),
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
93 .BDLIM(Analog_IM),
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
94 .BDLIP(Analog_IP),
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
95 .BDLQM(Analog_QM),
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
96 .BDLQP(Analog_QP),
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
97 .BDR(BDR),
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
98 .BDX(BDX),
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
99 .BFSR(BFSR),
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
100 .BFSX(BFSX),
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
101 .BULIM(BULIM),
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
102 .BULIP(BULIP),
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
103 .BULQM(BULQM),
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
104 .BULQP(BULQP),
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
105 .CK13M(CK13M),
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
106 .CK32K(CK32K),
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
107 .DAC(DAC),
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
108 .DBBSCK(DBBSCK),
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
109 .DBBSIO(DBBSIO),
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
110 .DBBSRST(DBBSRST),
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
111 .EARN(EARN),
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
112 .EARP(EARP),
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
113 .GNDA(GND),
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
114 .GNDAV(GND),
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
115 .GNDD(GND),
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
116 .GNDL1(GND),
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
117 .GNDL2(GND),
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
118 .HSMICBIAS(HSMICBIAS),
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
119 .HSMICP(HSMICP),
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
120 .HSO(HSO),
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
121 .IBIAS(IBIAS),
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
122 .ICTL(ICTL),
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
123 .INT1(INT1),
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
124 .INT2(INT2),
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
125 .ITWAKEUP(ITWAKEUP),
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
126 .LEDA(LED_A),
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
127 .LEDB1(LED_B),
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
128 .LEDB2(LED_B),
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
129 .LEDC(LED_C),
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
130 .MICBIAS(MICBIAS),
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
131 .MICIN(MICIN),
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
132 .MICIP(MICIP),
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
133 .ON_nOFF(ON_nOFF),
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
134 .PCHG(PCHG),
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
135 .PWON(PWON),
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
136 .REFGND(GND),
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
137 .RESPWONz(nRESPWON),
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
138 .RPWON(RPWON),
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
139 .SIMCK(SIM_CLK),
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
140 .SIMIO(SIM_IO),
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
141 .SIMRST(SIM_RST),
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
142 .TCK(TCK),
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
143 .TDI(TDI),
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
144 .TDO(TDO),
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
145 .TDR(TDR),
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
146 .TEN(TEN),
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
147 .TEST3(), /* no connect */
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
148 .TEST4(), /* ditto */
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
149 .TESTRSTz(nTESTRESET),
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
150 .TESTV(), /* no connect */
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
151 .TMS(TMS),
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
152 .UDR(UDR),
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
153 .UDX(UDX),
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
154 .UEN(UEN),
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
155 .UPR(UPR),
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
156 .VBACKUP(VBACKUP),
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
157 .VBAT(VBAT),
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
158 .VBATS(VBATS),
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
159 .VCABB(VBAT),
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
160 .VCCS(VCCS),
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
161 .VCDBB(VBAT),
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
162 .VCHG(VCHG),
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
163 .VCIO1(VBAT),
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
164 .VCIO2(VBAT),
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
165 .VCK(VCK),
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
166 .VCMEM(VBAT),
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
167 .VCRAM(VBAT),
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
168 .VDR(VDR),
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
169 .VDX(VDX),
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
170 .VFS(VFS),
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
171 .VLMEM(VLMEM),
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
172 .VLRTC(GND),
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
173 .VRABB(Vabb),
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
174 .VRDBB(Vdbb),
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
175 .VREF(VREF),
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
176 .VRIO1(Vio),
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
177 .VRIO2(Vio),
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
178 .VRMEM(Vflash),
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
179 .VRRAM(Vsram),
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
180 .VRRTC(Vrtc),
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
181 .VRSIM(VSIM),
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
182 .VSDBB(Vdbb),
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
183 .VXRTC() /* no connect */
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
184 );
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
185
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
186 /* power bypass caps per Leonardo schematics */
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
187
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
188 /* VBAT input */
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
189 capacitor C220 (VBAT, GND);
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
190 capacitor C221 (VBAT, GND);
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
191
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
192 /* regulator outputs */
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
193 capacitor C213 (Vabb, GND);
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
194 capacitor C214 (Vdbb, GND);
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
195 capacitor C215 (Vio, GND);
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
196 capacitor C216 (Vflash, GND);
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
197 capacitor C217 (Vsram, GND);
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
198 capacitor C218 (VSIM, GND);
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
199 capacitor C219 (Vrtc, GND);
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
200
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
201 /* UPR bypass cap */
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
202 capacitor C208 (UPR, GND);
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
203
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
204 /*
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
205 * VLMEM is pulled up to UPR, and we are eliminating the pull-down option
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
206 * on FC Venus - our LCD wiring is incompatible with 1.8V MEMIF.
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
207 */
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
208 resistor R209 (VLMEM, UPR);
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
209
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
210 /* nTESTRESET also needs to be pulled up to UPR */
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
211 resistor R208 (nTESTRESET, UPR);
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
212
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
213 /* IBIAS and VREF */
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
214 resistor R204 (IBIAS, GND);
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
215 capacitor C204 (VREF, GND);
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
216
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
217 /* pull-up on SIM_IO to VSIM */
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
218 resistor R206 (SIM_IO, VSIM);
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
219
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
220 /* cap on AFC output */
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
221 capacitor C205 (AFC, GND);
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
222
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
223 /* RC network joining BDL[IQ][MP] and BUL[IQ][MP] */
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
224
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
225 abb_rc_network abb_rc_network ( .IM_bidir(Analog_IM),
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
226 .IP_bidir(Analog_IP),
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
227 .QM_bidir(Analog_QM),
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
228 .QP_bidir(Analog_QP),
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
229 .IM_abbout(BULIM),
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
230 .IP_abbout(BULIP),
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
231 .QM_abbout(BULQM),
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
232 .QP_abbout(BULQP)
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
233 );
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
234
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
235 /* VBACKUP pull-down to GND */
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
236 resistor VBACKUP_pull_down (VBACKUP, GND);
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
237
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
238 endmodule