FreeCalypso > hg > freecalypso-schem2

annotate venus/src/core/S71PL064J.v @ 36:c1256c8757c3

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eliminate R209 and tie Iota VLMEM directly to UPR We already eliminated R210 (VLMEM pull-down option) earlier, because our simplified LCD power supply and reset line wiring is incompatible with 1.8V MEMIF. But with VLMEM always needing to be high, a pull-up resistor offers no advantage over a direct tie to UPR, so let's eliminate the superfluous resistor.
author Mychaela Falconia <falcon@freecalypso.org>
date Mon, 22 Nov 2021 19:19:59 +0000
parents 3ed0f7a9c489
children
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9
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
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1 module S71PL064J (Flash_Vcc, RAM_Vcc, Vss,
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2 A, DQ, OE, WE,
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3 Flash_CE1, Flash_RST,
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4 Flash_WP_ACC, Flash_ready_busy,
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5 RAM_CE_actlow, RAM_CE_acthigh, RAM_UB, RAM_LB);
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6
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7 input Flash_Vcc, RAM_Vcc, Vss;
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8 input [21:0] A;
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9 inout [15:0] DQ;
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
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10 input OE, WE;
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11 input Flash_CE1, Flash_RST, Flash_WP_ACC;
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12 output Flash_ready_busy;
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13 input RAM_CE_actlow, RAM_CE_acthigh, RAM_UB, RAM_LB;
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14
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15 /* instantiate the package; the mapping of signals to balls is defined here */
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16
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17 pkg_TLC056 pkg (.A2(A[7]),
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18 .A3(RAM_LB),
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19 .A4(Flash_WP_ACC),
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20 .A5(WE),
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21 .A6(A[8]),
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22 .A7(A[11]),
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23 .B1(A[3]),
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24 .B2(A[6]),
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25 .B3(RAM_UB),
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26 .B4(Flash_RST),
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27 .B5(RAM_CE_acthigh),
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28 .B6(A[19]),
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29 .B7(A[12]),
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30 .B8(A[15]),
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31 .C1(A[2]),
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32 .C2(A[5]),
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33 .C3(A[18]),
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34 .C4(Flash_ready_busy),
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35 .C5(A[20]),
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36 .C6(A[9]),
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37 .C7(A[13]),
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38 .C8(A[21]),
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39 .D1(A[1]),
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40 .D2(A[4]),
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41 .D3(A[17]),
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42 .D6(A[10]),
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43 .D7(A[14]),
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44 .D8(), /* no connect */
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45 .E1(A[0]),
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46 .E2(Vss),
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47 .E3(DQ[1]),
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48 .E6(DQ[6]),
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49 .E7(), /* no connect */
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50 .E8(A[16]),
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51 .F1(Flash_CE1),
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52 .F2(OE),
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53 .F3(DQ[9]),
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54 .F4(DQ[3]),
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55 .F5(DQ[4]),
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56 .F6(DQ[13]),
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57 .F7(DQ[15]),
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58 .F8(), /* no connect */
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59 .G1(RAM_CE_actlow),
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60 .G2(DQ[0]),
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61 .G3(DQ[10]),
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62 .G4(Flash_Vcc),
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63 .G5(RAM_Vcc),
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64 .G6(DQ[12]),
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65 .G7(DQ[7]),
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66 .G8(Vss),
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67 .H2(DQ[8]),
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
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68 .H3(DQ[2]),
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Mychaela Falconia <falcon@freecalypso.org>
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69 .H4(DQ[11]),
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70 .H5(), /* no connect */
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71 .H6(DQ[5]),
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72 .H7(DQ[14])
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73 );
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74
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75 endmodule