FreeCalypso > hg > freecalypso-schem2

annotate venus/src/core/int_vcxo_passive.v @ 36:c1256c8757c3

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eliminate R209 and tie Iota VLMEM directly to UPR We already eliminated R210 (VLMEM pull-down option) earlier, because our simplified LCD power supply and reset line wiring is incompatible with 1.8V MEMIF. But with VLMEM always needing to be high, a pull-up resistor offers no advantage over a direct tie to UPR, so let's eliminate the superfluous resistor.
author Mychaela Falconia <falcon@freecalypso.org>
date Mon, 22 Nov 2021 19:19:59 +0000
parents d0b6c4915397
children
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9
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
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1 /*
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
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2 * This module captures the mysterious all-passive circuit between Iota's
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
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3 * AFC output and Rita's XIN input as depicted on the Leonardo schematics.
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
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4 * This circuit defies understanding, but it appears in Openmoko's GSM
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
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5 * modem (unchanged from Leonardo) and that modem works, hence we deem
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
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parents:
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6 * this voodoo circuit to be suitable for mindless copying w/o understanding...
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
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7 *
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
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8 * Note that C205 is not included here, as it's already been included
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
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9 * in the abb_block wrapper instead.
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
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10 */
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
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11
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
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12 module int_vcxo_passive (AFC_in, XIN_connection, GND);
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
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13
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
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14 input AFC_in, GND;
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
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15 inout XIN_connection;
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
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16
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
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17 wire R217_to_xtal, xtal_to_R211, R211_to_C225;
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
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18
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
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19 resistor R217 (AFC_in, R217_to_xtal);
31
d0b6c4915397 Venus MCL: use new ipc-diode.pinout, add SS34 for charging
Mychaela Falconia <falcon@freecalypso.org>
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20 varactor_diode D200 (.C(R217_to_xtal), .A(GND));
9
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
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21 capacitor C226 (R217_to_xtal, GND);
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
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22 xtal_4pin_pkg xtal (.pin_1(xtal_to_R211), .pin_2(GND),
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
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23 .pin_3(R217_to_xtal), .pin_4(GND));
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
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24 resistor R211 (xtal_to_R211, R211_to_C225);
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
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25 capacitor C224 (R211_to_C225, GND);
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
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26 capacitor C225 (R211_to_C225, XIN_connection);
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
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27
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
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28 endmodule