FreeCalypso > hg > freecalypso-schem2

annotate venus/src/core/rf_pa_block.v @ 36:c1256c8757c3

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eliminate R209 and tie Iota VLMEM directly to UPR We already eliminated R210 (VLMEM pull-down option) earlier, because our simplified LCD power supply and reset line wiring is incompatible with 1.8V MEMIF. But with VLMEM always needing to be high, a pull-up resistor offers no advantage over a direct tie to UPR, so let's eliminate the superfluous resistor.
author Mychaela Falconia <falcon@freecalypso.org>
date Mon, 22 Nov 2021 19:19:59 +0000
parents 3ed0f7a9c489
children
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9
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
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1 /*
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2 * This module encapsulates the RF PA along with its power bypass caps
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3 * and the Rs and Cs on the control inputs.
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4 */
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5
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
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6 module rf_pa_block (GND, VBAT, Band_Select, Tx_Enable, APC_in,
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7 LB_RF_in, HB_RF_in, LB_RF_out, HB_RF_out);
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8
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
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9 input GND, VBAT;
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10 input Band_Select, Tx_Enable, APC_in;
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11 input LB_RF_in, HB_RF_in;
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12 output LB_RF_out, HB_RF_out;
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13
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
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14 /*
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
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15 * A little bit of muck with the control inputs, following Leonardo
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
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16 * and Openmoko schematics. On FC Venus we completely eliminate
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17 * R621 and R622.
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18 */
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19
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20 wire APC_after_resistor;
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21
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
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22 resistor R623 (APC_in, APC_after_resistor);
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23 capacitor C648 (APC_after_resistor, GND);
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24 capacitor C656 (Band_Select, GND);
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25
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26 /* instantiate the PA itself */
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27
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
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28 RF3166 PA (.HB_RF_in(HB_RF_in),
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29 .Band_Select(Band_Select),
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30 .Tx_Enable(Tx_Enable),
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31 .Vbatt(VBAT),
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32 .GND(GND),
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33 .Vramp(APC_after_resistor),
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34 .LB_RF_in(LB_RF_in),
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35 .LB_RF_out(LB_RF_out),
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36 .HB_RF_out(HB_RF_out)
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37 );
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38
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39 /* 4 bypass caps per both Leonardo and Openmoko schematics */
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40
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
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41 capacitor C651 (VBAT, GND);
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42 capacitor C652 (VBAT, GND);
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43 capacitor C653 (VBAT, GND);
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44 capacitor C654 (VBAT, GND);
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45
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46 endmodule